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Contents
PIN CONFIGURATIONS ............................................................................................................................................... 4-5
BLOCK DIAGRAM ......................................................................................................................................................... 4-6
DESCRIPTION................................................................................................................................................................. 4-7
Pin Descriptions.............................................................................................................................................................. 4-8
Crystal Oscillator ............................................................................................................................................................ 4-9
AT90S8414 AVR RISC MICROCONTROLLER CPU .......................................................................................... 4-10
Architectural Overview ................................................................................................................................................ 4-10
The General Purpose Register File ............................................................................................................................... 4-11
THE X-REGISTER, Y-REGISTER AND Z-REGISTER ....................................................................................................................................... 4-12
The ALU - Arithmetic Logic Unit................................................................................................................................ 4-13
The Downloadable Flash Program Memory................................................................................................................. 4-13
The SRAM Data Memory - Internal and External ....................................................................................................... 4-13
The Program and Data Addressing Modes ................................................................................................................... 4-15
REGISTER DIRECT, SINGLE REGISTER Rd...................................................................................................................................................... 4-15
REGISTER DIRECT, TWO REGISTERS Rd AND Rr .......................................................................................................................................... 4-15
I/O DIRECT .............................................................................................................................................................................................................. 4-16
SRAM DIRECT........................................................................................................................................................................................................ 4-16
SRAM DIRECT WITH DISPLACEMENT............................................................................................................................................................. 4-16
SRAM/REGISTER INDIRECT ............................................................................................................................................................................... 4-17
SRAM/REGISTER INDIRECT WITH PRE-DECREMENT ................................................................................................................................. 4-17
SRAM/REGISTER INDIRECT WITH POST-INCREMENT ................................................................................................................................ 4-17
CONSTANT ADDRESSING USING THE LPM INSTRUCTION........................................................................................................................ 4-18
DIRECT PROGRAM ADDRESS, JMP AND CALL ............................................................................................................................................. 4-18
INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL ............................................................................................................................... 4-18
RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL............................................................................................................................ 4-19
The EEPROM Data Memory........................................................................................................................................ 4-19
Memory Access Times and Instruction Execution Timing .......................................................................................... 4-19
I/O Memory .................................................................................................................................................................. 4-22
THE STATUS REGISTER - SREG ......................................................................................................................................................................... 4-23
THE STACK POINTER - SP ................................................................................................................................................................................... 4-24
Reset and Interrupt Handling........................................................................................................................................ 4-24
RESET SOURCES ................................................................................................................................................................................................... 4-25
POWER-ON RESET ................................................................................................................................................................................................ 4-26
EXTERNAL RESET ................................................................................................................................................................................................ 4-27
WATCHDOG RESET .............................................................................................................................................................................................. 4-27
INTERRUPT HANDLING ...................................................................................................................................................................................... 4-28
THE GENERAL INTERRUPT MASK REGISTER - GIMSK............................................................................................................................... 4-28
THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK.................................................................................................................. 4-29
THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR ...................................................................................................................... 4-29
EXTERNAL INTERRUPTS .................................................................................................................................................................................... 4-30
INTERRUPT RESPONSE TIME............................................................................................................................................................................. 4-32
MCU CONTROL REGISTER - MCUCR................................................................................................................................................................ 4-32
Sleep Modes.................................................................................................................................................................. 4-32
IDLE MODE............................................................................................................................................................................................................. 4-33
POWER DOWN MODE .......................................................................................................................................................................................... 4-33
TIMER / COUNTERS.................................................................................................................................................... 4-33
The Timer/Counter Prescaler........................................................................................................................................ 4-33
The 8-Bit Timer/Counter0 ............................................................................................................................................ 4-34
THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0 ............................................................................................................................... 4-35
THE TIMER COUNTER 0 - TCNT0....................................................................................................................................................................... 4-36
THE OUTPUT COMPARE REGISTER 0 - OCR0................................................................................................................................................. 4-36
The 16-Bit Timer/Counter1 .......................................................................................................................................... 4-36
THE TIMER/COUNTER1 CONTROL REGISTER A - TCCR1A ........................................................................................................................ 4-39
AT90S8414
Preliminary
4-1
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Summary of Contents for Atmel AT90S8414
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Page 1: Table Of Contents
BLOCK DIAGRAM ................................. 4-6 DESCRIPTION................................. 4-7 Pin Descriptions................................4-8 Crystal Oscillator ................................4-9 AT90S8414 AVR RISC MICROCONTROLLER CPU ..................4-10 Architectural Overview ..............................4-10 The General Purpose Register File ..........................4-11 THE X-REGISTER, Y-REGISTER AND Z-REGISTER ............................4-12 The ALU - Arithmetic Logic Unit..........................4-13 The Downloadable Flash Program Memory......................... - Page 2 THE PORT D DATA DIRECTION REGISTER - DDRD............................4-69 THE PORT D INPUT PINS ADDRESS - PIND ..............................4-69 PORTD AS GENERAL DIGITAL I/O ..................................4-70 ALTERNATE FUNCTIONS FOR PORTD................................4-70 PORTD SCHEMATICS ......................................4-71 MEMORY PROGRAMMING............................4-74 AT90S8414 Preliminary...
- Page 3 D.C. CHARACTERISTICS............................4-80 A.C. CHARACTERISTICS............................4-81 EXTERNAL DATA MEMORY READ CYCLE......................4-81 EXTERNAL MEMORY WRITE CYCLE ........................4-82 XTERNAL CLOCK DRIVE WAVEFORMS ......................4-82 EXTERNAL CLOCK DRIVE............................4-82 ORDERING INFORMATION............................4-83 AT90S8414 REGISTER SUMMARY........................... 4-84 AT90S8414 INSTRUCTION SET SUMMARY......................4-85 Preliminary...
- Page 4 AT90S8414 Preliminary...
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Page 5: Pin Configurations
AT90S8414 Features Utilizes the AV R Enhanced RISC Architecture AV R - High Performance and Low Power RISC Architecture 120 Powerful Instructions - Most Single Clock Cycle Execution Efficient Context Switching Concept 8 Kbytes of In-System Reprogrammable Downloadable Flash SPI Serial Interface for Program Downloading... -
Page 6: Block Diagram
Block Diagram Figure 1: The AT90S8414 Block Diagram AT90S8414 Preliminary... -
Page 7: Description
Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8 bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT90S8414 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. -
Page 8: Pin Descriptions
Port B is an 8-bit bidirectional I/O pins with internal pullups. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current (IIL) if the pullups are activated. Port B also serves the functions of various special features of the AT90S8414 as listed on Page 4-62. Port C (PC7..PC0) Port C is an 8-bit bidirectional I/O port with internal pullups. -
Page 9: Crystal Oscillator
AT90S8414 ALE / PROG ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low- order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the second access cycle. -
Page 10: At90S8414 Avr Risc Microcontroller Cpu
The AT90S8414 AVR RISC microcontroller is upward compatible with the AVR Enhanced RISC Architecture. The programs written for the AT90S8414 MCU are fully compatible with the range of AVR 8-bit MCUs (AT90Sxxxx) with respect to source code and clock cycles for execution. - Page 11 AT90S8414 In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost SRAM addresses, allowing them to be accessed as though they were ordinary memory locations.
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Page 12: The General Purpose Register File
X ,Y and Z registers can be set to index any register in the file. The 256 bytes of SRAM available for general data are implemented as addresses $0020 to $011F. AT90S8414 Preliminary 4-12... -
Page 13: The X-Register, Y-Register And Z-Register
The Downloadable Flash Program Memory The AT90S8414 contains 8K bytes on-chip downloadable Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 4K x 16 words. The Flash memory has an endurance of at least 1000 write/erase cycles. -
Page 14: The Sram Data Memory - Internal And External
The SRAM Data Memory - Internal and External The following figure shows how the AT90S8414 SRAM Memory is organized: Register File SRAM $0000 $0001 $0002 $001D $001E $001F Internal SRAM start $0020 $0021 $011D $011E Internal SRAM end $011F External SRAM start... -
Page 15: The Program And Data Addressing Modes
See the next section for a detailed description of the different addressing modes. The Program and Data Addressing Modes The AT90S8414 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM). This section describes the different addressing modes supported by the AVR architecture. -
Page 16: I/O Direct
A 16-bit SRAM or Register Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. SRAM DIRECT WITH DISPLACEMENT Figure 12: SRAM Direct with Displacement Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction word. AT90S8414 Preliminary 4-16... -
Page 17: Sram/Register Indirect
AT90S8414 SRAM/REGISTER INDIRECT Figure 13: SRAM Indirect Addressing Operand address is the contents of the X, Y or the Z-register. SRAM/REGISTER INDIRECT WITH PRE-DECREMENT Figure 14: SRAM Indirect Addressing With Pre-Decrement The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register. -
Page 18: Constant Addressing Using The Lpm Instruction
Program execution continues at the address immediate in the instruction words. INDIRECT PROGRAM ADDRESSING, IJMP AND ICALL Figure 18: Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z- register). AT90S8414 Preliminary 4-18... -
Page 19: Relative Program Addressing, Rjmp And Rcall
The EEPROM Data Memory The AT90S8414 contains 256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on Page 4-44 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register. - Page 20 Internal Read Signal Internal Data Bus (read) Internal Write Signal Internal Data Bus (write) Figure 22: On-Chip Data SRAM Access Cycles The external data SRAM access is performed in two System Clock cycles as described in Figure 23. AT90S8414 Preliminary 4-20...
- Page 21 AT90S8414 System Clock Ø External Address [7..0] External Address [15..8] External Data Bus (read) External Data Bus (write) Figure 23: External Data SRAM Memory Cycles without Wait State The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 24.
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Page 22: I/O Memory
Note: reserved and unused locations are not shown in the table All the different AT90S8414 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O... -
Page 23: The Status Register - Sreg
AT90S8414 registers within the address range $00 - $19 are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. -
Page 24: The Stack Pointer - Sp
Stack with return from subroutine RET or return from interrupt IRET. Reset and Interrupt Handling The AT90S8414 provides 13 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. -
Page 25: Reset Sources
AT90S8414 Address Labels Code Comments $000 rjmp RESET ; Reset Handle $001 rjmp EXT_INT0 ; IRQ0 Handle $002 rjmp EXT_INT1 ; IRQ1 Handle $003 rjmp TIM1_CAPT ; Timer1 capture Handle $004 rjmp TIM1_COMPA ; Timer1 compareA Handle $005 rjmp TIM1_COMPB ;... -
Page 26: Power-On Reset
Power-On Reset period can be extended. Refer to Figure 28 for a timing example on this. Figure 26: MCU Start-Up, RESET Tied to VCC or Unconnected. Rapidly Rising VCC Figure 27: MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC AT90S8414 Preliminary 4-26... -
Page 27: External Reset
AT90S8414 Figure 28: MCU Start-Up, RESET Controlled Externally EXTERNAL RESET An external reset is generated by a low level on the RESET pin. The pin must be held low for at least two crystal clock cycles. When RESET reaches the Reset Threshold Voltage - V... -
Page 28: Interrupt Handling
Figure 30: Watchdog Reset During Operation INTERRUPT HANDLING The AT90S8414 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK - Timer/Counter Interrupt Mask register. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software must set (one) the I-bit to enable interrupts. -
Page 29: The Timer/Counter Interrupt Mask Register - Timsk
The CompareB Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. Bit 4 - Res : Reserved bit: This bit is a reserved bit in the AT90S8414 and always reads zero. Bit 3 - TICIE1 : Timer/Counter1 Input Capture Interrupt Enable: When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. -
Page 30: External Interrupts
Bit 4 - Res : Reserved bit: This bit is a reserved bit in the AT90S8414 and always reads zero. Bit 3 - ICF1 : - Input Capture Flag 1: The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. -
Page 31: Interrupt Response Time
AT90S8414 INTERRUPT RESPONSE TIME The interrupt response time for all the enabled AVR interrupt is 4 clock cycles. After the 4 clock cycles the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. -
Page 32: Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the instruction following SLEEP, AT90S8414 Preliminary 4-32... -
Page 33: Idle Mode
MCU. Timer / Counters The AT90S8414 provides two general purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have separate prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting. -
Page 34: The 8-Bit Timer/Counter0
Timer/Counter0 contents. The Output Compare functions include optional clearing of the counter on compare matches, and actions on the Output Compare pin 0 on compare matches. The Output Compare pin 0 function makes the Timer/Counter0 useful for PWM (Pulse Width Modulation) functions. AT90S8414 Preliminary 4-34... -
Page 35: The Timer/Counter0 Control Register - Tccr0
Initial value Bits 7,6 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and always read zero. Bits 5,4 - COM01, COM00 : Compare Output Mode0, bit 1 and 0: The COM01 and COM00 control bits determine any output pin action following a compare match in Timer/Counter0. -
Page 36: The Timer Counter 0 - Tcnt0
These bits are reserved bits in the AT90S8414 and always read zero. THE TIMER COUNTER 0 - TCNT0 TCNT0 Read/Write Initial value The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. - Page 37 AT90S8414 Figure 33: Timer/Counter1 Block Diagram The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Register - TCCR1B. The different status flags (overflow, compare match and capture event) and control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B.
- Page 38 If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples before the capture is activated. The sampling clock is the same clock as the clock source selected for the Timer/Counter1. AT90S8414 Preliminary 4-38...
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Page 39: The Timer/Counter1 Control Register A - Tccr1A
Interrupt Enable bits in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed. Bits 3..1 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and always read zero. Bit 0 - PWM1 : Pulse Width Modulator enable: This bit enables the PWM mode for Timer/Counter1. -
Page 40: The Timer/Counter1 - Tcnt1H And Tcnt1L
Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. Bits 5, 4 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and always read zero. Bit 3 - CTC1 : Clear Timer/Counter1 on Compare match: When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. -
Page 41: Timer/Counter1 Output Compare Register - Ocr1Ah And Ocr1Al
AT90S8414 When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. -
Page 42: The Timer/Counter1 Input Capture Register - Icr1H And Icr1L
Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the top - $03FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 36 for an example. AT90S8414 Preliminary 4-42... -
Page 43: The Watchdog Timer
Watchdog Timer. From the Watchdog is reset, eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT90S8414 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to Page 2-27. -
Page 44: The Watchdog Timer Control Register - Wdtcr
Initial value Bits 7..4 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and will always read as zero. Bit 3 - WDE : Watch Dog Enable: When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. -
Page 45: The Eeprom Address Register - Eear
Initial value Bits 7..2 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and will always be read as zero. Bit 1 - EEWE : EEPROM Write Enable: The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. -
Page 46: The Serial Peripheral Interface - Spi
The Serial Peripheral Interface - SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8414 and peripheral devices or between several AT90S8414 devices. The AT90S8414 SPI features include the following: Full-Duplex, 3-Wire Synchronous Data Transfer Master or Slave Operation 5 Mbit/s Bit Frequency (max.) - Page 47 AT90S8414 low to select an individual SPI device as a slave. When PB4( SS ) is set high, the SPI port is deactivated and the PB6(MOSI) pin can be used as an input. Slave/Master mode can also be selected in software by clearing or setting the MSTR bit in the SPI Control Register.
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Page 48: The Spi Control Register - Spcr
Bit 5 - DORD : Data ORDer: When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. AT90S8414 Preliminary 4-48... -
Page 49: The Spi Status Register - Spsr
Bit 5..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and will always read as zero. The SPI interface on the AT90S8414 is also used for program memory and EEPROM downloading or uploading. See Page 4-75 for serial programming and reading. -
Page 50: The Spi Data Register - Spdr
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. The UART The AT90S8414 features a full duplex Universal Asynchronous Receiver and Transmitter (UART). The main features are: Baud rate generator generates any baud rate... - Page 51 AT90S8414 Figure 42: UART Transmitter Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit shift register when: A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately.
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Page 52: Data Reception
8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure 44. AT90S8414 Preliminary 4-52... -
Page 53: Uart Control
AT90S8414 Figure 44: Sampling Received Data When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. -
Page 54: The Uart Control Register - Ucr
The OR bit is cleared (zero) by first reading USR while OR is set and then reading UDR. Bits 2..0 - Res : Reserved bits: These bits are reserved bits in the AT90S8414 and will always read as zero. THE UART CONTROL REGISTER - UCR... -
Page 55: The Baud Rate Generator
AT90S8414 Bit 5 - UDRIE : UART Data Register Empty Interrupt Enable: When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled. -
Page 56: The Uart Baud Rate Register - Ubrr
0.0 UBRR= 3.7 UBRR= 0.0 UBRR= THE UART BAUD RATE REGISTER - UBRR UBRR Read/Write Initial value The UBRR register is an 8-bit read/write register which specifies the UART Baud Rate according to the description on Page 4-55. AT90S8414 Preliminary 4-56... -
Page 57: The Analog Comparator
ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. Bit 6 - Res : Reserved bit: This bit is a reserved bit in the AT90S8414 and will always read as zero. Bit 5 - ACO : Analog Comparator Output: ACO is directly connected to the comparator output. -
Page 58: I/O-Ports
External pullups are required during program verification. When PORT A is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control Register, the alternate settings override the data direction register. AT90S8414 Preliminary 4-58... -
Page 59: The Port A Data Register - Porta
AT90S8414 THE PORT A DATA REGISTER - PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write Initial value THE PORT A DATA DIRECTION REGISTER - DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write Initial value... -
Page 60: Port A Schematics
When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. The Port B pins with alternate functions are shown in the following table: AT90S8414 Preliminary 4-60... -
Page 61: The Port B Data Register - Portb
AT90S8414 Table 17: Port B Pins Alternate Functions Port Pin Alternate Functions T0 (Timer/Counter 0 external counter input) T1 (Timer/Counter 1 external counter input) AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) (SPI Slave Select input) MOSI (SPI Bus Master Output/Slave Input) -
Page 62: Alternate Functions For Portb
T0: Timer/Counter0 counter source: The PB0 pin has to be configured as an input (DDB0 is cleared (zero)) to serve this function. See the timer description for further details. The internal pull up MOS resistor can be activated as described above. AT90S8414 Preliminary 4-62... -
Page 63: Port B Schematics
AT90S8414 PORT B SCHEMATICS Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures. Figure 47: PORTB Schematic Diagram (Pins PB0 and PB1) Preliminary 4-63... - Page 64 Figure 48: PORTB Schematic Diagram (Pins PB2 and PB3) Figure 49: PORTB Schematic Diagram (Pin PB4) AT90S8414 Preliminary 4-64...
- Page 65 AT90S8414 Figure 50: PORTB Schematic Diagram (Pin PB5) Figure 51: PORTB Schematic Diagram (Pin PB6) Preliminary 4-65...
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Page 66: Port C
When PORT C is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control Register, the alternate settings override the data direction register. THE PORT C DATA REGISTER - PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/Write Initial value AT90S8414 Preliminary 4-66... -
Page 67: The Port C Data Direction Register - Ddrc
AT90S8414 THE PORT C DATA DIRECTION REGISTER - DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write Initial value THE PORT C INPUT PINS ADDRESS - PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC Read/Write Initial value... - Page 68 Figure 53: PORTC Schematic Diagram (Pins PC0 - PC7) AT90S8414 Preliminary 4-68...
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Page 69: Port D
AT90S8414 Port D Port D is an 8 bit bi-directional I/O port with internal pullups. Three data memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. -
Page 70: Portd As General Digital I/O
PD3 pin has to be configured as an input (DDD3 is cleared (zero)) to serve this function. The internal pull up MOS resistor can be activated as described above. See the interrupt description for further details, and how to enable the source. AT90S8414 Preliminary 4-70... -
Page 71: Portd Schematics
AT90S8414 INT0 - PORTD, Bit 2: INT0, External Interrupt source 0: The PD2 pin can serve as an external active low interrupt source to the MCU. The PD2 pin has to be configured as an input (DDD2 is cleared (zero)) to serve this function. The internal pull up MOS resistor can be activated as described above. - Page 72 Figure 55: PORTD Schematic Diagram (Pin PD1) Figure 56: PORTD Schematic Diagram (Pins PD2 and PD3) AT90S8414 Preliminary 4-72...
- Page 73 AT90S8414 Figure 57: PORTD Schematic Diagrams (Pin PD4 and PD5) Figure 58: PORTD Schematic Diagram (Pin PD6) Preliminary 4-73...
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Page 74: Memory Programming
Figure 59: PORTD Schematic Diagram (Pin PD7) Memory Programming Program Memory Lock Bits The AT90S8414 MCU provides three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 22. Table 22: Lock Bit Protection Modes... -
Page 75: Programming The Flash And Eeprom
Atmel’s AT90S8414 offers 8K bytes of in-system reprogrammable Flash Program memory and 256 bytes of EEPROM Data memory. The AT90S8414 is normally shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel programming mode and a Low-Voltage Serial programming mode. -
Page 76: Serial Programming Algorithm
SERIAL PROGRAMMING ALGORITHM To program and verify the AT90S8414 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in AT90S8414 Preliminary 4-76... - Page 77 AT90S8414 Table 23): Power-up sequence: Apply power between VCC and GND. pin to ’L’. R E S E T If a crystal is not connected across pins XTAL1 and XTAL2, apply a 1 MHz to 24 MHz clock to the XTAL1 pin and wait for at least 10 milliseconds.
- Page 78 H = 0 - Low byte, 1 - High Byte o = data out i = data in x = don’t care 1 = lock bit 1 2 = lock bit 2 Figure 60: Serial Programming and Verify AT90S8414 Preliminary 4-78...
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Page 79: Programming Characteristics
AT90S8414 When writing serial data to the AT90S8414, data is clocked on the rising edge of CLK. When reading data from the AT90S8414, data is clocked on the falling edge of CLK. See Figure 61 for an explanation. Programming Characteristics... -
Page 80: D.c. Characteristics
71 mA If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2 V. AT90S8414 Preliminary 4-80... -
Page 81: External Data Memory Read Cycle
AT90S8414 A.C. Characteristics Load capacitance for Port A & ALE = 100 pF; Load capacitance for all outputs = 80 pF. 10 MHz Oscillator Variable Oscillator Symbol Parameter Units Oscillator Frequency ALE Pulse Width LHLL Address Valid to ALE Low... -
Page 82: External Memory Write Cycle
VCC = 2.7 V to 6.0 V VCC = 4.0 V to 6.0 V Units Oscillator Frequency CLCL Clock Period 41.7 CLCL High Time 16.7 CHCX Low Time 16.7 CLCX Rise Time 4.15 CLCH Fall Time 4.15 CHCL AT90S8414 Preliminary 4-82... -
Page 83: Ordering Information
AT90S8414 Ordering Information Ordering Code Package Operation Range AT90S8414-JC Commercial AT90S8414-PC 40P6 (0 C to 70 C) AT90S8414-JI Industrial AT90S8414-PI 40P6 (-40 C to 85 C) Package Type 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600” Wide, Plastic Dual in Line Package (PDIP) -
Page 84: At90S8414 Register Summary
AT90S8414 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page SREG 4-23 4-24 4-24 Reserved GIMSK INT1 INT0 4-28 Reserved TIMSK TOIE1 OCIE1A OCIE1B TICIE1 TOIE0 OCIE0 4-29... -
Page 85: At90S8414 Instruction Set Summary
AT90S8414 AT90S8414 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd, Rr Add two Registers Rd + Rr Z,C,N,V,H Rd, Rr Add with Carry two Registers Rd + Rr + C Z,C,N,V,H ADIW Rdl,K Add Immediate to Word... - Page 86 Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation None SLEEP Sleep (see specific descr. for Sleep function) None Watchdog Reset (see specific descr. for WDR/timer) None AT90S8414 Preliminary 4-86...
- Page 87 AT90S8414 Preliminary 4-87...
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