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GOWIN GW5A Series Manuals
Manuals and User Guides for GOWIN GW5A Series. We have
1
GOWIN GW5A Series manual available for free PDF download: Schematics
GOWIN GW5A Series Schematics (31 pages)
FPGA Products
Brand:
GOWIN
| Category:
Semiconductors
| Size: 0 MB
Table of Contents
Table of Contents
4
Contents
5
List of Figures
6
About this Guide
8
Purpose
8
Related Documents
8
Terminology and Abbreviations
8
Table 1-1 Terminology and Abbreviations
8
Support and Feedback
9
Power Supply
10
Overview
10
Power Index
10
Total Power
10
Table 2-1 Arora V FPGA Products Voltage
10
Power-On Time and Sequence
11
Schematic Design Considerations
11
Figure 2-1 Isolate Wave Filtering
11
Table 2-2 Power Supply Ramp Rate
11
Table 2-3 Recommendations for Power Combination
11
Figure 2-2 Isolate with Ferrite Beads
12
Key Configuration Pins
13
Ready, Reconfig_N, Done
13
Table 3-1 RECONFIG_N, READY, DONE Description
13
Figure 3-1 RECONFIG_N, READY, DONE Schematic Reference Circuit
14
Cfgbvs
15
Pudc_B
15
Table 3-2 CFGBVS Description
15
Table 3-3 PUDC_B Description
15
Emcclk
16
Figure 3-2 EMCCLK and CCLK Diagram
16
Table 3-4 EMCCLK Description
16
Configuration Mode
17
Configuration Mode Selection Signal (MODE)
17
Jtag
18
Table 4-1 MODE Signal Definition
18
Table 4-2 Signal Definition of JTAG Configuration Mode
18
Mspi
19
Figure 4-1 Connection Diagram for JTAG Configuration Mode
19
Table 4-3 Signal Definition of MSPI Configuration Mode
19
Figure 4-2 Connection Diagram for Mspix1 Configuration Mode
20
Figure 4-3 Connection Diagram for Mspix2 Configuration Mode
20
Figure 4-4 Connection Diagram for Mspix4 Configuration Mode
20
Sspi
21
Table 4-4 Signal Definition of SSPI Configuration Mode
21
Figure 4-5 Connection Diagram for SSPI Configuration Mode
22
Figure 4-6 Multiple FPGA Connection Diagram
22
Cpu
23
Table 4-5 Signal Definition of CPU Configuration Mode
23
Serial
24
Figure 4-7 Connection Diagram for CPU Mode
24
Figure 4-8 Connection Diagram for SERIAL Configuration Mode
25
Table 4-6 Signal Definition of SERIAL Configuration Mode
25
Clock Pin
26
Overview
26
Table 5-1 Clock Overview
27
Schematic Design Considerations
28
Figure 5-1 FPGA External Crystal Oscillator Circuit
28
Differential Pins
29
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