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ADLINK Technology DAQ-2204 User Manual
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ADLINK Technology DAQ-2204 User Manual

64-/96-ch high performance multi-function data acquisition card
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DAQ/DAQe/PXI-
2204/2205/2206/2208
64-/96-ch High Performance
Multi-Function Data Acquisition Card
User's Manual
Manual Rev.
Revision Date:
Part No:
1.0
Dec. 28, 2023
50M-12258-1000

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Summary of Contents for ADLINK Technology DAQ-2204

  • Page 1 DAQ/DAQe/PXI- 2204/2205/2206/2208 64-/96-ch High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. Revision Date: Dec. 28, 2023 Part No: 50M-12258-1000...

  • Page 2: Revision History

    Revision History Revision Release Date Description of Change(s) 2.01 2007-12-04 Previous release PN: 50-11220-2010 Initial release under new part  number. Added 1.4 Software Support.  Added 2.4 Switch and Jumper  Settings. 2023-12-28 Added Board ID Configuration  note and figure to 2.4.1. Added SSI connector pin assign- ...
  • Page 3 DAQ/DAQe/PXI-220x Series Preface Copyright © 2023 ADLINK Technology Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

  • Page 4: California Proposition 65 Warning

    California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox- ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause...

  • Page 5: Table Of Contents

    DAQ/DAQe/PXI-220x Series Table of Contents Preface ..................iii List of Tables................. vii List of Figures ................ ix 1 Introduction ................ 1 Features................2 Applications ................. 3 Specifications............... 4 Software Support ............... 14 2 Installation ................ 19 Contents of Package ............19 Unpacking ................
  • Page 6 5 Calibration ................. 95 Loading Calibration Constants........... 95 Auto-calibration ..............96 Saving Calibration Constants..........96 Important Safety Instructions..........97 Getting Service ..............99...

  • Page 7: List Of Tables

    DAQ/DAQe/PXI-220x Series List of Tables Table 1-1: Programmabel Input Range..........5 Table 1-2: Bandwidth ................ 6 Table 1-3: System Noise..............7 Table 1-4: CMRR (DC to 60 Hz) ............7 Table 1-5: Settling Time to Full Scale Step........8 Table 2-1: Board ID SW1 DIP Switch Pin Definitions ..... 24 Table 3-1: CN1 Pin Assignment for DAQ/DAQe/PXI-2204/2205/2206 ........
  • Page 8 This page intentionally left blank. viii List of Tables...

  • Page 9: List Of Figures

    DAQ/DAQe/PXI-220x Series List of Figures Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout ....21 Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout ....22 Figure 2-3: PXI-2204/2205/2206/2208 Card Layout ....22 Figure 2-4: Board ID SW1 DIP Switch ........23 Figure 2-5: Enable Board ID Configuration ......... 25 Figure 2-6: DIO Initial Status (JP4) ..........
  • Page 10 Figure 4-23: Mode1 Operation ............73 Figure 4-24: Mode2 Operation ............73 Figure 4-25: Mode3 Operation ............74 Figure 4-26: Mode4 Operation ............75 Figure 4-27: Mode5 Operation ............76 Figure 4-28: Mode6 Operation ............77 Figure 4-29: Mode7 Operation ............77 Figure 4-30: Mode8 Operation ............

  • Page 11: Introduction

    DAQ/DAQe/PXI-220x Series Introduction The DAQ/DAQe/PXI-2204/2205/2206/2208 card is an advanced ® data acquisition card based on the 32-bit PCI or PCI Express architecture. High performance designs and state-of-the-art tech- nology make these cards ideal for data logging and signal analysis applications in medical, process control, etc.

  • Page 12: Features

    1.1 Features The DAQ/DAQe/PXI-2204/2205/2206/2208 advanced data acqui- sition card has the following features: 32-bit PCI bus (DAQ/PXI models) or PCI Express (DAQe  model), plug and play Up to 96 single-ended inputs or 48 differential inputs sup-  porting combinations of SE and DI analog input signals Up to 1024 words analog input Channel Gain Queue config- ...

  • Page 13: Applications

    DAQ/DAQe/PXI-220x Series 1.2 Applications Automotive Testing  Cable Testing  Transient signal measurement   Laboratory Automation  Biotech measurement ...

  • Page 14: Specifications

    1.3 Specifications Analog Input (AI) Programmable channels:  DAQ/DAQe/PXI-2204/2205/2206: 64 single-ended (SE)  or 32 differential input (DI) DAQ/DAQe/PXI-2208: 96 single-ended (SE) or 48 differ-  ential input (DI) Mixing of SE and DI analog signal sources (Software  selectable per channel) A/D converter: ...

  • Page 15: Table 1-1: Programmabel Input Range

    DAQ/DAQe/PXI-220x Series Programmable input range:  Device Bipolar input range Unipolar input range ±10 V — ±5 V 0 to 10 V ±2.5 V 0 to 5 V ±2 V 0 to 4 V ±1.25 V 0 to 2.5 V 2204/ 2208 ±1 V...

  • Page 16: Table 1-2: Bandwidth

    Bandwidth (Typical 25ºC):  Small signal Large signal Device Input range bandwidth bandwidth (-3dB) (1% THD) ±10 V — ±5 V 0 V to 10 V 2000 kHz — ±2.5 V 0 V to 5 V ±1.25 V 0 V to 2.5 V ±2 V 0 V to 4 V 2204/...

  • Page 17: Table 1-3: System Noise

    DAQ/DAQe/PXI-220x Series System Noise (LSBrms, including Quantization, Typical,  25°C) System System Device Input Range Input Range Noise Noise ±10 V 0.95 LSBrms 0 V to 10 V 1.5 LSBrms ±5 V 1.0 LSBrms 0 V to 5 V 1.6 LSBrms 2205 ±2.5 V 1.1 LSBrms...

  • Page 18: Table 1-5: Settling Time To Full Scale Step

    Settling time to full-scale step (Typical, 25°C):  Device Input Range Condition Settling time ±10 V • Multiple channels, multiple ranges. ±5 V 0 to 10 V • All samples in unipolar/ ±2.5 V 0 to 5 V bipolar mode. 1 µs to 0.1% error ±2 V 0 to 4 V...
  • Page 19 DAQ/DAQe/PXI-220x Series Time-base source:  Internal 40 MHz or external clock Input (f : 40 MHz,  : 1 MHz, 50% duty cycle) Trigger modes: Post-trigger, delay-trigger, pre-trigger and  middle-trigger Offset error:  ±50mV max. for DAQ/DAQe/PXI-2204/2208  ±1mV max. for DAQ/DAQe/PXI-2205/2206 ...
  • Page 20 Analog Output (AO) NOTEThe DAQ/DAQe/PXI-2208 card does not support this function. Channels: Two-channel analog voltage output  DA converter: LTC7545 or equivalent  Max update rate: 1 MS/s  Resolution: 12-bit  FIFO buffer size:  512 samples per channel when both channels are ...
  • Page 21 DAQ/DAQe/PXI-220x Series General Purpose Digital I/O (G.P. DIO, 82C55A) Channels: 24 programmable input/output  Compatibility: TTL  Input voltage:  Logic Low: VIL=0.8 V max; IIL=0.2 mA max  High: VIH=2.0 V max; IIH=0.02 mA max  Output voltage:  Low: VOL=0.5 V max;...
  • Page 22 Analog Trigger (A.Trig) Source:  All analog input channels  External analog trigger (EXTATRIG)  Level: ±Full-scale, internal; ±10 V external  Resolution: 8-bit  Slope: Positive or negative (software-selectable)  Hysteresis: Programmable  Bandwidth: 400 kHz  External Analog Trigger Input (EXTATRIG) Input Impedance: ...
  • Page 23 DAQ/DAQe/PXI-220x Series Physical Dimensions:  175mm by 107mm for DAQ-/DAQe-2204/2205/2206/  2208 Standard CompactPCI form factor for PXI-2204/2205/  2206/2208 I/O connector: 68-pin female VHDCI type (e.g. AMP-  787254-1) Power Requirement (typical) +5 VDC  1.3 A for DAQ/DAQe/PXI-2204 ...

  • Page 24: Software Support

    1.4 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from pro- gramming libraries, such as DLLs, for most Windows-based sys- tems, ADLINK also provides drivers for other application environments such as LabVIEW. All software can be downloaded from the ADLINK official website.
  • Page 25 DAQ/DAQe/PXI-220x Series 1.4.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access.
  • Page 26 ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen. 1.4.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package.
  • Page 27 DAQ/DAQe/PXI-220x Series 1.4.3 MAPS/C, C & C++ Support Customers who develop their own programs in C or C++ environ- ments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipu- late the device correctly.
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  • Page 29: Installation

    DAQ/DAQe/PXI-220x Series Installation This chapter describes how to install the DAQ/DAQe/PXI-2204/ 2205/2206/2208 card. The contents of the package and unpacking information that you should be aware of are outlined first. 2.1 Contents of Package In addition to this User's Manual, the package includes the follow- ing items: DAQ/DAQe/PXI-2204/2205/2206/2208 multi-function data ...

  • Page 30: Unpacking

    2.2 Unpacking Your DAQ/DAQe/PXI-2204/2205/2206/2208 card contains elec- tro-static sensitive components that can be easily be damaged by static electricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat. Inspect the card package for obvious damages.

  • Page 31: Card Layout

    DAQ/DAQe/PXI-220x Series 2.3 Card Layout 2.3.1 DAQe-2204/2205/2206/2208 Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout...

  • Page 32: Figure 2-2: Daq-2204/2205/2206/2208 Card Layout

    2.3.2 DAQ-2204/2205/2206/2208 Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout 2.3.3 PXI-2204/2205/2206/2208 Figure 2-3: PXI-2204/2205/2206/2208 Card Layout...

  • Page 33: Switch And Jumper Settings

    DAQ/DAQe/PXI-220x Series 2.4 Switch and Jumper Settings 2.4.1 Board ID (SW1) The DAQ/DAQe-2000 Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are mul- tiple cards on the same platform, this board ID switch is useful for identifying each card’s device number.

  • Page 34: Table 2-1: Board Id Sw1 Dip Switch Pin Definitions

    Pin 1 Pin 2 Pin 3 Pin 4 Board ID Table 2-1: Board ID SW1 DIP Switch Pin Definitions...

  • Page 35: Figure 2-5: Enable Board Id Configuration

    DAQ/DAQe/PXI-220x Series Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select NOTE: NOTE: your Card Type and uncheck Ignore Board ID. See figure below. Figure 2-5: Enable Board ID Configuration...

  • Page 36: Figure 2-6: Dio Initial Status (Jp4)

    2.4.2 DIO Initial Status (JP4) The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below. Disabled Enabled Figure 2-6: DIO Initial Status (JP4)

  • Page 37: Pci Configuration

    DAQ/DAQe/PXI-220x Series 2.5 PCI Configuration 2.5.1 Plug and Play With support for plug and play, the card requests an interrupt num- ber via its PCI controller. The system BIOS responds with an inter- rupt assignment based on the card information and on known system parameters.
  • Page 38 This page intentionally left blank.

  • Page 39: Signal Connections

    DAQ/DAQe/PXI-220x Series Signal Connections This chapter describes DAQ/DAQe/PXI-2204/2205/2206/2208 card connectors and the signal connection between the DAQ/ DAQe/PXI-2204/2205/2206/2208 card and external devices. 3.1 Connectors Pin Assignment The DAQ/DAQe/PXI-2204/2205/2206/2208 card is equipped with two 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input/output, timer/counter signals, etc.

  • Page 40: Table 3-1: Cn1 Pin Assignment For Daq/Daqe/Pxi-2204/2205/2206

    3.1.1 CN1 Connector AI0 (AIH0) (AIL0) AI32 AI1 (AIH1) (AIL1) AI33 AI2 (AIH2) (AIL2) AI34 AI3 (AIH3) (AIL3) AI35 AI4 (AIH4) (AIL4) AI36 AI5 (AIH5) (AIL5) AI37 AI6 (AIH6) (AIL6) AI38 AI7 (AIH7) (AIL7) AI39 AI8 (AIH8) (AIL8) AI40 AI9 (AIH9) 10 (AIL9) AI41 AI10 (AIH10) (AIL10) AI42...

  • Page 41: Table 3-2: Cn1 Pin Assignment For Daq/Daqe/Pxi-2208

    DAQ/DAQe/PXI-220x Series AI0 (AIH0) (AIL0) AI48 AI1 (AIH1) (AIL1) AI49 AI2 (AIH2) (AIL2) AI50 AI3 (AIH3) (AIL3) AI51 AI4 (AIH4) (AIL4) AI52 AI5 (AIH5) (AIL5) AI53 AI6 (AIH6) (AIL6) AI54 AI7 (AIH7) (AIL7) AI55 AISENSE AIGND AI8 (AIH8) 10 (AIL8) AI56 AI9 (AIH9) (AIL9) AI57 AI10 (AIH10) 12...

  • Page 42: Table 3-3: Cn2 Pin Assignment For Daq/Daqe/Pxi-2204/2205/2206

    3.1.2 CN2 Connector DA0OUT AOGND DA1OUT AOGND AOEXTREF AOGND DGND DGND EXTWFTRIG DGND EXTDTRIG DGND SSHOUT SDI0 / DGND* RESERVED SDI1 / DGND* RESERVED SDI2 / DGND* AFI1 SDI3 / DGND* AFI0 DGND GPTC0_SRC DGND GPTC0_GATE 14 DGND GPTC0_UPDOWN DGND GPTC0_OUT DGND GPTC1_SRC...

  • Page 43: Table 3-4: Cn2 Pin Assignment For Daq/Daqe/Pxi-2208

    DAQ/DAQe/PXI-220x Series AI32 (AIH32) (AIL32) AI80 AI33 (AIH33) (AIL33) AI81 AI34 (AIH34) (AIL34) AI82 AI35 (AIH35) (AIL35) AI83 AI36 (AIH36) (AIL36) AI84 AI37 (AIH37) (AIL37) AI85 AI38 (AIH38) (AIL38) AI86 AI39 (AIH39) (AIL39) AI87 EXTATRIG AIGND AI40 (AIH40) 10 (AIL40) AI88 AI41 (AIH41) (AIL41) AI89 AI42 (AIH42) 12...

  • Page 44: Table 3-5: Cn1/Cn2 Signal Description

    CN1/CN2 Connector Signal Description Signal Name Reference Direction Description Analog ground for AI. All three ground references (AIGND, AIGND — — AOGND, and DGND) are connected together on board. • For DAQ/DAQe/PXI-2204/ 2205/2206: Analog Input Channels 0~63. Each channel pair, AI<i, i+32> (I=0..31) can be configured either two single- ended inputs or one differential input pair(marked as...

  • Page 45: Table 3-6: Ssi Connector Pin Assignment

    DAQ/DAQe/PXI-220x Series Signal Name Reference Direction Description Synchronous digital inputs. These SDI<0..3> 4 digital inputs are sampled DGND Input (for 2204 only) simultaneously with the analog signal input. GPTC<0,1>_SRC DGND Input Source of GPTC<0,1> GPTC<0,1>_GATE DGND Input Gate of GPTC<0,1> GPTC<0,1>_OUT DGND Input...

  • Page 46: Table 3-7: Ssi Connector Pin Assignment On Pxi J2

    SSI Connector Signal Description on PXI J2: Sync. Signal PXI J2 location PXI Trigger Bus SSI_TIMEBASE PXI_TRIG4 SSI_ADCONV PXI_TRIG1 SSI_SCAN_START PXI_TRIG3 SSI_AD_TRIG PXI_TRIG5 SSI_DAWR PXI_TRIG2 SSI_DA_START PXI_TRIG0 SSI_DA_TRIG PXI_TRIG6 Table 3-7: SSI Connector Pin Assignment on PXI J2 SSI Connector Signal Description: SSI Timing Signal Setting Function Master Send the TIMEBASE out...

  • Page 47: Analog Input Signal Connection

    DAQ/DAQe/PXI-220x Series 3.2 Analog Input Signal Connection The DAQ/DAQe/PXI-2204/2205/2206/2208 card provides up to 64 single-ended or 32 differential analog input channels. You can fill the Channel Gain Queue to get desired combination of the input signal types. The analog signal can be converted to digital values by the A/D converter.

  • Page 48: Figure 3-1: Floating Source And Rse Input Connections

    signal provides its own reference grounding point and is suit- able for ground-referenced signals. Referenced Single-ended (RSE) Mode In referenced single-ended mode, all input signals are con- nected to the ground provided by the DAQ/DAQe/PXI-2204/ 2205/2206/2208 card. This is suitable for connections with floating signal sources.

  • Page 49: Figure 3-2: Ground-Referenced Sources And Nrse Input

    DAQ/DAQe/PXI-220x Series Input Multipexer Instrumentation Amplifier Ground- Referenced To A/D Signal Source Converter Common- AISENSE n = 0, ...,63 mode noise & Ground potential Figure 3-2: Ground-referenced Sources and NRSE Input Connections 3.2.3 Differential Input Mode The differential input mode provides two inputs that respond to signal voltage difference between them.

  • Page 50: Figure 3-4: Floating Source And Differential Input

    resistors. In differential input mode, less noise couples into the signal connections than in single-ended mode. Input Multipexer x = 0, ..., 31 Instrumentation Amplifier AIxH Ground Referenced To A/D Signal Converter Source AIxL AIGND Figure 3-4: Floating Source and Differential Input...

  • Page 51: Operation Theory

    DAQ/DAQe/PXI-220x Series Operation Theory The operation theory of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card functions are described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O, and gen- eral purpose counter/timer. The operation theory can help you understand how to configure and program the DAQ/DAQe/PXI- 2204/2205/2206/2208 card.

  • Page 52: Figure 4-1: Synchronous Digital Inputs Block Diagram

    SDI<3..0> SDI<3..0> 16-bit from CN2 Register From Data AD<11..0> Instrumentation FIFO Amplifier nADBUSY nADBUSY AD_conversion nADCONV Figure 4-1: Synchronous Digital Inputs Block Diagram AD_conversion nADBUSY 16 bits data(including AD<11..0> and SDI<3..0> latched into AD Data FIFO Figure 4-2: Synchronous Digital Inputs Timing Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D_conversion signal), while SDI<3..0>...

  • Page 53: Table 4-1: Bipolar Analog Input Range And Output Digital Code On Daq/Daqe/Pxi-2204/2208

    DAQ/DAQe/PXI-220x Series Table 4-1and Table 4-2 illustrate the ideal transfer characteristics of various input ranges of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card. Digital Description Bipolar Analog Input Range code Full-scale Range ±10V ±5V ±2.5V ±1.25V — Least significant bit 4.88mV 2.44mV 1.22mV 0.61mV —...

  • Page 54: Table 4-3: Bipolar Analog Input Range And Output Digital Code For Daq/Daqe/Pxi-2205/2206

    4.1.2 DAQ/DAQe/PXI-2005/2006/2016 AI Data Format The data format of the acquired 16-bit A/D data is 2's Comple- ment coding. Table 4-3 and Table 4-4 illustrate the valid input ranges and the ideal transfer characteristics. Digital Description Bipolar Analog Input Range code Full-scale Range ±10V...
  • Page 55 DAQ/DAQe/PXI-220x Series 4.1.3 Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D con- verter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conver- sion status and read the A/D data back when it is available.

  • Page 56: Programmable Scan Acquisition Mode

    4.1.4 Programmable Scan Acquisition Mode Scan Timing and Procedure It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accu- rately program the period between conversions of individual channels. There are at least four counters which need to be specified: SI_counter (24-bit): Specify the Scan Interval = SI_counter / ...

  • Page 57: Figure 4-3: Scan Timing

    DAQ/DAQe/PXI-220x Series 3 Scans, 4 Samples per scan (PSC_Counter=3, NumChan_Counter=4) ( channel sequences are specified in Channel Gain Queue) Scan_start AD_conversion Scan_in_progress (SSHOUT)(pin8 on CN2) Acquisition_in_progress Sampling Interval t= Scan Interval T= SI2_COUNTER/TimeBase SI_COUNTER/TimeBase Figure 4-3: Scan Timing There are four trigger modes to start the scan acquisition. Refer to section 4.1 for details.
  • Page 58 Scan with SSH You can send the SSHOUT signal on CN2 to external S&H cir- cuits to sample and hold all signals if you want to simultane- ously sample all channels in a scan, as illustrated in Figure 4-3. The DAQ/DAQe/PXI-2208 does not support this function. The SSHOUT signal is sent to external S&H circuits to hold the NOTE: NOTE:...

  • Page 59: Trigger Modes

    DAQ/DAQe/PXI-220x Series 4.1.6 Trigger Modes The DAQ/DAQe/PXI-2204/2205/2206/2208 card provides four trigger sources (internal software trigger, external analog trigger, and digital trigger sources, and SSI trigger signals). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source.

  • Page 60: Pre-Trigger Acquisition

    Pre-Trigger Acquisition Use pre-trigger acquisition in applications where you want to collect data before a trigger event. The A/D starts to sample when you execute the specified function calls to begin the pre- trigger operation, and it stops when the trigger event occurs. Users must program the value M in M_counter (16 bits) to specify the amount of the stored scans before the trigger event.

  • Page 61: Figure 4-5: Pre-Trigger (Trigger With Scan In Progress)

    DAQ/DAQe/PXI-220x Series Note that if a trigger event occurs when a scan is in progress, the data acquisition won't stop until the scan completes, and the stored M scans of data includes the last scan. Therefore, the first stored data will always be the first channel entry of a scan (that is, the first channel entry in the Channel Gain Queue if the number of entries in the Channel Gain Queue is equivalent to the value of NumChan_counter), no matter when a trigger signal occurs, as...

  • Page 62: Figure 4-6: Pre-Trigger With M_Enable=0 (Trigger Occurs Before M Scans)

    When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the orig- inally specified amount M_counter, as illustrated in Figure 4-6. This situation can be avoided by setting M_enable. If M_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7.

  • Page 63: Figure 4-7: Pre-Trigger With M_Enable=1

    DAQ/DAQe/PXI-220x Series (M_counter = M = 3, NumChan_counter=4, PSC_counter=0) The first M scans Trigger signals which occur in the shadow region(the first M scans) will be ignored Trigger Scan_start AD_conversion Scan_in_progress (SSHOUT)(pin2 on CN2) Acquisition_in_progress Aquired data Acquired & stored data (M scans) Operation start Figure 4-7: Pre-trigger with M_enable=1...

  • Page 64: Middle-Trigger Acquisition

    Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.

  • Page 65: Figure 4-9: Middle-Trigger (Trigger Occurs When A Scan Is In Progress)

    DAQ/DAQe/PXI-220x Series If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9. Figure 4-9: Middle-Trigger (Trigger occurs when a scan is in progress)

  • Page 66: Figure 4-10: Post-Trigger

    Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC_counter, as illustrated in Figure 4- 10. The total acquired data length = NumChan_counter * PSC_counter.

  • Page 67: Figure 4-11: Delay Trigger

    DAQ/DAQe/PXI-220x Series Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trig- ger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16-bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met.

  • Page 68: Figure 4-12: Post Trigger With Re-Trigger

    Use post-trigger or delay-trigger acquisition with re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter, and users could program Retrig_no to specify the re-trigger numbers. Figure 4-12 illus- trates an example.
  • Page 69 DAQ/DAQe/PXI-220x Series 4.1.7 Bus-mastering DMA Data Transfer In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI bus- mastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth. The bus-mastering controller con- trols the PCI bus when it becomes the master.

  • Page 70: Figure 4-13: Linked List Of Pci Address Dma Descriptors

    support 64-bit addresses which can be mapped into more than 4 GB of the address space. You can allocate many small size mem- ory blocks and chain their associative DMA descriptors altogether by their application programs. Figure 4-13: Linked List of PCI Address DMA Descriptors In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB).

  • Page 71: D/A Conversion

    DAQ/DAQe/PXI-220x Series 4.2 D/A Conversion NOTEThe DAQ/DAQe/PXI-2208 card does not support this func- tion. There are two 12-bit D/A output channels available in the DAQ/ DAQe/PXI-2204/2205/2206 card. When using D/A converters, you should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels.

  • Page 72: Table 4-6: Unipolar Output Code Table

    Digital Code Analog Output 111111111111 Vref * (4095/4096) 100000000000 Vref * (2048/4096) 000000000001 Vref * (1/4096) 000000000000 Table 4-6: Unipolar Output Code Table The D/A conversion is initiated by a trigger source. You must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met.
  • Page 73 DAQ/DAQe/PXI-220x Series 4.2.2 Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters.

  • Page 74: Figure 4-14: Typical D/A Timing Of Waveform Generation

    4 update counts, 3 iterations (UC _Counter=4, IC_Counter=3) Trigger UC_Counter=4 DAWR WFG_in_progress Delay until Delay until Delay until DLY1_Counter DLY2_Counter DLY2_Counter reaches 0 reaches 0 reaches 0 DA update_interval t= UI_Counter/Timebase Output Waveform Operation start A single waveform IC_Counter = 3 Figure 4-14: Typical D/A Timing of Waveform Generation The maximum D/A update rate is 1 MHz.

  • Page 75: Figure 4-15: Post Trigger Waveform Generation

    DAQ/DAQe/PXI-220x Series 4.2.3 Trigger Modes Post-Trigger Generation Use post-trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1_Counter is ignored and not be specified. Figure 4-15 shows a single waveform generated right after a trigger signal is detected and assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, and 4V.

  • Page 76: Figure 4-16: Delay Trigger Waveform Generation

    Figure 4-16: Delay Trigger Waveform Generation Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation assuming the data in the data buffer are 2V, 4V, 2V, and 0V.

  • Page 77: Figure 4-18: Finite Iterative Waveform Generation With Post-Trigger (Dly2_Counter = 0)

    DAQ/DAQe/PXI-220x Series Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number and the iterations may be finite (Figure 4-18) or infinite (Figure 4-19). Take note that in infinite mode the waveform generation does not stop until software stop function is exe- cuted and IC_Counter is still valid when stop mode III is selected.

  • Page 78: Figure 4-19: Infinite Iterative Waveform Generation With Post-Trigger (Dly2_Counter = 0)

    Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger (DLY2_Counter = 0) Delay2 in Iterative Waveform Generation To stretch out the flexibility of the D/A waveform generation, we add a DLY2_Counter to separate two consecutive waveforms in iterative waveform generation. The time between two wave- forms is assigned by setting the value of the DLY2_Counter.

  • Page 79: Figure 4-20: Stop Mode I

    DAQ/DAQe/PXI-220x Series Stop Modes of Scan Update You can call software stop function to stop waveform genera- tion when it is still in progress. Three stop modes are provided for timed waveform generation meant to stop the waveform generation. You can apply these three modes to stop waveform generation no matter infinite or finite waveform generation mode is selected.

  • Page 80: Figure 4-21: Stop Mode Ii

    In stop mode II, after a software stop command is given, the waveform generation does not stop until a complete single waveform is finished. See Figure 4-21. Since the UC_counter is set to four, the total DA update counts (number of pulses of DAWR signal) must be a multiple of four (update counts = 20 in this example).

  • Page 81: Digital I/O

    DAQ/DAQe/PXI-220x Series 4.3 Digital I/O The DAQ/DAQe/PXI-2204/2205/2206/2208 card contains 24 lines of general-purpose digital I/O (GPIO) which is provided through the 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. Port A and Port B can be programmed to be either input or output ports.
  • Page 82 4.4.1 The Basics of Timer/Counter Functions Each timer/counter has three inputs that can be controlled via hardware or software. These are clock input (GPTC_CLK), gate input (GPTC_GATE), up/down control input (GPTC_UPDOWN). The GPTC_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC_CLK input make counter...

  • Page 83: Figure 4-23: Mode1 Operation

    DAQ/DAQe/PXI-220x Series Figure 4-23: Mode1 Operation Mode2: Single Period Measurement In this mode, the counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE.

  • Page 84: Figure 4-25: Mode3 Operation

    Mode3: Single Pulse-width Measurement In this mode, the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state.

  • Page 85: Figure 4-26: Mode4 Operation

    DAQ/DAQe/PXI-220x Series Mode4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC_CLK input by software. GPTC_GATE is used to enable/disable counting.

  • Page 86: Figure 4-27: Mode5 Operation

    Mode5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC_GATE edge. You could specify these programmable parameters in terms of periods of the GPTC_CLK input. Once the first GPTC_GATE edge triggers the single pulse, GPTC_GATE takes no effect until the software-start is re-exe- cuted.

  • Page 87: Figure 4-28: Mode6 Operation

    DAQ/DAQe/PXI-220x Series Mode6: Re-triggered Single Pulse Generation This mode is similar to Mode5 except that the counter gener- ates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored.

  • Page 88: Figure 4-30: Mode8 Operation

    Mode8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval pulse-width following software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.

  • Page 89: Trigger Sources

    DAQ/DAQe/PXI-220x Series 4.5 Trigger Sources ADLINK provides flexible trigger selections in the DAQ/DAQe/PXI- 2204/2205/2206/2208 card. In addition to the internal software trigger, the DAQ/DAQe/PXI-2204/2205/2206/2208 card also sup- ports external analog, digital triggers, and SSI triggers. You can configure the trigger source by software for A/D and D/A pro- cesses individually.

  • Page 90: Table 4-7: Analog Trigger Src1 (Extatrig) Ideal Transfer

    Figure 4-31: Analog Trigger Block Diagram Trigger level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80 0x7F -0.08V 0x01 -9.92V Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic The trigger signal is generated when the analog trigger condition is satisfied.

  • Page 91: Figure 4-32: Below-Low Analog Trigger Condition

    DAQ/DAQe/PXI-220x Series Below-Low Analog Trigger Condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low_Threshold voltage, and the High_Threshold set- ting is not used in this trigger condition. Figure 4-32: Below-Low Analog Trigger Condition Above-High Analog Trigger Condition Figure 4-33 shows the above-high analog trigger condition, the...

  • Page 92: Figure 4-34: Inside-Region Analog Trigger Condition

    Inside-Region Analog Trigger Condition Figure 4-34 shows the inside-region analog trigger condition, the trigger signal is generated when the input analog signal level falls in the range between the High_Threshold and the Low_Threshold voltages. The High_Threshold setting should be always higher than the Low_Threshold voltage setting.

  • Page 93: Figure 4-35: High-Hysteresis Analog Trigger Condition

    DAQ/DAQe/PXI-220x Series High-Hysteresis Analog Trigger Condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting.

  • Page 94: Figure 4-36: Low-Hysteresis Analog Trigger Condition

    Low-Hysteresis Analog Trigger Condition Figure 4-36 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low_Threshold voltage, and the High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting.

  • Page 95: Figure 4-37: External Digital Trigger

    DAQ/DAQe/PXI-220x Series External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT- DTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process.

  • Page 96: User-Controllable Timing Signals

    4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and requirements for synchronizing multiple cards, the DAQ/DAQe/ PXI-2204/2205/2206/2208 card provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/DAQe/PXI-2204/2205/2206/ 2208 card is composed of a bunch of counters and trigger signals in the FPGA.

  • Page 97: Table 4-8: User-Controllable Timing Signals And Functionalities

    DAQ/DAQe/PXI-220x Series You can utilize the flexible timing signals through our software drivers, then simply and correctly connect the signals with the DAQ/DAQe/PXI-2204/2205/2206/2208 card. Here is the summary of the DAQ timing signals and the corresponding functionalities for DAQ/DAQe/PXI-2204/2205/2206/2208 card. Timing signal category Corresponding functionality SSI/PXI signals...
  • Page 98 4. ADCONV, the conversion signal to initiate a single con- version, which could be derived from internal counter, AFI[0] or SSI_ADCONV. Note that this signal is edge- sensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effec- tive conversion signal.

  • Page 99: Table 4-9: Auxiliary Function Input Signals And Functionalities

    DAQ/DAQe/PXI-220x Series 4.6.2 Auxiliary Function Inputs (AFI) You can use the AFI in applications that take advantage of exter- nal circuitry to directly control the DAQ/DAQe/PXI-2204/2205/ 2206/2208 card. The AFI includes two categories of timing signals: one group is the dedicated input, and the other is the multi-func- tion input.
  • Page 100 intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE. AFI[0] Alternatively, you can also directly apply an external A/D con- version signal to replace the internal ADCONV signal.

  • Page 101: System Synchronization Interface

    DAQ/DAQe/PXI-220x Series 4.6.3 System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing synchronization between multiple cards. In DAQ/DAQe/PXI-2204/ 2205/2206/2208 card, we designed a bi-directional SSI I/O to pro- vide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI sig- nal.
  • Page 102 is needed. For detailed information of the PXI specifications, refer to the PXI Specification Revision 2.0 from PXI System Alliance (www.pxisa.org). The six internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers. Refer to section 4.6 for detailed information on the six internal timing signals.
  • Page 103 DAQ/DAQe/PXI-220x Series output the internal timing signals to the SSI slaves. With the SSI, users could achieve better card-to-card synchronization. Note that when power-up or reset, the DAQ timing signals are reset to use the internal generated timing signals.
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  • Page 105: Calibration

    DAQ/DAQe/PXI-220x Series Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ/DAQe/PXI-2204/2205/2206/2208 card is factory-cali- brated before shipment. The associated calibration constants of the TrimDACs firmware to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package.

  • Page 106: Auto-Calibration

    5.2 Auto-calibration Through the DAQ/DAQe/PXI-2204/2205/2206/2208 card auto-cal- ibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connec- tions, reference voltage, or measurement devices. The DAQ/DAQe/PXI-2204/2205/2206/2208 card comes with an onboard calibration reference to ensure the accuracy of auto-cali- bration.

  • Page 107: Important Safety Instructions

    DAQ/DAQe/PXI-220x Series Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.
  • Page 108 Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately. Risque d’explosion si la pile est remplacée par une autre de CAUTION: type incorrect. Veuillez jeter les piles usagées de façon appro- priée.

  • Page 109: Getting Service

    6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com ADLINK Technology GmbH Hans-Thoma-Straße 11...

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