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ADLINK Technology DAQ-2006DB-001 User Manual

4-ch, simultaneous, high performance multi-function data acquisition card
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Adlink DAQ-2006DB-001
4-CH 16-Bit 250 kS/s Simultaneous-Sampling
Multi-Function DAQ Card
A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
• C r i t i c a l a n d e x p e d i t e d s e r v i c e s
• I n s t o c k / R e a d y - t o - s h i p
Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate, representative, or authorized distributor for any manufacturer listed herein.
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https://www.artisantg.com/50301-1
• We b u y y o u r e x c e s s , u n d e r u t i l i z e d , a n d i d l e e q u i p me n t
• F u l l - s e r v i c e , i n d e p e n d e n t r e p a i r c e n t e r

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Summary of Contents for ADLINK Technology DAQ-2006DB-001

  • Page 1 Adlink DAQ-2006DB-001 4-CH 16-Bit 250 kS/s Simultaneous-Sampling Multi-Function DAQ Card 1345 In Stock Qty Available: 1 Used and in Excellent Condition Buy Today! https://www.artisantg.com/50301-1 A l l t r a d e m a r k s , b r a n d n a m e s , a n d b r a n d s a p p e a r i n g h e r e i n a r e t h e p r o p e r t y o f t h e i r r e s p e c t i v e o w n e r s .
  • Page 2 DAQ/PXI-201x/200x 4-CH, Simultaneous, High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. 2.00 Revision Date: April 20, 2006 Part No: 50-11020-1030 Advance Technologies; Automate the World.
  • Page 3 Copyright 2006 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
  • Page 4 Getting Service from ADLINK Customer Satisfaction is top priority for ADLINK Technology Inc. Please contact us should you require any service or assistance. ADLINK TECHNOLOGY INC. Web Site: http://www.adlinktech.com Sales & Service: Service@adlinktech.com TEL: +886-2-82265877 FAX: +886-2-82265717 Address: 9F, No. 166, Jian Yi Road, Chungho City,...
  • Page 6 Table of Contents 1 Introduction ................ 1 Features................2 Applications ................. 3 Specifications............... 4 Software Support ............... 13 Programming Library ............ 13 DAQ-LVIEW PnP: LabVIEW® Driver ......13 D2K-OCX: ActiveX Controls ......... 14 2 Installation ................ 15 Contents of Package ............15 Unpacking................
  • Page 7 Trigger Sources ..............57 Software-Trigger ............57 External Analog Trigger ..........57 User-controllable Timing Signals ........61 DAQ timing signals ............63 Auxiliary Function Inputs (AFI) ........64 System Synchronization Interface ........ 67 AI_Trig_Out and AO_Trig_Out ........69 5 Calibration ................. 71 Loading Calibration Constants...........
  • Page 8 List of Tables Table 1-1: -3dB small signal bandwidth ........5 Table 1-2: System Noise ............5 Table 1-3: CMRR: (DC to 60Hz) ..........7 Table 3-1: 68-pin VHDCI-type pin assignment ......19 Table 3-2: 68-pin VHDCI-type Connector Legend ....20 Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX 22 Table 3-4: Legend of SSI connector ........
  • Page 9 List of Figures Figure 2-1: PCB Layout of the DAQ-20XX......... 17 Figure 2-2: PCB Layout of the PXI-20XX........17 Figure 3-1: Single-Ended connections ........25 Figure 3-2: Ground-referenced source and differential input ..25 Figure 3-3: Floating source and differential input....... 26 Figure 4-1: Synchronous Digital Inputs Block Diagram....
  • Page 10 Figure 4-21: Stop mode II ............51 Figure 4-22: Stop mode III ............51 Figure 4-23: Mode 1 Operation............ 53 Figure 4-24: Mode 2 Operation............ 54 Figure 4-25: Mode 3 Operation............ 54 Figure 4-26: Mode 4 Operation............ 55 Figure 4-27: Mode 5 Operation............ 55 Figure 4-28: Mode 6 Operation............
  • Page 12 Introduction The DAQ/PXI-20XX is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap-plications in medical, process control, etc. Introduction...
  • Page 13 1.1 Features The DAQ/PXI-20XX Advanced Data Acquisition Card provides the fol-lowing advanced features: 32-bit PCI-Bus, plug and play 4-channel simultaneous differential analog inputs DAQ/PXI-2010: 14-bit Analog input resolution with sampling rate up to 2MS/s DAQ/PXI-2005: 16-bit Analog input resolution with sampling rate up to 500KS/s DAQ/PXI-2006: 16-bit Analog input resolution with sampling rate up to 250KS/s...
  • Page 14 1.2 Applications Automotive Testing Cable Testing Transient signal measurement Laboratory Automation Biotech measurement Introduction...
  • Page 15 1.3 Specifications Analog Input (AI) Number of channels: 4 differential A/D converter: 2010: LTC1414 or equivalent 2005: A/D7665 or equivalent 2006: A/D7663 or equivalent 2016: A/D7671 or equivalent Max sampling rate: 2010: 2MS/s 2016: 800kS/s 2005: 500kS/s 2006: 250kS/s Resolution: 2010: 14 bits, no missing code 2005/2006/2016:16 bits, no missing code FIFO buffer size:...
  • Page 16 ° -3dB small signal bandwidth: (Typical, 25 Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB) ±10V 1170 kHz 0~10V 1090 kHz ±5V 1050 kHz 0~5V 1020 kHz 2010 ±2.5V 800 kHz 0~2.5V 790 kHz ±1.25V 530 kHz 0~1.25V 530 kHz ±10V 1160 kHz 0~10V...
  • Page 17 Device Input Range System noise Input Range System noise ±10V 1.0 LSBrms 0~10V 1.5 LSBrms ±5V 1.0 LSBrms 0~5V 1.6 LSBrms 2006 ±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms ±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms ±10V 1.6 LSBrms 0~10V 2.9 LSBrms ±5V 1.8 LSBrms 0~5V...
  • Page 18 CMRR: (DC to 60Hz, Typical) Device Input Range CMRR Input Range CMRR ±10V 90 dB 0~10V 89 dB ±5V 92 dB 0~5V 92 dB 2010 ±2.5V 95 dB 0~2.5V 94 dB ±1.25V 97 dB 0~1.25V 97 dB ±10V 86 dB 0~10V 85 dB ±5V...
  • Page 19 Before calibration: ±0.6% of output max After calibration: ±0.1% of output max for DAQ/PXI- 2010, ±0.03% of output max for DAQ/PXI-2005/2006/ 2016 Introduction...
  • Page 20 Analog Output (AO) Number of channels: 2 channel voltage output DA converter: LTC7545 or equivalent Max update rate: 1MS/s Resolution: 12 bits FIFO buffer size: 1k samples per channel when both channels are enabled for timed DA output, and 2k samples when only one channel is used for timed DA output Data transfers: Programmed I/O, and bus-mastering DMA with scatter/...
  • Page 21 Before calibration: ±0.8% of output max After calibration: ±0.02% of output max General Purpose Digital I/O (G.P. DIO, 82C55A) Number of channels: 24 programmable Input/Output Compatibility: TTL/CMOS Input voltage: Logic Low: VIL=0.8V max; IIL=0.2mA max. High: VIH=2.0V max; IIH=0.02mA max Output voltage: Low: VOL=0.5V max;...
  • Page 22 Analog Trigger (A.Trig) Source: All analog input channels; external analog trigger (EXTATRIG) Level: ±Full-scale, internal; ±10V external Resolution: 8 bits Slope: Positive or negative (software selectable) Hysteresis: Programmable Bandwidth: 400khz External Analog Trigger Input (EXTATRIG) Input Impedance: Ω for DAQ/PXI-2010 Ω...
  • Page 23 Physical Dimensions: 175mm by 107mm for DAQ-20XX Standard CompactPCI form factor for PXI-20XX I/O connector: 68-pin female VHDCI type (e.g. AMP- 787254-1) Power Requirement (typical) +5VDC: 1.82 A for DAQ/PXI-2010 2.04 A for DAQ/PXI-2005 1.82 A for DAQ/PXI-2006 2.52 A for DAQ/PXI-2016 Operating Environment °...
  • Page 24 1.4 Software Support ADLINK provides versatile software drivers and packages for users’ dif-ferent approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Win- dows based systems, but also provide drivers for other software packages such as LabVIEW®.
  • Page 25 license. For detailed information about DAQ-LVIEW PnP, please refer to the user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW PnP) D2K-OCX: ActiveX Controls We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use D2K-OCX ActiveX control component libraries for developing applications. D2K-OCX is designed for Windows 98/NT/2000/XP.
  • Page 26 Installation This chapter describes how to install the DAQ/PXI-20XX. The con- tents of the package and unpacking information that you should be aware of are outlined first. The DAQ/PXI-20XX performs an automatic configuration of the IRQ, and port address. Users can use software utility, PCI_SCAN to read the system configuration.
  • Page 27 Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. You are now ready to install your DAQ/PXI-20XX. Note: DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.
  • Page 28 2.3 DAQ/PXI-20XX Layout Figure 2-1: PCB Layout of the DAQ-20XX Figure 2-2: PCB Layout of the PXI-20XX Installation...
  • Page 29 2.4 PCI Configuration 1. Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system.
  • Page 30 Signal Connections This chapter describes the connectors of the DAQ/PXI-20XX, and the signal connection between the DAQ/PXI-20XX and external devices. 3.1 Connectors Pin Assignment The DAQ/PXI-20XX is equipped with one 68-pin VHDCI-type con- nector (AMP-787254-1). It is used for digital input/output, analog input / output, and timer/counter signals, etc.
  • Page 31 22 56 23 57 24 58 25 59 26 60 27 61 DGND 28 62 DGND 29 63 30 64 31 65 32 66 33 67 34 68 Table 3-1: 68-pin VHDCI-type pin assignment * SDI for DAQ/PXI-2010 only; NC for DAQ/PXI-2005/2006/2016 Legend: Pin # Signal Name...
  • Page 32 Pin # Signal Name Reference Direction Description Gate of 17,51 GPTC<0,1>_GATE DGND Input GPTC<0,1> Output of 18,52 GPTC<0,1>_OUT DGND Input GPTC<0,1> Up/Down of 19,53 GPTC<0,1>_UPDOWN DGND Input GPTC<0,1> External TIME- EXTTIMEBASE DGND Input BASE 21,28,49,50,54,62 DGND -------- -------- Digital ground Programmable 22,56,23,57,24,58,25,59 PB<7,0>...
  • Page 33 Pin # Signal Name Reference Direction Description Auxiliary Func- tion Input 1 AFI1 DGND Input (DAWR, DA_START) Table 3-2: 68-pin VHDCI-type Connector Legend *PIO means programmable I/O SSI_TIMEBASE DGND SSI_ADCONV DGND SSI_DAWR DGND SSI_SCAN_START 7 DGND RESERVED 9 10 DGND SSI_AD_TRIG 11 12 DGND SSI_DA_TRIG...
  • Page 34 SSI timing signal Functionality SSI master: send the DAWR out. SSI_DAWR SSI slave: accept the SSI_DAWR to replace the internal DAWR signal. SSI master: send the DA_TRIG out. SSI_DA_TRIG SSI slave: accept the SSI_DA_TRIG as the digital trigger signal. Table 3-4: Legend of SSI connector Signal Connections...
  • Page 35 3.2 Analog Input Signal Connection The DAQ/PXI-20XX provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measure- ments from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input sig- nals.
  • Page 36 Figure 3-1: Single-Ended connections In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential con- figurations. Therefore, the single-ended connection is not recom- mended unless minimal wire connections are necessary. Differential Measurements Differential Connection Grounded-Reference Signal Sources...
  • Page 37 Differential Connection for Floating Signal Sources Figure 3-3 shows how to connect a floating signal source to DAQ/PXI-20XX in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance.
  • Page 38 Operation Theory The operation theory of the functions on the DAQ/PXI-20XX is described in this chapter. The functions include the A/D conver- sion, D/A conversion, Digital I/O and General Purpose Counter/ Timer. The operation theory can help you understand how to con- figure and program the DAQ/PXI-20XX.
  • Page 39 DAQ/PXI-2010 AI Data Format Synchronous Digital Inputs (for DAQ/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>_X per chan- nel from J5 will be latched into the 16-bit register and data FIFO, as shown in Figure 8 and Figure 9.
  • Page 40 due to the variation of the conver-sion time of the A/D con- verters. Table 4-1 and 4-2 illustrate the ideal transfer characteristics of var- ious input ranges of DAQ\PXI-20XX. The converted digital codes for DAQ\PXI-2010 are 14-bit and 2’s complement, and here we present the codes as hexa-decimal numbers.
  • Page 41 DAQ/PXI-2005/2006/2016 AI Data Format The data format of the acquired 16-bit A/D data is Binary coding. Table 7 and 8 illustrate the valid input ranges and the ideal transfer characteristics. The converted digital codes for DAQ/PXI-2005/ 2006/2016 are 16-bit and direct binary, and here we present the codes as hexadecimal numbers.
  • Page 42 This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D con- version is fully controlled under software. However, it is difficult to control the A/D con-version rate. Specifying Channel, Gain, and Polarity In both the Software Polling and programmable scan acquisi- tion mode, the channel, gain, and polarity for each channel can...
  • Page 43 pling A/D card, so the “scan interval” equals to the “sampling interval”. Example: (Post-trigger acquisition) SI_counter = 160 PSC_counter = 30 TIMEBASE = Internal clock source Then Scan Interval = 160/40M s = 4 us Total acquisition time = 30 X 4 us = 120 us TIMEBASE clock source In scan acquisition mode, all the A/D conversions start on the output of counters, which use TIMEBASE as the clock source.
  • Page 44 There are 4 trigger modes to start the scan acquisition, please refer to section 4.1for more details. The data transfer mode is dis- cussed below. Note: 1. The maximum A/D sampling rate is 2MHz for DAQ/PXI- 2010, 500kHz for DAQ/PXI-2005, 250kHz for DAQ/PXI- 2006 and 800kHz for DAQ/PXI-2016.
  • Page 45 post scan count is 0 because there is no sampling after the trig- ger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels * M_counter. Figure 4-4: Pre-trigger (trigger occurs after at least M scans acquired) Note that If the trigger event occurs when a conversion is in progress, the data acquisition won’t stop until this conversion is completed, and the stored M scans of data include the last scan,...
  • Page 46 This situation can be avoided by setting M_enable. If M_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7. However, if M_enable is set to 0, the trigger signal will be accepted any time, as illustrated in Figure 13.
  • Page 47 Note: The PSC_counter is set to 0 in pre-trigger acquisition mode. Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.
  • Page 48 If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9. Figure 4-9: Middle trigger (trigger occurs when a scan is in progress) Note:M_counter defined in Middle-Trigger is different from that of Pre-Trigger.
  • Page 49 Figure 4-10: Post trigger Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trig- ger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16bit).
  • Page 50 data. The total acquired data length = number of enable-chan- nel * PSC_counter. Figure 4-11: Delay trigger Note: When the Delay_counter clock source is set to TIMEBASE, the maximum delay time = 216/40M s = 1.638ms, and when the source is set to A/D sampling clock, the maximum delay time can be as higher as (216 * SI_counter / 40M ).
  • Page 51 Figure 4-12: Post trigger with re-trigger Bus-mastering DMA Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-master- ing controller, which is built in the PLX IOP-480 PCI controller, controls the PCI bus when it becomes the master of the bus.
  • Page 52 please refer to http://www.plxtech.com for more in-formation on PCI controllers. By using a high-level programming library for high speed DMA data ac-quisition, users simply need to assign the sampling period and the number of conversion into their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA.
  • Page 53 Figure 4-13: Scatter/gather DMA for data transfer In non-chaining mode, the maximum DMA data transfer size is 2M double words (8M bytes). However, by using chaining mode, scat- ter/gather, there is no limitation on DMA data transfer size. Users can also link the de-scriptor nodes circularly to achieve a multi- buffered mode DMA.
  • Page 54 put by feeding a sinusoidal signal into the reference input. The range of the external reference should be within ±10V. Table 4-5 and 4-6 illustrates the relationship between digital code and output voltages. Digital Code Analog Output 111111111111 Vref * (2047/2048) 100000000001 Vref * (1/2048) 100000000000...
  • Page 55 bipolar, and ref-erence source: internal 10V or external AOEX- TREF. Then update the digital values into D/A data registers through a software output command. Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform.
  • Page 56 Figure 21 shows a typical D/A timing diagram. D/A updates its out- put on each rising edge of DAWR. The meaning of the counters above is dis-cussed more in the following sections. Figure 4-14: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Note: The maximum D/A update rate is 1MHz.
  • Page 57 Figure 4-15: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Delay-Trigger Generation Use delay trigger when you want to delay the waveform gener- ation after a trigger event. In Figure 4-16, DA_DLY1_counter determines the delay time from the trigger signal to the start of the waveform generation.
  • Page 58 Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events.
  • Page 59 Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number, and the itera-tions can be finite (Figure 4-12) or infinite (Figure 4-13). A data FIFO on board is used to buffer the digital data for DA output.
  • Page 60 Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) Note: 1. When running infinite iterative waveform generation, set- ting IC_Counter is ineffective to the waveform genera- tion.
  • Page 61 for timed waveform gen-eration, which means when it is to stop the waveform generation. You can apply these 3 modes to stop waveform generation no matter infinite or finite waveform gen- eration mode is selected. Figure 4-20 illustrates an example for stop mode I, in this mode the waveform stops immediately when software command is asserted.
  • Page 62 Figure 4-21: Stop mode II Figure 4-22: Stop mode III 4.3 Digital I/O The DAQ/PXI-20XX contains 24-lines of general-purpose digital I/ O (GPIO), which is provided through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C.
  • Page 63 input and is stored with the 14-bit AD data. Please refer to section 4.1 for the more details. 4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications. They have the following fea- tures: Count up/down controlled by hardware or software Programmable counter clock source (internal or external...
  • Page 64 GPTC_GATE, and GPTC_OUT are assumed to be active high or rising-edge triggered in the figures. General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter.
  • Page 65 4-24 il-lustrates the operation where initial count = 0, count-up mode. Figure 4-24: Mode 2 Operation Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software.
  • Page 66 GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. Figure 4-26: Mode 4 Operation Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active...
  • Page 67 Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode5 except that the counter gener- ates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored.
  • Page 68 Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval pulse-width following software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.
  • Page 69 level for SRC1 is ±10V and the resolution is 78mV (please refer to Table 4-6), while the trigger range of SRC2 is the full-scale range of the selected channel input, and the resolution is the desired range divided by 256. For example, if the channel input selected to be the trigger source is set bipolar and ±5V range, the trigger volt- age would be 4.96V when the trigger level code is set to 0xFF while 0V when the code is set to 0x80.
  • Page 70 Below-Low analog trigger condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low_Threshold voltage, and the High_Threshold set- ting is not used in this trigger condi-tion. Figure 4-32: Below-Low analog trigger condition Above-High analog trigger condition Figure 4-33 shows the above-high analog trigger condition, the...
  • Page 71 should be always higher then the Low_Threshold voltage set- ting. Figure 4-34: Inside-Region analog trigger condition High-Hysteresis analog trigger condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration.
  • Page 72 High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting. Figure 4-36: Low-Hysteresis analog trigger condition External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXT- DTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger.
  • Page 73 20XX series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/PXI-20XX series is composed of a bunch of counters and trigger signals in the FPGA. These tim- ing signals are related to the A/D, D/A conversions and Timer/ Counter applications.
  • Page 74 Timing signal category Corresponding functionality AFI signals Control DAQ-2000 by external timing signals AI_Trig_Out, AO_Trig_Out Control external circuitry or boards Table 4-8: Summary of user-controllable timing signals and the corresponding functionalities DAQ timing signals The user-controllable internal timing-signals contain: (Please refer to Section 4.1 for the internal timing signal definition) 1.
  • Page 75 should be TTL-compatible and the minimum pulse width is 20ns. 5. DA_TRIG, the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trig- ger, internal software trigger and SSI_AD_TRIG. Refer to Section 4.5 for detailed de-scription. 6.
  • Page 76 Category Timing signal Functionality Constraints 1. TTL-compatible Replace the 2. 1MHz to 40MHz EXTTIMEBASE internal 3. Affects on both A/D TIMEBASE and D/A operations 1. TTL-compatible External digi- 2. Minimum pulse tal trigger EXTDTRIG width = 20ns Dedicated input input for A/D 3.
  • Page 77 EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXT- TIMEBASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE.
  • Page 78 AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. AFI[1] cur- rently only has one function. ADLINK reserves it for future development. System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing syn-chronization between multiple cards.
  • Page 79 In PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector posi- tion. All the SSI signals are routed to the 20-pin connector from the FPGA.
  • Page 80 For example: We want to synchronize the A/D operation through the ADCONV signal for 4 DAQ/PXI-20XX cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisition. The SSI setting could be: 1.
  • Page 81 VHDCI). Connecting them to any signal source may cause per-manent damage. Operation Theory...
  • Page 82 Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ/PXI-20XX is factory calibrated before shipment by writ- ing the associated calibration constants of TrimDACs to the on- board EEPROM. TrimDACs are devices containing multiple DACs within a single package.
  • Page 83 recommended for users to adjust the on-board calibration refer- ence except when an ultra-precision cali-brator is available. Note: 1. Before auto-calibration procedure starts, it is recom- mended to warn up the card for at least 15 minutes. 2. Please remove the cable before an auto-calibration pro- cedure is initiated because the DA outputs would be changed in the process of calibration.
  • Page 84 Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the follow- ing carefully. 1. Before using ADLINK’s products please read the user man- ual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA appli- cation form which can be downloaded from: http:// rma.adlinktech.com/policy/.
  • Page 85 3. Our repair service is not covered by ADLINK's guarantee in the following situations: Damage caused by not following instructions in the User's Manual. Damage caused by carelessness on the user's part dur- ing product transportation. Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.

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