ADLINK Technology DAQ/DAQe/PXI-250 Series User Manual

High performance analog output multi-function cards

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DAQ/DAQe/PXI-250x Series

High Performance

Analog Output Multi-function Cards

User's Manual

Manual Rev.

Revision Date:

Part No:

1.0

Dec. 29, 2023

50M-12264-1000

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Page 1 DAQ/DAQe/PXI-250x Series High Performance Analog Output Multi-function Cards User’s Manual Manual Rev. Revision Date: Dec. 29, 2023 Part No: 50M-12264-1000...
Page 2: Revision History
Revision History Revision Release Date Description of Change(s) 2.01 2006-12-21 Previous release PN: 50-12265-100 Initial release under new part number.  Added 1.4 Software Support.  Added 2.4 Switch and Jumper Settings.  2023-12-29 Added SSI connector pin assignment on ...
Page 3 DAQ/DAQe/PXI-250x Series Preface Copyright © 2023 ADLINK Technology Inc. This document contains proprietary information protected by copy- right. All rights are reserved. No part of this manual may be repro- duced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Page 4: California Proposition 65 Warning
California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox- ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause...
Page 5: Table Of Contents
DAQ/DAQe/PXI-250x Series Table of Contents Preface ..................iii List of Tables................. vii List of Figures ................ ix 1 Introduction ................ 1 Features................2 Applications ................. 3 Specifications............... 3 Software Support ..............7 2 Installation ................ 11 Contents of Package ............11 Unpacking ................
Page 6 5 Calibration ................. 61 Auto-calibration ..............61 Saving Calibration Constants..........62 Loading Calibration Constants........... 62 Important Safety Instructions..........65 Getting Service ..............67...
Page 7: List Of Tables
DAQ/DAQe/PXI-250x Series List of Tables Table 2-1: Board ID SW1 DIP Switch Settings ......15 Table 3-1: Connector CN1 pin assignment ......19 Table 3-2: Connector CN2 pin assignment ......20 Table 3-3: SSI connector pin assignment ........ 22 Table 3-4: SSI Connector Pin Assignment on PXI J2 ....22 Table 3-5: Legend of SSI connector ........
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Page 9: List Of Figures
DAQ/DAQe/PXI-250x Series List of Figures Figure 2-1: PCB Layout of the DAQ-2502/2501 ......13 Figure 2-2: PCB Layout of the PXI-DAQ-2502/2501 ....13 Figure 2-3: Board ID SW1 DIP Switch ........14 Figure 2-4: Enable Board ID Configuration ........ 16 Figure 4-1: DAQ/DAQe/PXI-250x Series Block Diagram...
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Page 11: Introduction
DAQ/DAQe/PXI-250x Series Introduction The DAQ/DAQe/PXI-250x Series is an advanced analog output card based on the 32-bit PCI/PXI architecture. High performance designs and state-of-the-art technology make this card ideal for waveform generation, industrial process control, and signal analy- sis applications in medical, process control, etc. Introduction...
Page 12: Features
1.1 Features DAQ/DAQe/PXI-250x Series advanced analog output cards pro- vide the following advanced features: 32-bit PCI/PXI-Bus, plug and play  Up to 1MS/s analog output rate  Up to 400KS/s analog input rate  Up to 8 analog output channels for DAQ/DAQe/PXI-2502, ...
Page 13: Applications
DAQ/DAQe/PXI-250x Series 1.2 Applications Automotive Testing  Arbitrary Waveform Generator  Transient signal measurement   Laboratory Automation  Biotech measurement  1.3 Specifications Analog Input (AI) Number of channels:  4 single-ended for DAQ/DAQe/PXI-2502  8 single-ended for DAQ/DAQe/PXI-2501 ...
Page 14 Analog Output (AO) Number of channels: 4-ch for DAQ/DAQe/PXI-2501, 8-ch  for DAQ/DAQe/PXI-2502 DA converter: AD7945  Max update rate: 1MS/s  Resolution: 12 bits  FIFO buffer size: 8K for DAQ/DAQe/PXI-2501, 16K for  DAQ/PXI- 2502 Data transfer: Programmed I/O, and bus-mastering DMA ...
Page 15 DAQ/DAQe/PXI-250x Series General Purpose Digital I/O (G.P. DIO) Number of channels: 24 programmable Input/Output  Compatibility: TTL/CMOS  Input voltage:  C> Logic Low: VIL=0.8V max.; IIL=0.2mA max.  C> High: VIH=2.0V max.; IIH=0.02mA max  Output voltage:  C> Low: VOL=0.5 V max.; IOL=8mA max. ...
Page 16 Calibration Recommended warm-up time: 15 minutes  Onboard reference: 5.0V   Temperature coefficient: ±2ppm/  Long-term stability: 6ppm/1000Hr  Physical Dimensions: 175mm by 107mm  I/O connector: 68-pin female mini-SCSI type  Power Requirement: +5VDC: 1.6A typical  Operating Environment ...
Page 17: Software Support
DAQ/DAQe/PXI-250x Series 1.4 Software Support ADLINK provides versatile software drivers and packages to suit various user approaches to building a system. Aside from pro- gramming libraries, such as DLLs, for most Windows-based sys- tems, ADLINK also provides drivers for other application environments such as LabVIEW.
Page 18 1.4.1 MAPS Core ADLINK MAPS Core is a software package that includes all the device drivers for Windows and a system level management tool called ACE (ADLINK Connection Explorer). With MAPS Core installed, the operating system can identify ADLINK devices and assign the necessary resources for low-level access, such as IO read/write or direct memory access.
Page 19 DAQ/DAQe/PXI-250x Series ADLINK Connection Explorer (ACE) also provides a ready-to-use soft-front panel for digitizer products. Clicking the Launch button in the "Utility" block allows users to control digitizers through the UI and display the acquired waveform/data on the screen. 1.4.2 MAPS/LV, LabVIEW Support Customers who develop their own programs in LabVIEW must install the MAPS/LV software package.
Page 20 1.4.3 MAPS/C, C & C++ Support Customers who develop their own programs in C or C++ environ- ments must install the MAPS/C software package. MAPS/C includes all the software components required for developing applications in C/C++, such as header files, a device API library and versatile sample programs for understanding how to manipu- late the device correctly.
Page 21: Installation
DAQ/DAQe/PXI-250x Series Installation This chapter describes how to install DAQ/DAQe/PXI-250x Series cards. The contents of the package and unpacking information that you should be aware of are outlined first. 2.1 Contents of Package In addition to this User's Guide, the package should include the following items: DAQ/DAQe/PXI-250x Series Multi-function Data Acquisition ...
Page 22: Unpacking
2.2 Unpacking Your DAQ/DAQe/PXI-250x Series card contains electro-static sen- sitive components that can be easily be damaged by static elec- tricity. Therefore, the card should be handled on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.
Page 23: Daq/Daqe/Pxi-250X Series Layout
DAQ/DAQe/PXI-250x Series 2.3 DAQ/DAQe/PXI-250x Series Layout Figure 2-1: PCB Layout of the DAQ-2502/2501 Figure 2-2: PCB Layout of the PXI-DAQ-2502/2501 Installation...
Page 24: Switch And Jumper Settings
2.4 Switch and Jumper Settings 2.4.1 Board ID (SW1) The DAQ/DAQe/PXI-250x Series has a built-in DIP switch (SW1), which is used to define each card’s board ID. When there are mul- tiple cards on the same platform, this board ID switch is useful for identifying each card’s device number.
Page 25: Table 2-1: Board Id Sw1 Dip Switch Settings
DAQ/DAQe/PXI-250x Series Pin 1 Pin 2 Pin 3 Pin 4 Board ID Table 2-1: Board ID SW1 DIP Switch Settings Installation...
Page 26: Figure 2-4: Enable Board Id Configuration
Board ID configuration is disabled by default. To enable Board ID configuration, install D2K-DASK and launch W2K_D2kUtil.exe in C:\ADLINK\D2K-DASK\Utility\. Select NOTE: NOTE: your Card Type and uncheck Ignore Board ID. See figure below. Figure 2-4: Enable Board ID Configuration Installation...
Page 27 DAQ/DAQe/PXI-250x Series 2.4.2 DIO Initial Status (JP4) The default jumper setting is enabled, making the DIO initial status low by using a 1K ohm resistor poll down to GND. To disable this feature, move the jumper cap as shown in the table below. Disabled Enabled Installation...
Page 28: Pci Configuration
2.5 PCI Configuration 1. Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system.
Page 29: Signal Connections
DAQ/DAQe/PXI-250x Series Signal Connections This chapter describes the connectors of the DAQ/DAQe/PXI- 250x Series, and the signal connection between the DAQ/DAQe/ PXI-250x Series and external devices. 3.1 Connectors Pin Assignment DAQ/DAQe/PXI-250x Series is equipped with two 68-pin VHDCI- type connectors (AMP-787254-1). It is used for digital input / out- put, analog input / output, and timer/counter signals, etc.
Page 30: Table 3-2: Connector Cn2 Pin Assignment
DGND DGND Table 3-1: Connector CN1 pin assignment Legend: Pin # Signal Name Reference Direction Description Voltage output of AO_<0..3> AGND Output DA channel <0..3> External reference for AO AOEXTREF_A/AI_0 AGND Input channel <0..3> / AI input 2 AI_1 AGND Input AI input 0 External analog...
Page 31 DAQ/DAQe/PXI-250x Series Pin # Signal Name Reference Direction Description Voltage output of DA channel <4..7> / AI Output/ 9~12 AO_<4..7>/AI_<4..7> AGND channel <4..7> Input (only for DAQ- 2501) AO trigger signal for channel 13,14 AO_TRIG_OUT_<A,B> DGND Output <0..3> <4..7> Source of 15,16 GPTC<0,1>_SRC DGND...
Page 32: Table 3-3: Ssi Connector Pin Assignment
Pin # Signal Name Reference Direction Description Power +5V Power DGND (Output) Source 28,50,54, DGND -------- -------- Digital ground Table 3-2: Connector CN2 pin assignment *PIO means programmable I/O SSI_TIMEBASE DGND SSI_ADCONV DGND SSI_DAWR DGND SSI_SCAN_START 7 DGND RESERVED 9 10 DGND SSI_AD_TRIG 11 12 DGND SSI_DA_TRIG...
Page 33: Table 3-5: Legend Of Ssi Connector
DAQ/DAQe/PXI-250x Series Legend: SSI timing signal Functionality SSI master: send the TIMEBASE out SSI_TIMEBASE SSI slave: accept the SSI_TIMEBASE to replace the internal TIMEBASE signal. SSI master: send the ADCONV out SSI_ADCONV SSI slave: accept the SSI_ADCONV to replace the internal ADCONV signal. SSI master: send the SCAN_START out SSI_SCAN_START SSI slave: accept the SSI_SCAN_START to...
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Page 35: Operation Theory
DAQ/DAQe/PXI-250x Series Operation Theory The operation theories of the DAQ/DAQe/PXI-250x Series are described in this chapter. The functions include A/D conversion, D/ A conversion, Digital I/O, and General Purpose Counter / Timer. This operation theory will help you understand how to configure and program the DAQ/DAQe/PXI-250x Series.
Page 36: Figure 4-1: Daq/Daqe/Pxi-250X Series Block Diagram
Figure 4-1: DAQ/DAQe/PXI-250x Series Block Diagram Operation Theory...
Page 37: A/D Conversion
DAQ/DAQe/PXI-250x Series 4.1 A/D Conversion When using an A/D converter, users should know the properties of the signal to be measured. In addition, users should setup the A/D configurations, including scan channels, input range, and polari- ties. The A/D acquisition is initiated by a trigger signal. The data acqui- sition will start once the trigger signal matches the trigger condi- tions.
Page 38: Table 4-2: Unipolar Input Range And Converted Digital Codes
Description Unipolar Analog Input Range Digital code Full-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25V Least significant bit 610.39uV 305.19uV 152.60uV 76.3uV FSR-1LSB 4.999389V 2.499694V 1.249847V 1.249923V 1FFF Midscale +1LSB 5.000611V 2.500306V 1.250153V 0.625076V 0001 Midscale 2.5V...
Page 39: Table 4-3: Trigger Modes And Corresponding Trigger Sources
DAQ/DAQe/PXI-250x Series Please refer to Table 4-3 for a brief summary on Trigger Modes and their Trigger Sources. Trigger Trigger Mode Description Sources Post-Trigger Perform a scan right after the trigger occurs. Scan delayed by the amount of time Delay-Trigger Software Trigger programmed after the trigger Digital Trigger...
Page 40: Figure 4-2: Timing For Scan
The relationship between counters and acquisition timing is illustrated in Figure 4-2. Figure 4-2: Timing for Scan Note: 1. The maximum A/D sampling rate is 400KHz for DAQ/DAQe/ PXI-250x Series therefore the minimum setting of SI2_counter is 100. 2. The Scan Interval can not be smaller than the interval of data Sampling Interval multiple by the Number of channels per Scan, i.e.: SI_counter >= SI2_counter * NumChan_Counter.
Page 41: Figure 4-3: Post Trigger
DAQ/DAQe/PXI-250x Series Delay Trigger Acquisition Use delay trigger when users want to delay the scan after a trigger signal. The delay time is determined by the Delay_counter, as shown in Figure 4-4. The counter counts down on the rising edges of Delay_counter clock source after the trigger signal.
Page 42: Figure 4-4: Delay Trigger
Figure 4-4: Delay Trigger Figure 4-5: Post Trigger with Retrigger 4.1.6 Bus-mastering DMA Data Transfer In programmable scan acquisition mode, all DAQ/DAQe/PXI series cards supports bus-mastering DMA data transfer. PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum bus bandwidth.
Page 43 DAQ/DAQe/PXI-250x Series mastering reduces the size of the onboard memory and reduces CPU loading since data is directly transferred to the system memory with no host CPU intervention. Bus-mastering DMA provides the fastest data transfer rate on a PCI bus. Once the analog input operation starts, control returns to your program.
Page 44: Figure 4-6: Linked List Of Pci Address Dma Descriptors
Figure 4-6: Linked List of PCI Address DMA Descriptors In non-chaining mode, the maximum DMA data transfer size is 2M double words (8 MB). However, by using chaining mode-scatter/ gather, there is no limitation for the DMA data transfer size. You may also link the descriptor nodes circularly to achieve a multi- buffered mode DMA.
Page 45: D/A Conversion
DAQ/DAQe/PXI-250x Series 4.2 D/A Conversion DAQ/DAQe/PXI-250x Series offers flexible and versatile analog output scheme to fit users’ complex field applications. In order to take full advantages of DAQ/DAQe/PXI-250x Series, we suggest users carefully read the following con-tents. Architecture There are up to 8-channel of 12-bit Digital-to-Analog Converter (DAC) available in the DAQ/DAQe/PXI-2502.
Page 46: Figure 4-8: Data Format In Fifo And Mapping
tal codes for all enabled DA channels are ready and latched. This ensures D/A conversions to be synchronized for each channel in the same D/A group. Users can utilize this property to perform multi-channel waveform generation without any phase-lag. Hardware controlled Waveform Generation FIFO is a hardware first-in first-out data queue, which holds tem- porary digital codes for D/A conversion.
Page 47 DAQ/DAQe/PXI-250x Series When using waveform generation mode, all the four DACs in the same D/A group must be configured for the same mode. However, any one of the DAC can be disabled. If users need to NOTE: NOTE: use the software update mode, they can use another D/A group on the DAQ/DAQe/PXI-2502.
Page 48: Table 4-5: D/A Output Versus Digital Codes
Bipolar Unipolar Magnitude Digital Output Output Code FSR – LSB +Vref * (2046 / 2048) Vref * (4095 / 4096) 0FFF Midscale + LSB +Vref * (1 / 2048) Vref * (2049 4096) 0801 Midscale Vref * (2048 / 4096) 0800 Midscale –...
Page 49: Table 4-6: Trigger Signals And Corresponding Signal Sources
DAQ/DAQe/PXI-250x Series Signal Descriptions Valid Sources Start Waveform Generation Software Trigger Ext. Digital Trigger Start process. Analog Trigger SSI Trigger Write data to the DAC on the Internal Update External Update SSI DAWR fal-ling edges of DAWR. Update Software Trigger Ext. Digital Trigger Stop Stop Waveform Generation Analog Trigger...
Page 50 Define the delay time for Delay Time = (DLY1_counter / DLY1_counter 16-bit waveform generation Clock Timebase) after the trigger signal. Define the delay time to separate consecutive waveform generation. Delay Time = (DLY2_counter / DLY2_counter 16-bit Effective only in Iterative Clock Timebase) Waveform Generation mode.
Page 51: Figure 4-9: Typical D/A Timing Of Waveform Generation
DAQ/DAQe/PXI-250x Series Figure 4-9: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Trigger Modes Post-Trigger Generation Use post-trigger generation when users want to generate wave- form right after a trigger signal. The number of patterns to be updated after the trigger signal is specified by UC_counter* IC_counter, as illustrated in Figure 4-9 Delay-Trigger Generation...
Page 52: Figure 4-10: Post-Trigger Generation
The counter counts down on the rising edges of DLY1_counter clock source after the start trigger signal. When the count reaches zero, DAQ/DAQe/PXI-250x Series starts to generate the wave- form. The DLY1_counter clock source can be software selected from the Internal 40MHz Timebase, external clock input (AFI-0), or GPTC output 0/1.
Page 53: Figure 4-11: Delay-Trigger Generation
DAQ/DAQe/PXI-250x Series Figure 4-11: Delay-Trigger Generation Figure 4-12: Post-Trigger with Retrigger Generation Iterative Waveform Generation Users can set IC_counter to generate iterative waveforms, no mat- ter which Trigger Mode is used. The IC_counter stores the itera- tion number. Examples are shown in Figure 4-13 and 4-14. Operation Theory...
Page 54 When IC_counter is disabled, the waveform generation will not stop until a stop trigger is asserted. For Stop Mode, please refer to Section 4.2 for details. An on-board data FIFO is used to buffer the waveform patterns for waveform generation. If the size of a single waveform is smaller than that of the FIFO, after initially loading the data from the host PC’s memory, the data in FIFO will be re-used when a single waveform generation is completed.
Page 55: Figure 4-13: Finite Iterative Waveform Generation W/Post-Trigger
DAQ/DAQe/PXI-250x Series Figure 4-13: Finite iterative waveform generation w/Post-trigger (Assuming the digital codes in the FIFO are 2V, 4V, 2V, 0V) Figure 4-14: Infinite iterative waveform generation w/Post-trigger (Assuming the digital codes in the FIFO are 2V, 4V, 2V, 0V) DLY2_Counter in iterative Waveform Generation To expand the flexibility of Iterative Waveform Generation, DLY2_counter was implemented to separate consecutive wave-...
Page 56 ation of waveform generation will start as shown in Figure 4.2.3. If users are generating waveform piece-wisely, the next piece of waveform will be generated. The DLY2_counter clock source can be software selected from Internal 40MHz Timebase, external clock input (AFI-0), or GPTC output 0/1. Stop Modes Users can stop waveform generation while it is still in progress, either by hardware or software trigger.
Page 57: Figure 4-15: Stop Mode I
DAQ/DAQe/PXI-250x Series Figure 4-15: Stop mode I (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) Figure 4-16: Stop mode II Operation Theory...
Page 58: Figure 4-17: Stop Mode Iii
Figure 4-17: Stop mode III Operation Theory...
Page 59: General Purpose Digital I/O
DAQ/DAQe/PXI-250x Series 4.3 General Purpose Digital I/O DAQ/DAQE/PXI-250x Series provides 24-line general-purpose digital I/ O (GPIO) through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be individually programmed to be either inputs or outputs.
Page 60: General Purpose Timer/Counter Modes
is a control line, which acts as a counter enable or a counter trig- ger signal in different modes. The output of timer/counter is GPTC_OUT. After power-up, GPTC_OUT is pulled high by a 10K resistor. GPTC_OUT goes low after the DAQ board is initialized. All the polarities of input/output signals can be programmed via software.
Page 61: Figure 4-19: Mode 2 Operation
DAQ/DAQe/PXI-250x Series loaded via software. After the software start, the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE. After the completion of the period mea- surement, GPTC_OUT outputs high and current count value can be read-back by software.
Page 62: Figure 4-21: Mode 4 Operation
Mode 4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software start. These software programmable parameters could be specified in terms of periods of the GPTC_CLK. GPTC_GATE is used to enable/disable counting.
Page 63: Figure 4-22: Mode 5 Operation
DAQ/DAQe/PXI-250x Series Figure 4-22: Mode 5 Operation Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode 5 except that the counter gener- ates a pulse following every active edge on GPTC_GATE. After the software start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width.
Page 64: Figure 4-24: Mode 7 Operation
re-executed. Figure 4-24 illustrates the generation of two pulses with pulse delay of four and pulse-width of three. Figure 4-24: Mode 7 Operation Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval pulse-width following software start.
Page 65: Trigger Sources
DAQ/DAQe/PXI-250x Series 4.5 Trigger Sources We provide flexible trigger selections in DAQ/DAQE/PXI-250x Series. In addition to software trigger, DAQ/DAQE/PXI-250x Series also supports external analog and digital triggers. Users can configure the trigger source for A/D and D/A processes indi- vidually via software. Note that the A/D and the D/A conversion share the same analog trigger.
Page 66: Table 4-8: Analog Trigger Src1 (Extatrig) Ideal Transfer Characteristic
Figure 4-26: Analog trigger block diagram Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80 0x7F -0.08V 0x01 -9.92V 0x00 -10V Table 4-8: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic The trigger signal asserts when an analog trigger condition is meet.
Page 67: Figure 4-28: Above-High Analog Trigger Condition
DAQ/DAQe/PXI-250x Series Above-High analog trigger condition Figure 4-28 shows the above-high analog trigger condition, the trigger signal asserts when the input analog signal is higher than the High_Threshold voltage. The Low_Threshold setting is not used in this trigger condition. Figure 4-28: Above-High analog trigger condition Figure 4-29 shows the inside-region analog trigger condition, the trigger signal asserts when the input analog signal level falls in the range between the High_Threshold and the...
Page 68: Figure 4-30: High-Hysteresis Analog Trigger Condition
higher than the High_Threshold voltage, where the hysteresis region is determined by the Low_Threshold voltage. Figure 4-30: High-Hysteresis analog trigger condition Low-Hysteresis analog trigger condition Figure 4-30 shows the low-hysteresis analog trigger condition, the trigger signal asserts when the input analog signal level is lower than the Low_Threshold voltage, where the hysteresis region is determined by the High_Threshold voltage.
Page 69: Timing Signals
DAQ/DAQe/PXI-250x Series 4.6 Timing Signals In order to meet the requirements for user-specific timing or syn- chronizing multiple boards, DAQ/DAQE/PXI-250x Series provides a flexible interface for connecting timing signals with external cir- cuitry or other boards. The DAQ timing of the DAQ/DAQE/PXI- 250x Series is composed of a bunch of counters and trigger sig- nals in the FPGA on board.
Page 70: System Synchronization Interface
4.6.1 System Synchronization Interface SSI uses bi-directional I/O to provide flexible connections between boards. You can choose each of the 7 timing signals and which board to be the SSI master. The SSI master can drive the timing signals of the slaves. Users can thus achieve better synchroniza- tion between boards.
Page 71: Calibration
DAQ/DAQe/PXI-250x Series Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. DAQ/DAQE/PXI-250x Series is factory calibrated before ship- ment. The onboard high precision band-gap voltage reference together with TrimDAC compensates for unwanted offsets and gain errors, caused by environment variation or component aging.
Page 72: Saving Calibration Constants
5.2 Saving Calibration Constants An onboard EEPROM is used to store calibration constants. In addition to a default bank that stores factory calibration constants, there are three user banks. Users can save the subsequently per- formed calibration constants in anyone of these user banks. ADLINK provides software for users to save calibration constants in an easy manner.
Page 73: Appendix A Waveform Generation Demonstration
DAQ/DAQe/PXI-250x Series Appendix A Waveform Generation Demonstration Combined with 6 counters, selectable trigger sources, external ref- erence sources, and time base, DAQ/DAQE/PXI-250x Series pro- vides the capabilities to generate complex waveforms. Various modes shown below can be mixed together to generate wave- forms that are even more complex.
Page 74 Iterative Generation w. Intermediate Space Utilize DLY2_counter to separate consecutive waveform generations in iterative generation mode. In this demo, the original standard sine wave is repeated several times as specified in IC_counter, with intermediate space determined by DLY2_counter. Piece-wise Generation When the value specified in UC_counter is smaller than the sample size of waveform, the waveform is generated piece-wisely.
Page 75: Important Safety Instructions
DAQ/DAQe/PXI-250x Series Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures ou des dommages.
Page 76 Risk of explosion if battery is replaced with one of an incorrect type; please dispose of used batteries appropriately. Risque d’explosion si la pile est remplacée par une autre de CAUTION: type incorrect. Veuillez jeter les piles usagées de façon appro- priée.
Page 77: Getting Service
6450 Via Del Oro, San Jose, CA 95119-1208, USA Tel: +1-408-360-0200 Toll Free: +1-800-966-5200 (USA only) Fax: +1-408-600-1189 Email: info@adlinktech.com ADLINK Technology (China) Co., Ltd. 300 Fang Chun Rd., Zhangjiang Hi-Tech Park Pudong New Area, Shanghai, 201203 China Tel: +86-21-5132-8988 Fax: +86-21-5132-3588 Email: market@adlinktech.com ADLINK Technology GmbH Hans-Thoma-Straße 11...

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