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ADLINK Technology DAQe-2208 Manuals
Manuals and User Guides for ADLINK Technology DAQe-2208. We have
2
ADLINK Technology DAQe-2208 manuals available for free PDF download: User Manual
ADLINK Technology
DAQe Series
User Manual
ADLINK Technology DAQe-2208 User Manual (102 pages)
64-/96-CH High Performance Multi-Function Data Acquisition Card
Brand:
ADLINK Technology
| Category:
I/O Systems
| Size: 1 MB
Table of Contents
Table of Contents
8
List of Tables
10
1 Introduction
14
Features
15
Applications
16
Specifications
16
Table 1-1: Programmabel Input Range
17
Table 1-2: Bandwidth
18
Table 1-3: System Noise
19
Table 1-4: CMRR (DC to 60 Hz)
19
Table 1-5: Settling Time to Full Scale Step
20
Software Support
26
Programming Library
26
DAQ-LVIEW Pnp: Labview Driver
27
D2K-OCX: Activex Controls
27
2 Installation
28
Contents of Package
28
Unpacking
28
Card Layout
30
Daqe-2204/2205/2206/2208
30
Figure 2-1: Daqe-2204/2205/2206/2208 Card Layout
30
Daq-2204/2205/2206/2208
31
Pxi-2204/2205/2206/2208
31
Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout
31
Figure 2-3: PXI-2204/2205/2206/2208 Card Layout
31
PCI Configuration
32
Plug and Play
32
Configuration
32
Troubleshooting
32
3 Signal Connections
34
Connectors Pin Assignment
34
CN1 Connector
35
Table 3-1: CN1 Pin Assignment for DAQ-/Daqe-/PXI-2204/2205/2206
35
Table 3-2: CN1 Pin Assignment for DAQ-/Daqe-/PXI-2208
36
CN2 Connector
37
Table 3-3: CN2 Pin Assignment for DAQ-/Daqe-/PXI-2204/2205/2206
37
Table 3-4: CN2 Pin Assignment Fordaq-/Daqe-/PXI-2208
38
Table 3-5: CN1/CN2 Signal Description
39
SSI Connector
41
Table 3-6: SSI Connector Pin Assignment
41
Table 3-7: SSI Connector Legend
41
Analog Input Signal Connection
42
Types of Signal Sources
42
Input Configurations
42
Figure 3-1: Floating Source and RSE Input Connections
43
Figure 3-2: Ground-Referenced Sources and NRSE Input Connections
43
Differential Input Mode
44
Figure 3-3: Ground-Referenced Source and Differential Input
44
Figure 3-4: Floating Source and Differential Input
44
4 Operation Theory
46
A/D Conversion
46
DAQ-/Daqe-/PXI-2204/2208 AI Data Format
46
Figure 4-1: Synchronous Digital Inputs Block Diagram
47
Figure 4-2: Synchronous Digital Inputs Timing
47
Table 4-1: Bipolar Analog Input Range and Output Digital Code on Daq/Daqe/Pxi-2204/2208
48
Table 4-2: Unipolar Analog Input Range and Output Digital Code on Daq/Daqe/Pxi-2204/2208
48
Daq/Daqe/Pxi-2005/2006/2016 AI Data Format
49
Table 4-3: Bipolar Analog Input Range and Output Digital Code for Daq/Daqe/Pxi-2205/2206
49
Table 4-4: Unipolar Analog Input Range and Output Digital Code for Daq/Daqe/Pxi-2205/2206
49
Software Conversion with Polling Data Transfer
50
Acquisition Mode (Software Polling)
50
Programmable Scan Acquisition Mode
51
Figure 4-3: Scan Timing
52
Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue
53
Trigger Modes
55
Figure 4-4: Pre-Trigger (Trigger Occurs after M Scans)
56
Figure 4-5: Pre-Trigger (Trigger with Scan in Progress)
57
Figure 4-6: Pre-Trigger with M_Enable=0 (Trigger Occurs before M Scans)
58
Figure 4-7: Pre-Trigger with M_Enable=1
59
Figure 4-8: Middle-Trigger with M_Enable = 1
60
Figure 4-9: Middle-Trigger (Trigger Occurs When a Scan Is in Progress)
61
Figure 4-10: Post-Trigger
62
Figure 4-11: Delay Trigger
63
Figure 4-12: Post Trigger with Re-Trigger
64
Bus-Mastering DMA Data Transfer
65
Figure 4-13: Scatter/Gather DMA for Data Transfer
66
D/A Conversion
67
Table 4-5: Bipolar Output Code Table
67
Software Update
68
Table 4-6: Unipolar Output Code Table
68
Timed Waveform Generation
69
Figure 4-14: Typical D/A Timing of Waveform Generation
70
Figure 4-15: Post Trigger Waveform Generation
71
Trigger Modes
71
Figure 4-16: Delay Trigger Waveform Generation
72
Figure 4-17: Re-Triggered Waveform Generation with
72
Figure 4-18: Finite Iterative Waveform Generation with
73
Figure 4-19: Infinite Iterative Waveform Generation with
74
Figure 4-20: Stop Mode I
75
Figure 4-21: Stop Mode II
76
Figure 4-22: Stop Mode III
76
Digital I/O
77
General Purpose Timer/Counter Operation
77
The Basics of Timer/Counter Functions
78
General Purpose Timer/Counter Modes
78
Figure 4-23: Mode1 Operation
79
Figure 4-24: Mode2 Operation
80
Figure 4-25: Mode3 Operation
80
Figure 4-26: Mode4 Operation
81
Figure 4-27: Mode5 Operation
82
Figure 4-28: Mode6 Operation
82
Figure 4-29: Mode7 Operation
83
Figure 4-30: Mode8 Operation
83
Trigger Sources
84
Software-Trigger
84
External Analog Trigger
84
Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic
85
Figure 4-31: Analog Trigger Block Diagram
85
Figure 4-32: Below-Low Analog Trigger Condition
86
Figure 4-33: Above-High Analog Trigger Condition
86
Figure 4-34: Inside-Region Analog Trigger Condition
87
Figure 4-35: High-Hysteresis Analog Trigger Condition
88
Figure 4-36: Low-Hysteresis Analog Trigger Condition
88
Figure 4-37: External Digital Trigger
89
User-Controllable Timing Signals
90
Figure 4-38: DAQ Signals Routing
90
DAQ Timing Signals
91
Table 4-8: User-Controllable Timing Signals and
91
Auxiliary Function Inputs (AFI)
93
Table 4-9: Auxiliary Function Input Signals and
93
System Synchronization Interface
95
Table 4-10: SSI Timing Signal and Functions
95
5 Calibration
98
Loading Calibration Constants
98
Auto-Calibration
99
Saving Calibration Constants
99
Warranty Policy
100
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ADLINK Technology DAQe-2208 User Manual (109 pages)
64-/96-ch High Performance Multi-Function Data Acquisition Card
Brand:
ADLINK Technology
| Category:
PCI Card
| Size: 2 MB
Table of Contents
Revision History
2
California Proposition 65 Warning
4
Table of Contents
5
List of Tables
7
List of Figures
9
Introduction
11
Features
12
Applications
13
Specifications
14
Table 1-1: Programmabel Input Range
15
Table 1-2: Bandwidth
16
Table 1-3: System Noise
17
Input Impedance
17
Table 1-4: CMRR (DC to 60 Hz)
17
Table 1-5: Settling Time to Full Scale Step
18
Software Support
24
Installation
29
Contents of Package
29
Unpacking
30
Card Layout
31
Figure 2-1: Daqe-2204/2205/2206/2208 Card Layout
31
Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout
32
Figure 2-3: PXI-2204/2205/2206/2208 Card Layout
32
Switch and Jumper Settings
33
Figure 2-4: Board ID SW1 DIP Switch
33
Table 2-1: Board ID SW1 DIP Switch Pin Definitions
34
Figure 2-5: Enable Board ID Configuration
35
Figure 2-6: DIO Initial Status (JP4)
36
PCI Configuration
37
Troubleshooting
37
Signal Connections
39
Connectors Pin Assignment
39
Table 3-1: CN1 Pin Assignment for Daq/Daqe/Pxi-2204/2205/2206
40
Table 3-2: CN1 Pin Assignment for Daq/Daqe/Pxi-2208
41
Table 3-3: CN2 Pin Assignment for Daq/Daqe/Pxi-2204/2205/2206
42
Table 3-4: CN2 Pin Assignment for Daq/Daqe/Pxi-2208
43
Table 3-5: CN1/CN2 Signal Description
44
Table 3-6: SSI Connector Pin Assignment
45
Table 3-7: SSI Connector Pin Assignment on PXI J2
46
Table 3-8: SSI Connector Legend
46
Analog Input Signal Connection
47
Figure 3-1: Floating Source and RSE Input Connections
48
Figure 3-2: Ground-Referenced Sources and NRSE Input
49
Differential Input Mode
49
Figure 3-3: Ground-Referenced Source and Differential Input
49
Figure 3-4: Floating Source and Differential Input
50
Operation Theory
51
A/D Conversion
51
Figure 4-1: Synchronous Digital Inputs Block Diagram
52
Figure 4-2: Synchronous Digital Inputs Timing
52
Table 4-1: Bipolar Analog Input Range and Output Digital Code on Daq/Daqe/Pxi-2204/2208
53
Table 4-2: Unipolar Analog Input Range and Output Digital Code on Daq/Daqe/Pxi-2204/2208
53
Table 4-3: Bipolar Analog Input Range and Output Digital Code for Daq/Daqe/Pxi-2205/2206
54
Table 4-4: Unipolar Analog Input Range and Output Digital Code for Daq/Daqe/Pxi-2205/2206
54
Programmable Scan Acquisition Mode
56
Figure 4-3: Scan Timing
57
Trigger Modes
59
Pre-Trigger Acquisition
60
Figure 4-4: Pre-Trigger (Trigger Occurs after M Scans)
60
Figure 4-5: Pre-Trigger (Trigger with Scan in Progress)
61
Figure 4-6: Pre-Trigger with M_Enable=0 (Trigger Occurs before M Scans)
62
Figure 4-7: Pre-Trigger with M_Enable=1
63
Middle-Trigger Acquisition
64
Figure 4-8: Middle-Trigger with M_Enable = 1
64
Figure 4-9: Middle-Trigger (Trigger Occurs When a Scan Is in Progress)
65
Figure 4-10: Post-Trigger
66
Figure 4-11: Delay Trigger
67
Figure 4-12: Post Trigger with Re-Trigger
68
Figure 4-13: Linked List of PCI Address DMA Descriptors
70
D/A Conversion
71
Table 4-5: Bipolar Output Code Table
71
Table 4-6: Unipolar Output Code Table
72
Software Update
72
Figure 4-14: Typical D/A Timing of Waveform Generation
74
Figure 4-15: Post Trigger Waveform Generation
75
Delay-Trigger Generation
75
Figure 4-16: Delay Trigger Waveform Generation
76
Figure 4-17: Re-Triggered Waveform Generation with Post-Trigger (Dly2_Counter=0)
76
Figure 4-18: Finite Iterative Waveform Generation with Post-Trigger (Dly2_Counter = 0)
77
Figure 4-19: Infinite Iterative Waveform Generation with Post-Trigger (Dly2_Counter = 0)
78
Figure 4-20: Stop Mode I
79
Figure 4-21: Stop Mode II
80
Figure 4-22: Stop Mode III
80
Digital I/O
81
General Purpose Timer/Counter Operation
81
Figure 4-23: Mode1 Operation
83
Figure 4-24: Mode2 Operation
83
Figure 4-25: Mode3 Operation
84
Figure 4-26: Mode4 Operation
85
Figure 4-27: Mode5 Operation
86
Figure 4-28: Mode6 Operation
87
Figure 4-29: Mode7 Operation
87
Figure 4-30: Mode8 Operation
88
Trigger Sources
89
Software-Trigger
89
External Analog Trigger
89
Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer
90
Figure 4-31: Analog Trigger Block Diagram
90
Figure 4-32: Below-Low Analog Trigger Condition
91
Figure 4-33: Above-High Analog Trigger Condition
91
Figure 4-34: Inside-Region Analog Trigger Condition
92
Figure 4-35: High-Hysteresis Analog Trigger Condition
93
Figure 4-36: Low-Hysteresis Analog Trigger Condition
94
Figure 4-37: External Digital Trigger
95
User-Controllable Timing Signals
96
Figure 4-38: DAQ Signals Routing
96
Table 4-8: User-Controllable Timing Signals and Functionalities
97
Table 4-9: Auxiliary Function Input Signals and Functionalities
99
System Synchronization Interface
101
Table 4-10: SSI Timing Signal and Functions
101
Calibration
105
Loading Calibration Constants
105
Auto-Calibration
106
Saving Calibration Constants
106
Important Safety Instructions
107
Getting Service
109
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