Cisco UBR924 - uBR 924 Router Troubleshooting Tips page 24

show controllers cable-modem
Table 2
Field
TX PD ring:
tx_head_pd
tx_tail_pd
ehdr
MIB Statistics:
DS fifo full
rerequests
DS mac msg overruns
DS data overruns
Qualified maps
Qualified syncs
CRC fails
HDR chk fails
Data pdus
Mac msgs
Valid hdrs
Global control and status:
interrupts:
24 Cisco IOS Release 12.0(5)T
Show Controllers Cable-Modem Field Descriptions (continued)
Description
Indicates the memory location of the beginning of buffer information for the transmit
packet descriptor ring.
Indicates current head packet descriptor.
Indicates current tail packet descriptor.
Extended MCNS header.
Number of times the downstream input first-in first-out (FIFO) buffer became full on
the Cisco uBR924.
Number of times a bandwidth request generated by the Cisco uBR924 was not
responded to by the CMTS.
Number of times the Cisco uBR924's DMA controller had a downstream MAC
message and there were no free MAC message buffer descriptors to accept the message.
Number of times the Cisco uBR924's DMA controller had downstream data and there
were no free data PDU buffer descriptors to accept the data.
Number of times a MAP message passed all filtering requirements and was received by
the Cisco uBR924.
Number of times a timestamp message was received by the Cisco uBR924.
Number of times a MAC message failed a cyclic redundancy (CRC) check.
Number of times a MAC header failed its 16-bit CRC check. The MAC header CRC is a
16-bit Header Check Sequence (HCS) field that ensures the integrity of the MAC
header even in a collision environment.
Total number of data PDUs (protocol data units) of all types received by the
Cisco uBR924.
Number of MAC messages received by the Cisco uBR924.
Number of valid headers received by the Cisco uBR924, including PDU headers, MAC
headers, and headers only.
Used to reset the BCM3300 chip.
Hexadecimal values of the pending IRQ interrupt and IRQ mask.