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Programming Lock for Software Security
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JTAG (IEEE std. 1149.1 Compliant) Interface
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Boundary-scan Capabilities According to the JTAG Standard
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Extensive On-chip Debug Support
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Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
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Interface
Peripheral Features
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Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
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One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
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Capture Mode
Real Time Counter with Separate Oscillator
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Four PWM Channels
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8-channel, 10-bit ADC
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8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
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Programmable Serial USART
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Master/Slave SPI Serial Interface
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Programmable Watchdog Timer with Separate On-chip Oscillator
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On-chip Analog Comparator
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Special Microcontroller Features
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Power-on Reset and Programmable Brown-out Detection
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Internal Calibrated RC Oscillator
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External and Internal Interrupt Sources
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Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
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Standby and Extended Standby
I/O and Packages
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32 Programmable I/O Lines
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Operating Voltages
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2.7 - 5.5V
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Speed Grades
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0 - 8 MHz
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Power Consumption @ 1 MHz, 3V, and 25⋅C
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Active: 1.1 mA
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Page 5
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