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Infineon AURIX TC37 Series Manual

Infineon AURIX TC37 Series Manual

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AURIX™ TC37x
About this document
Scope and purpose
The Appendix supplies information specific for the TC37x supplementing the family documentation.
User's Manual
Please read the Important Notice and Warnings at the end of this document
www.infineon.com
OPEN MARKET VERSION
V2.0.0
2021-02

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Summary of Contents for Infineon AURIX TC37 Series

  • Page 1 AURIX™ TC37x About this document Scope and purpose The Appendix supplies information specific for the TC37x supplementing the family documentation. User’s Manual Please read the Important Notice and Warnings at the end of this document V2.0.0 www.infineon.com 2021-02 OPEN MARKET VERSION...

  • Page 2: Table Of Contents

    AURIX™ TC37x Table of Contents About this document............Preface-1 Table of Contents .
  • Page 3 AURIX™ TC37x 6.3.4 Revision History ............... . 6-18 Non Volatile Memory (NVM) .
  • Page 4 AURIX™ TC37x 14.3.1 SPB bus slave interface ..............14-28 14.4 Connectivity .
  • Page 5 AURIX™ TC37x 25.5 Revision History ................25-2 Generic Timer Module (GTM) .
  • Page 6 AURIX™ TC37x 31.3 Connectivity ................31-2 31.3.1 Analog Module Connections .
  • Page 7 AURIX™ TC37x 37.4.1 Interrupt and DMA Controller Service Requests ..........37-2 37.4.2 Trigger Inputs .
  • Page 8 AURIX™ TC37x 46.3 TC37x Specific Registers ..............46-1 46.4 Connectivity .

  • Page 9: Introduction

    AURIX™ TC37x Introduction Introduction For Introduction, block diagrams and feature set consult the family document. For Pinning consult the Data Sheet. User’s Manual V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 10: Memory Maps (Memmap)

    AURIX™ TC37x Memory Maps (MEMMAP) Memory Maps (MEMMAP) This is the automatically generated memory map of the TC37x. Overview The memory map describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from the different on-chip buses’ point of view. Functional Description The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses.

  • Page 11: Bus Fabric Sri

    AURIX™ TC37x Memory Maps (MEMMAP) The attribute of these segments (cached / non-cached) can be partially configured for each CPUs data and program side individually (see CPU chapter: Physical Memory Attribute Registers, PMAx). Segment 8 This memory segment allows cached access to PFlash and BROM. Segment 9 This memory segment allows cached access to LMU and to EMEM.
  • Page 12 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write 501C0000 501C2FFF 12 Kbyte Program Cache TAG RAM (CPU2) 501C3000 5FFFFFFF Reserved 60000000 6003BFFF 240 Kbyte Data ScratchPad RAM (CPU1)
  • Page 13 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write A0000000 A02FFFFF 3 Mbyte Program Flash (PFI0_NC) A0300000 A05FFFFF 3 Mbyte Program Flash (PFI1_NC) A0600000 A7FFFFFF Reserved...
  • Page 14 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write AF400000 AF405FFF 24 Kbyte UCB_BMHD0_ORIG (UCB) UCB_BMHD1_ORIG (UCB) UCB_BMHD2_ORIG (UCB) UCB_BMHD3_ORIG (UCB) UCB_SSW (UCB) UCB_USER (UCB) UCB_TEST (UCB) UCB_HSMCFG (UCB)
  • Page 15 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write cont’d UCB_OTP0_ORIG (UCB) UCB_OTP1_ORIG (UCB) UCB_OTP2_ORIG (UCB) UCB_OTP3_ORIG (UCB) UCB_OTP4_ORIG (UCB) UCB_OTP5_ORIG (UCB) UCB_OTP6_ORIG (UCB) UCB_OTP7_ORIG (UCB) UCB_OTP0_COPY (UCB)
  • Page 16 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write F8080000 F84FFFFF Reserved F8500000 F8507FFF 32 Kbyte Special Function Registers (DAM0) F8508000 F85080FF 256 byte sri slave interface (AMU00) F8508100...

  • Page 17: Bus Instance Spb

    AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SRI (cont’d) Table 2 Address Range Size Unit Access Type from Read Write F8840000 F885FFFF 128 Kbyte Safety Memory Protection Register (CPU2) DLMU Safety Memory Protection registers (CPU2) Safety register protection registers (CPU2) Kernel Reset registers (CPU2) Flash Configuration registers (CPU2)
  • Page 18 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SPB (cont’d) Table 3 Address Range Size Unit Access Type from Read Write F0000E00 F0000EFF 256 byte FPI slave interface (ASCLIN8) F0000F00 F0000FFF 256 byte FPI slave interface (ASCLIN9) F0001000 F00010FF 256 byte...
  • Page 19 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SPB (cont’d) Table 3 Address Range Size Unit Access Type from Read Write F0025100 F002FFFF Reserved F0030000 F00300FF 256 byte BCU Registers (SBCU) F0030100 F0034FFF Reserved F0035000 F00351FF 512 byte...
  • Page 20 AURIX™ TC37x Memory Maps (MEMMAP) Address Map as seen by Bus Masters on Bus SPB (cont’d) Table 3 Address Range Size Unit Access Type from Read Write F0060000 F006FFFF 64 Kbyte FPI slave interface (MTU) FPI slave interface (MTU) F0070000 F007FFFF Reserved F0080000...

  • Page 21: Revision History

    AURIX™ TC37x Memory Maps (MEMMAP) Revision History Table 4 Revision History Reference Change to Previous Version Comment V0.1.12 – Formal change: for some memory ranges (e.g. “PFI0”) the name was – changed by appending “_NC” to “PFI0_NC” to ensure that derived tool files contain different symbols for cached and non-cached memory ranges.

  • Page 22: Tc37X Firmware

    AURIX™ TC37x TC37x Firmware TC37x Firmware This chapter supplements the family documentation with device specific information for TC37x devices. Checker Software exit information for ALL CHECKS PASSED Below the SCU_STMEM3...SCU_STMEM6 registers’ content corresponding to “ALL CHECKS PASSED” result from Checker Software (CHSW) upon different device reset types is shown. Table 5 “ALL CHECKS PASSED”...

  • Page 23: On-Chip System Connectivity {And Bridges

    AURIX™ TC37x On-Chip System Connectivity {and Bridges} On-Chip System Connectivity {and Bridges} Text with reference to family spec. TC37x Specific IP Configuration Table 7 TC37x specific configuration of DOM Parameter DOM0 Application Reset Application Reset Access only when any Endinit (SCU_WDTCPUxCON0.EI ENDINIT = 0 for any CPUx) Safety ENDINIT...

  • Page 24: Tc37X Specific Register Set

    AURIX™ TC37x On-Chip System Connectivity {and Bridges} TC37x Specific Register Set Register Address Space Table Table 8 Register Address Space - DOM Module Base Address End Address Note (DOM0) 8FE00000 8FE7FFFF Online Data Acquisition (OLDA) AFE00000 AFE7FFFF Online Data Acquisition (OLDA) DOM0 F8700000 F870FFFF...
  • Page 25 AURIX™ TC37x On-Chip System Connectivity {and Bridges} Register Overview - DOM0 (ascending Offset Address) (cont’d) Table 9 Short Name Description Offset Access Mode Page Address Number Read Write DOM0_ACCEN0 Access Enable Register 0 004F0 32,U,SV 32,SV,SE See Family Spec DOM0_ACCEN1 Access Enable Register 1 004F8 32,U,SV 32,SV,SE See...

  • Page 26: Tc37X Specific Registers

    AURIX™ TC37x On-Chip System Connectivity {and Bridges} TC37x Specific Registers 4.3.1 sri slave interface Domain 0 Bridge Control Register DOM0_BRCON Domain 0 Bridge Control Register (00430 Application Reset Value: 0000 0200 OLDAE Field Bits Type Description OLDAEN Online Data Acquisition Enable This bit is used to control trap generated for write accesses to the OLDA address range associated with this domain.

  • Page 27: Revision History

    AURIX™ TC37x On-Chip System Connectivity {and Bridges} r/w MCI has read write connectivity to SCI MCI has only read connectivity to SCI MCI has no connectivity to SCI DMA MIF0 MCI0 r/w r/w r.o r/w r.o r/w r/w SFI F2S MCI1 r/w r/w r.o r/w r.o...

  • Page 28: Fpi Bus Control Units (Sbcu)

    AURIX™ TC37x FPI Bus Control Units (SBCU) This chapter supplements the family documentation with device specific information for TC37x. 4.7.1 TC37x Specific IP Configuration The TC37x includes one FPI Bus instance. Each FPI Bus instance has its dedicated Bus Control Unit: Table 11 Register Address Space - BCU Module...

  • Page 29: Sbcu Control Unit Registers

    AURIX™ TC37x 4.7.2 SBCU Control Unit Registers are showing the address maps with all registers of the System Bus Control Unit (SBCU) Figure 2 Table 12 module. SBCU Control Registers Overview BCU System Registers FPI EDC Registers Access Enable Module ID EDC Alarm Status EDC Alarm Clear Register...
  • Page 30 AURIX™ TC37x Register Overview - SBCU (ascending Offset Address) (cont’d) Table 12 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SBCU_ECON BCU Error Control Capture 0020 U,SV SV,P Application Register Reset Family Spec SBCU_EADD BCU Error Address Capture 0024 U,SV SV,P...
  • Page 31 AURIX™ TC37x Register Overview - SBCU (ascending Offset Address) (cont’d) Table 12 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SBCU_FEGEN FPI Error Generation 0084 U,SV SV,SE Application Control Register Reset Family Spec SBCU_ACCEN1 Access Enable Register 1 00F8 U,SV SV,SE...

  • Page 32: Sbcu Control Registers Descriptions

    AURIX™ TC37x 4.7.2.1 SBCU Control Registers Descriptions Note: For all PRIOH / PRIOL bit fields, a lower number has a higher priority in the arbitration round than a higher one. Arbiter Priority Register High SBCU_PRIOH Arbiter Priority Register High (0014 Application Reset Value: FEDC 8888 RESERVED RESERVED...
  • Page 33 AURIX™ TC37x Field Bits Type Description DMA / Cerberus Priority (Index 0) This bit field defines the priority on the SPB for DMA and Cerberus access to the SPB. 7:4, RESERVED Reserved 11:8, Read as reset value or last written value; should be written with 0. 19:16, 23:20 15:12...

  • Page 34: Sbcu Ocds Registers Descriptions

    AURIX™ TC37x 4.7.2.2 SBCU OCDS Registers Descriptions SBCU Debug Grant Mask Register SBCU_DBGRNT SBCU Debug Grant Mask Register (0034 Debug Reset Value: 0000 FFFF HSMC HSMR CPU2 CPU1 CPU0 HSSL0 Field Bits Type Description DMA / Cerberus Trigger Enable FPI Bus transactions with DMA / Cerberus as bus master are enabled for grant trigger event generation.
  • Page 35 AURIX™ TC37x Field Bits Type Description HSMCMI HSM Cache Master Interface Grant Trigger Enable FPI Bus transactions requested by the HSM bus master are enabled for grant trigger event generation. FPI Bus transactions requested by the HSM bus master are disabled for grant trigger event generation.
  • Page 36 AURIX™ TC37x Field Bits Type Description CPU1 CPU1 FPI Bus Master Status This bit indicates whether the CPU1 was FPI Bus master when the break trigger event occurred. The CPU1 was the FPI Bus master. The CPU1 was not the FPI Bus master. CPU2 CPU2 Grant Trigger Enable FPI Bus transactions with CPU2 as bus master are enabled for grant...
  • Page 37 AURIX™ TC37x Field Bits Type Description ALy (y=00) Alarm y SBCU_S, an EDC error was detected in an active phase of the SBCU Slave Interface. ALy (y=01) Alarm y DMA_S, ALy (y=02) Alarm y IR_S, ALy (y=03) Alarm y SFI_F2S_S, ALy (y=04) Alarm y SCU_S,...
  • Page 38 AURIX™ TC37x Field Bits Type Description ALy (y=20) Alarm y FCE0_S, ALy (y=22) Alarm y STM0_S, ALy (y=23) Alarm y STM1_S, ALy (y=24) Alarm y STM2_S, ALy (y=28) Alarm y PSI5_S, ALy (y=29) Alarm y PSI5S_S, ALy (y=30) Alarm y ERAY0_S, SBCU_ALSTATx (x=1) BCU EDC Alarm Status Register x...
  • Page 39 AURIX™ TC37x Field Bits Type Description ALy (y=08) Alarm y ETH_S, ALy (y=09) Alarm y EVADC_S, ALy (y=10) Alarm y EDSADC_S, ALy (y=11) Alarm y HSM_S, ALy (y=12) Alarm y HSSL0_S, ALy (y=13) Alarm y CAN0_S, ALy (y=14) Alarm y CAN1_S, ALy (y=16) Alarm y...
  • Page 40 AURIX™ TC37x Field Bits Type Description ALy (y=02) Alarm y P02_S, Alarm y (y=03,10,15- 20,24,26- 28,30) ALy (y=04) Alarm y P10_S, ALy (y=05) Alarm y P11_S, ALy (y=06) Alarm y P12_S, ALy (y=07) Alarm y P13_S, ALy (y=08) Alarm y P14_S, ALy (y=09) Alarm y...

  • Page 41: Connectivity

    AURIX™ TC37x SBCU_ALSTATx (x=3) BCU EDC Alarm Status Register x (0060 +x*4) Application Reset Value: 0000 0000 AL31 AL30 AL29 AL28 AL27 AL26 AL25 AL24 AL23 AL22 AL21 AL20 AL19 AL18 AL17 AL16 AL15 AL14 AL13 AL12 AL11 AL10 AL09 AL08 AL07 AL06 AL05 AL04 AL03 AL02 AL01 AL00 Field Bits Type...

  • Page 42: Sbcu Connectivity

    AURIX™ TC37x 4.7.3.1 SBCU Connectivity Table 13 List of SBCU Interface Signals Interface Signals Description Bus Control Unit SPB Service Request Bus Control Unit BBB Service Request Table 14 Connections of SBCU Interface Signals connects Description SBCU:INT INT:sbcu.INT Bus Control Unit SPB Service Request 4.7.4 Revision History Table 15...

  • Page 43: Cpu Subsystem (Cpu)

    AURIX™ TC37x CPU Subsystem (CPU) CPU Subsystem (CPU) This chapter describes the CPU subsystem module of the TC37x. TC37x Specific Configuration No product specific configuration for CPU TC37x Specific Register Set Register Address Space Table Table 16 Register Address Space - CPU Module Base Address End Address...
  • Page 44 AURIX™ TC37x CPU Subsystem (CPU) Register Overview Table Register Overview Tables of CPU Table 17 Register Overview - CPU0 (ascending Offset Address) Short Name Long Name Offset Page Address Number CPU0_FLASHCON0 CPUx Flash Configuration Register 0 01100 CPU0_FLASHCON1 CPUx Flash Configuration Register 1 01104 Family Spec...
  • Page 45 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_SPR_SPROT_R CPUx Safety Protection SPR Region Read Access Enable 0E08C +i*10 GNACCENBi_R Register Bi Family (i=0-7) Spec CPU0_SFR_SPROT_A CPUx Safety Protection Register Access Enable Register A 0E100...
  • Page 46 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_OMASKi CPUx Overlay Mask Register i 0FB18 +i*12 (i=0-31) Family Spec CPU0_SEGEN CPUx SRI Error Generation Register 11030 Family Spec...
  • Page 47 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_PSTR CPUx Program Synchronous Trap Register 19200 Family Spec CPU0_PCON1 CPUx Program Control 1 19204 Family Spec CPU0_PCON2 CPUx Program Control 2 19208...
  • Page 48 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_DPRy_U CPUx Data Protection Range y, Upper Bound Register 1C004 +y*8 (y=0-17) Family Spec CPU0_CPRy_L CPUx Code Protection Range y Lower Bound Register 1D000 +y*8 (y=0-9)
  • Page 49 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_TPS_EXTIM_E CPUx Exception Exit Timer Current Value 1E44C XIT_CVAL Family Spec CPU0_TPS_EXTIM_C CPUx Exception Timer Class Enable Register 1E450 LASS_EN Family...
  • Page 50 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_CREVT CPUx Core Register Access Event 1FD0C Family Spec CPU0_SWEVT CPUx Software Debug Event 1FD10 Family Spec CPU0_TRIG_ACC CPUx TriggerAddressx 1FD30...
  • Page 51 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU0 (ascending Offset Address) (cont’d) Table 17 Short Name Long Name Offset Page Address Number CPU0_ISP CPUx Interrupt Stack Pointer 1FE28 Family Spec CPU0_ICR CPUx Interrupt Control Register 1FE2C Family Spec CPU0_FCX CPUx Free CSA List Head Pointer 1FE38 Family...
  • Page 52 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_KRST1 CPUx Reset Register 1 0D004 Family Spec CPU1_KRSTCLR CPUx Reset Clear Register 0D008 Family Spec CPU1_SPR_SPROT_R CPUx Safety Protection SPR Region Lower Address Register i 0E000 +i*10 GNLAi...
  • Page 53 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_DLMU_SPROT CPUx Safety Protection Region DLMU Write Access Enable 0E208 +i*10 _RGNACCENAi_W Register Ai Family (i=0-7) Spec CPU1_DLMU_SPROT CPUx Safety Protection Region DLMU Write Access Enable 0E20C...
  • Page 54 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_SMACON CPUx SIST Mode Access Control Register 1900C Family Spec CPU1_DSTR CPUx Data Synchronous Trap Register 19010 Family Spec CPU1_DATR...
  • Page 55 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_FPU_TRAP_CO CPUx Trap Control Register 1A000 Family Spec CPU1_FPU_TRAP_PC CPUx Trapping Instruction Program Counter Register 1A004 Family Spec CPU1_FPU_TRAP_OP CPUx Trapping Instruction Opcode Register...
  • Page 56 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_DPRE_y CPUx Data Protection Read Enable Register Set y 1E050 +(y- (y=4-5) 4)*4 Family Spec CPU1_DPWE_y CPUx Data Protection Write Enable Register Set y 1E060 +(y- (y=4-5)
  • Page 57 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_CCNT CPUx CPU Clock Cycle Count 1FC04 Family Spec CPU1_ICNT CPUx Instruction Count 1FC08 Family Spec CPU1_M1CNT CPUx Multi-Count Register 1 1FC0C Family...
  • Page 58 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU1 (ascending Offset Address) (cont’d) Table 18 Short Name Long Name Offset Page Address Number CPU1_PSW CPUx Program Status Word 1FE04 Family Spec CPU1_PC CPUx Program Counter 1FE08 Family Spec CPU1_SYSCON CPUx System Configuration Register 1FE14 Family Spec...
  • Page 59 AURIX™ TC37x CPU Subsystem (CPU) Table 19 Register Overview - CPU2 (ascending Offset Address) Short Name Long Name Offset Page Address Number CPU2_FLASHCON0 CPUx Flash Configuration Register 0 01100 Family Spec CPU2_FLASHCON1 CPUx Flash Configuration Register 1 01104 Family Spec CPU2_FLASHCON2 CPUx Flash Configuration Register 2 01108...
  • Page 60 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_SFR_SPROT_A CPUx Safety Protection Register Access Enable Register A 0E100 CCENA_W Family Spec CPU2_SFR_SPROT_A CPUx Safety Protection Region Access Enable Register B 0E104 CCENB_W Family...
  • Page 61 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_SEGEN CPUx SRI Error Generation Register 11030 Family Spec CPU2_TASK_ASI CPUx Task Address Space Identifier Register 18004 Family Spec CPU2_PMA0...
  • Page 62 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_PCON1 CPUx Program Control 1 19204 Family Spec CPU2_PCON2 CPUx Program Control 2 19208 Family Spec CPU2_PCON0 CPUx Program Control 0 1920C Family...
  • Page 63 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_CPRy_L CPUx Code Protection Range y Lower Bound Register 1D000 +y*8 (y=0-9) Family Spec CPU2_CPRy_U CPUx Code Protection Range y Upper Bound Register 1D004 +y*8 (y=0-9)
  • Page 64 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_TPS_EXTIM_C CPUx Exception Timer Class Enable Register 1E450 LASS_EN Family Spec CPU2_TPS_EXTIM_S CPUx Exception Timer Status Register 1E454 Family Spec...
  • Page 65 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_SWEVT CPUx Software Debug Event 1FD10 Family Spec CPU2_TRIG_ACC CPUx TriggerAddressx 1FD30 Family Spec CPU2_DMS CPUx Debug Monitor Start Address 1FD40 Family Spec...
  • Page 66 AURIX™ TC37x CPU Subsystem (CPU) Register Overview - CPU2 (ascending Offset Address) (cont’d) Table 19 Short Name Long Name Offset Page Address Number CPU2_ICR CPUx Interrupt Control Register 1FE2C Family Spec CPU2_FCX CPUx Free CSA List Head Pointer 1FE38 Family Spec CPU2_LCX CPUx Free CSA List Limit Pointer...

  • Page 67: Tc37X Specific Registers

    AURIX™ TC37x CPU Subsystem (CPU) TC37x Specific Registers 5.3.1 SRI slave interface for SFR+CSFR CPUx Flash Configuration Register 0 Software may program a Flash Prefetch Buffer with a master tag identifier stored in Flash Configuration Register If a CPU instance does not have a local PFlash bank then the FLASHCON0 register associated with that instance will have no functionality.

  • Page 68: Connectivity

    AURIX™ TC37x CPU Subsystem (CPU) Table 21 Reset Values of CPU1_FLASHCON0 Reset Type Reset Value Note Application Reset 3F3F 3F3F CFS Value 2220 2021 Connectivity No connections in TC37x Revision History Table 22 Revision History Reference Change to Previous Version Comment V1.1.16 No change...

  • Page 69: Non Volatile Memory (Nvm) Subsystem

    AURIX™ TC37x Non Volatile Memory (NVM) Subsystem Non Volatile Memory (NVM) Subsystem Overview The Non Volatile Memory (NVM) Subsystem comprises of the Data Memory Unit (DMU), Program Flash Interface (PFI), and Non Volatile Memory module (comprising of the Flash Standard Interface (FSI), Program and Data Flash memories and Program Flash Read Write buffer (PFRWB)).
  • Page 70 AURIX™ TC37x Non Volatile Memory (NVM) Subsystem CPUn SRI SIF PFIn BROM PFRWBn FSI RAM FSI REG DFRWB0 DFRWB1 Figure 3 Non Volatile Memory (NVM) Subsystem The purpose of the PFLASH NVM is: • One or more PFLASH banks stores program code and data constants. •...
  • Page 71 AURIX™ TC37x Non Volatile Memory (NVM) Subsystem • Write protection is enabled/disabled with a Flash Module sector based granularity. Safety Layer • Master specific read access protection to each Flash Module (Bank). • Master specific read and write access control to individual Special Function Registers (SFRs). •...

  • Page 72: Revision History

    AURIX™ TC37x Non Volatile Memory (NVM) Subsystem Revision History Table 23 Revision History Reference Change to Previous Version Comment V2.0.3 Created to form a concise introduction chapter for the appendices V2.0.4 No Changes. V2.0.5 No Changes. V2.0.6 No Changes. V2.0.7 No Changes.

  • Page 73: Data Memory Unit (Dmu)

    AURIX™ TC37x Data Memory Unit (DMU) This chapter supplements the family documentation with the device specific information for TC37x. User’s Manual V2.0.0 DMUV2.0.12 2021-02 OPEN MARKET VERSION...

  • Page 74: Tc37X Specific Register Set

    AURIX™ TC37x 6.3.1 TC37x Specific Register Set Register Address Space Table Table 24 Register Address Space - PMU Module Base Address End Address Note F8038000 F803FFFF sri slave interface Table 25 Register Address Space - DMU Module Base Address End Address Note (DMU) 8FFF0000...
  • Page 75 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HF_OPERA Flash Operation Register 0000018 U,SV System Reset TION Family Spec DMU_HF_PROTE Flash Protection Status 000001C U,SV Application...
  • Page 76 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HF_PCONT Power Control Register 0000064 U,SV P,SV Application Reset Family Spec DMU_HF_PWAIT PFLASH Wait Cycle Register 0000068 U,SV P,SV,E System Reset...
  • Page 77 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HP_PROCO PFLASH Bank i Protection 0010004 U,SV See Family Spec See NPi1 Configuration 1 +i*100 Family (i=0-1) Spec...
  • Page 78 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_HP_PROCO PFLASH Bank i WOP 001008C U,SV See Family Spec See NWOPi3 Configuration 3 +i*100 Family (i=0-1) Spec...
  • Page 79 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_SF_CLRE HSM Clear Error Register 0020038 Application Reset Family Spec DMU_SF_ECCR HSM DF1 ECC Read Register 0020040 Application Reset Family...
  • Page 80 AURIX™ TC37x Register Overview - DMU (ascending Offset Address) (cont’d) Table 27 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMU_SP_PROCO HSM Code OTP Protection 0030014 U,SV See Family Spec See NHSMCOTP1 Configuration Family Spec DMU_SP_PROCO HSM Interface Protection 0030040...

  • Page 81: Tc37X Specific Registers

    AURIX™ TC37x 6.3.2 TC37x Specific Registers 6.3.2.1 SRI slave interface - Register Address Space Flash Status Register The Flash Status Register reflects the status of the Flash Banks after reset. Note: The DxBUSY and PxBUSY flags cannot be cleared with the “Clear Status” command or with the “Reset to Read”...
  • Page 82 AURIX™ TC37x Field Bits Type Description PxBUSY (x=0- Program Flash PFxBUSY HW-controlled status flag. Indication of busy state of PFx because of active execution of an operation; PFx busy state is also indicated during Flash startup after reset or in sleep mode; while in busy state the PFx does not allow read access.
  • Page 83 AURIX™ TC37x DMU_HF_PROTECT Flash Protection Status Register (000001C Application Reset Value: 0000 0000 PRODI PRODI PRODI PRODI PRODI PRODI PRODI PRODI SSWA SBMH SDBG Field Bits Type Description PRODISP PFLASH Protection Disabled The protection configured by UCB_PFLASH_ORIG and UCB_PFLASH_COPY was successfully disabled by supplying the correct password to “Disable Protection”.
  • Page 84 AURIX™ TC37x Field Bits Type Description PRODISSWAP 5 UCB_SWAP protection Disabled The protection configured by UCB_SWAP_ORIG and UCB_SWAP_COPY was successfully disabled by supplying the correct password to “Disable Protection”. Note: Cleared with command "Resume Protection". 7:6, Reserved 23:14, Always read as 0; should be written with 0. 31:25 PRODISPx Program Flash Protection Disable PRODISPx...
  • Page 85 AURIX™ TC37x Field Bits Type Description 7:1, Reserved for UCB 15:10, Deliver the corresponding content of UCB. 31:24 Boot Mode Lock Used by the SSW to restrict the boot mode selection. Boot flow with standard evaluation of boot headers. Restricted boot flow, never evaluating HWCFG pins and without fallback to boot loader.

  • Page 86: Revision History

    AURIX™ TC37x 6.3.4 Revision History Table 30 Revision History Reference Change to Previous Version Comment V2.0.9 No document changes - version update to remain aligned with family document. V2.0.10 No document changes - version update to remain aligned with family document.

  • Page 87: Non Volatile Memory (Nvm)

    AURIX™ TC37x Non Volatile Memory (NVM) This chapter supplements the family documentation with the device specific information for TC37x. User’s Manual 6-19 V2.0.0 NVMV2.0.6 2021-02 OPEN MARKET VERSION...

  • Page 88: Tc37X Specific Register Set

    AURIX™ TC37x 6.4.1 TC37x Specific Register Set Register Address Space Table Table 31 Register Address Space - FSI Module Base Address End Address Note F8030000 F80300FF sri slave interface Table 32 Register Address Space - PFI Module Base Address End Address Note (PFI0) 80000000...

  • Page 89: Connectivity

    AURIX™ TC37x Table 34 Register Overview - PFI (ascending Offset Address) Short Name Long Name Offset Page Address Number PFI0_ECCR ECC Read Register 000000 Family Spec PFI1_ECCR ECC Read Register 000000 Family Spec PFI0_ECCS ECC Status Register 000020 Family Spec PFI1_ECCS ECC Status Register 000020...

  • Page 90: Revision History

    AURIX™ TC37x 6.4.3 Revision History Table 35 Revision History Reference Change to Previous Version Comment V2.0.4 No document changes - version update to remain aligned with family document. V2.0.5 - PFI instances not used in this device Page 20 Register Address Space Table removed.

  • Page 91: Local Memory Unit (Lmu)

    AURIX™ TC37x Local Memory Unit (LMU) Local Memory Unit (LMU) This device doesn’t contain a LMU module. User’s Manual V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 92: Default Application Memory (Dam)

    AURIX™ TC37x Default Application Memory (DAM) Default Application Memory (DAM) This appendix covers product specific information for the DAM module used in the AURIX™ TC3XX product family. TC37x Specific IP Configuration RAM size for the TC37x is 32 KiB per instance TC37x Specific Register Set Table 36 Register Address Space - DAM...

  • Page 93: Tc37X Specific Registers

    AURIX™ TC37x Default Application Memory (DAM) Register Overview - DAM0 (ascending Offset Address) (cont’d) Table 37 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DAM0_RGNACCE DAM Region Write Enable 0005C SV,SE,P Application NWBx Register B x*10 Reset Family...

  • Page 94: System Control Unit (Scu)

    AURIX™ TC37x System Control Unit (SCU) System Control Unit (SCU) This chapter describes the System Control Unit (short SCU) Module of the TC37x. TC37x Specific IP Configuration Table 40 TC37x specific configuration of SCU Parameter Number of WDT linked to the number of CPU Name of the ssw value After SSW execution CFS value for DTSCBGOCTRL register...

  • Page 95: Tc37X Specific Register Set

    AURIX™ TC37x System Control Unit (SCU) TC37x Specific Register Set The address space for the module registers is defined in Register Address Space - SCU. Table 41 Register Address Space - SCU Module Base Address End Address Note F0036000 F00363FF SCU: Connections to FPI/BPI bus Table 42 Register Overview - SCU (ascending Offset Address)
  • Page 96 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_CCUCON1 CCU Clock Control Register 0034 U,SV SV,SE,P0 System Reset Family Spec SCU_FDR Fractional Divider Register...
  • Page 97 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_SYSCON System Control Register 007C U,SV U,SV,P0 System Reset Family Spec SCU_CCUCON6 CCU Clock Control Register 0080...
  • Page 98 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_PMCSR2 Power Management Control 00D0 U,SV SE,CE2,SV, Application and Status Register Reset Family Spec...
  • Page 99 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_TRAPCLR Trap Clear Register 012C U,SV U,SV,P0 System Reset Family Spec SCU_TRAPDIS0 Trap Disable Register 0 0130...
  • Page 100 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_PDISC Pad Disable Control 018C U,SV SV,E,P0 System Reset Register Family Spec Reserved (0020 Byte)
  • Page 101 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_FMR Flag Modification Register 0224 U,SV U,SV,P0 Application Reset Family Spec SCU_PDRR Pattern Detection Result 0228...
  • Page 102 AURIX™ TC37x System Control Unit (SCU) Register Overview - SCU (ascending Offset Address) (cont’d) Table 42 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SCU_SEICON0 Safety ENDINIT Control 02B4 U,SV U,SV,32,P1 Application Register 0 Reset Family Spec SCU_SEICON1...

  • Page 103: Tc37X Specific Registers

    AURIX™ TC37x System Control Unit (SCU) TC37x Specific Registers 9.3.1 SCU: Connections to FPI/BPI bus LCL CPU0 and CPU2 Control Register Provides control for CPU0and CPU2 Lockstep Comparator Logic blocks. SCU_LCLCON0 LCL CPU0 and CPU2 Control Register (0134 Reset Value: Table 43 LSEN0 Field...
  • Page 104 AURIX™ TC37x System Control Unit (SCU) SCU_LCLCON1 LCL CPU1 and CPU3 Control Register (0138 Reset Value: Table 44 LSEN1 Field Bits Type Description Lockstep Mode Status This bit indicates whether CPU1 is currently running in lockstep monitor mode Not in lockstep mode Running in lockstep mode LSEN1 Lockstep Enable...
  • Page 105 AURIX™ TC37x System Control Unit (SCU) SCU_LCLTEST LCL Test Register (013C System Reset Value: 0000 0000 PLCLT PLCLT PLCLT LCLT2 LCLT1 LCLT0 Field Bits Type Description LCLT0 LCL0 Lockstep Test Fault injection for LCL0. Reads as zero. No action Inject single fault in LCL0 LCLT1 LCL1 Lockstep Test Fault injection for LCL1.
  • Page 106 AURIX™ TC37x System Control Unit (SCU) Logic BIST Control 2 Register SCU_LBISTCTRL2 Logic BIST Control 2 Register (016C Reset Value: Table 45 LENGTH Field Bits Type Description 11:0 LENGTH LBIST Maximum Scan-Chain Length This field defines the number of shift-cycles for each LBIST scan-load. It will be automatically loaded with the product-specific value, stored in Flash config-sector during startup-software execution.
  • Page 107 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description OVEN1 Overlay Enable 1 (If product has CPU1) OVC is disabled on CPU1. All Overlay redirections are disabled regardless of the state of OVC1_RABRy.OVEN. OVC is enabled on CPU1. OVEN2 Overlay Enable 2 (If product has CPU2) OVC is disabled on CPU2.
  • Page 108 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description OVSTRT Overlay Start CPUs which are not selected are not affected. No action is taken if OVSTP is also set. Return 0 if read. No action For each CPU selected with CSEL, all the blocks selected with OVCx_OSEL will be activated.
  • Page 109 AURIX™ TC37x System Control Unit (SCU) Reset Status Register SCU_RSTSTAT Reset Status Register (0050 Reset Value: Table 46 LBTER LBPO PORS STBYR HSMA HSMS SWD EVR33 EVRC STM2 STM1 STM0 ESR1 ESR0 Field Bits Type Description ESR0 Reset Request Trigger Reset Status for ESR0 The last reset was not requested by this reset trigger The last reset was requested by this reset trigger ESR1...
  • Page 110 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description Reset Request Trigger Reset Status for Cerberus System Reset The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Reset Request Trigger Reset Status for Cerberus Debug Reset The last reset was not requested by this reset trigger The last reset was requested by this reset trigger Reset Request Trigger Reset Status for Cerberus Application Reset...
  • Page 111 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description LBPORST LBIST termination due to PORST This bitfield indicates if the LBIST was early terminated due to the occurrence of a Power On Reset. If the status of this bitfield is 0, the application must still check the LBTERM to check if the LBIST was terminated properly.
  • Page 112 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description ESR0 ESR0 Reset Request Trigger Reset Configuration This bit field defines which reset is generated by a reset request trigger from ESR0 reset. No reset is generated for a trigger of ESR0 A System Reset is generated for a trigger of ESR0 reset An Application Reset is generated for a trigger of ESR0 reset Reserved, do not use this combination...
  • Page 113 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description 15:14 STM2 STM2 Reset Request Trigger Reset Configuration (If Product has STM2) This bit field defines which reset is generated by a reset request trigger from STM2 compare match reset. No reset is generated for a trigger of STM2 A System Reset is generated for a trigger of STM2 reset An Application Reset is generated for a trigger of STM2 reset...
  • Page 114 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description STM2DIS STM2 Disable Reset This bit field defines if an Application Reset leads to an reset for the STM2. An Application Reset resets the STM2 An Application Reset has no effect for the STM2 Reserved Should be written with 0.
  • Page 115 AURIX™ TC37x System Control Unit (SCU) Trap Disable Register 0 SCU_TRAPDIS0 Trap Disable Register 0 (0130 Application Reset Value: FFFF FFFF CPU2S CPU2T CPU2E CPU2E CPU3xT RAP2T SR1T SR0T CPU1S CPU1T CPU1E CPU1E CPU0S CPU0T CPU0E CPU0E RAP2T SR1T SR0T RAP2T SR1T SR0T...
  • Page 116 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description CPU2TRAP2T 18 Disable Trap Request TRAP2T on CPU2 (If product has CPU2) A CPU2 trap request can be generated for this source No trap request can be generated for this source CPU2SMUT Disable Trap Request SMUT on CPU2 (If product has CPU2) A CPU2 trap request can be generated for this source...
  • Page 117 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description ASCLINFDIV ASCLIN Fast Divider Reload Value The resulting ASCLIN frequency is configured to f ASCLINF source2 ASCLINFDIV for the allowed configurations. For ASCLINFDIV = 0000 clock is shut off. f could be configured either to f (CLKSEL = 01 source2...
  • Page 118 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description 13:12 CLKSELASCLI Clock Selection for ASCLINS This bit field defines the clock source that is used for the clock generation of f ASCLINS Note: For switching between two non-zero configurations the following sequence has to be applied: First step is to switch to .
  • Page 119 AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description GETHDIV GETH Divider Reload Value The resulting GETH frequency is configured to f / GETHDIV GETH source0 for the allowed configurations. For GETHDIV = 0000 the clock is shut off. could be configured either to f (CLKSEL = 01 ) or f...

  • Page 120: Connectivity

    AURIX™ TC37x System Control Unit (SCU) Field Bits Type Description Update Request Setting this bit will request an update for CCUCON0 and CCUCON5. Only one UP bit must be set either CCUCON0 or CCUCON5. This bit always reads as zero. No action A new complete parameter set is transferred to the CCU defined by register CCUCON0 and CCUCON5.
  • Page 121 AURIX™ TC37x System Control Unit (SCU) Connections of SCU (cont’d) Table 48 Interface Signals connects Description SCU:E_IOUT(4) CAN0:TTCPT_TRIG(4) ERU IOUTn output (MSB is IOUT7 and LSB is IOUT0) SCU:E_PDOUT(0) CCU60:CTRAPD ERU PDOUTn output (MSB is PDOUT7 and LSB is PDOUT0) CCU60:T12HRH EDSADC:ITR0G EVADC:G0REQGTM...
  • Page 122 AURIX™ TC37x System Control Unit (SCU) Connections of SCU (cont’d) Table 48 Interface Signals connects Description SCU:E_REQ0(2) from P10.7:IN ERU Channel 0 input X; x=0-5, where 0 is input A and 5 is input F. SCU:E_REQ0(3) from MSC0:FCLP ERU Channel 0 input X; x=0-5, where 0 is input A and 5 is input F.

  • Page 123: Revision History

    AURIX™ TC37x System Control Unit (SCU) Connections of SCU (cont’d) Table 48 Interface Signals connects Description SCU:E_REQ5(3) from STM2:STMIR(0) ERU Channel 5 input X; x=0-5, where 0 is input A and 5 is input F. SCU:E_REQ6(0) from P20.0:IN ERU Channel 6 input X; x=0-5, where 0 is input A and 5 is input F.
  • Page 124 AURIX™ TC37x System Control Unit (SCU) Table 49 Revision History Reference Change to Previous Version Comment V2.1.21 Revision History entries up to V2.1.20 removed. Parameter values added for: Page 1 SCU_LBISTCTRL0, SCU_LBISTCTRL2. Page 27 Connectivity information updated. V2.1.22 Revision History entries up to V2.1.22 removed. Page 16 Cold PORST reset value changed from 1xx10000 to 0xx10000 in RSTSTAT register.

  • Page 125: Clocking System

    AURIX™ TC37x Clocking System Clocking System Device specific information about the clocking system is contained in the SCU chapter as both modules share a common bus interface. User’s Manual 10-1 V2.0.0 CCUV2.0.29 2021-02 OPEN MARKET VERSION...

  • Page 126: Power Management System (Pms)

    AURIX™ TC37x Power Management System (PMS) Power Management System (PMS) This chapter describes the Power Management System (PMS) Module of the TC37x. 11.1 TC37x Specific IP Configuration Table 50 TC37x specific configuration of PMS Parameter CFS value for the PMSWCR4 register 02000020 User’s Manual 11-1...

  • Page 127: Tc37X Specific Register Set

    AURIX™ TC37x Power Management System (PMS) 11.2 TC37x Specific Register Set The PMS related SCU registers are specified in the SCU section of this appendix. Table 51 Register Address Space - PMS Module Base Address End Address Note (PMS) F0240000 F0241FFF F0248000 F02481FF...
  • Page 128 AURIX™ TC37x Power Management System (PMS) Register Overview - PMS (ascending Offset Address) (cont’d) Table 52 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_PMSIEN PMS Interrupt Enable 0074 U,SV SV,SE,P See Family Spec See Register Family Spec...
  • Page 129 AURIX™ TC37x Power Management System (PMS) Register Overview - PMS (ascending Offset Address) (cont’d) Table 52 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_PMSWSTAT Standby and Wake-up 00D4 U,SV LVD Reset Status Register Family Spec PMS_PMSWSTAT Standby and Wake-up...
  • Page 130 AURIX™ TC37x Power Management System (PMS) Register Overview - PMS (ascending Offset Address) (cont’d) Table 52 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_EVRSDCTRL EVRC SD Control Register 9 012C U,SV SV,SE,P See Family Spec See Family Spec PMS_EVRSDCTRL...

  • Page 131: Tc37X Specific Registers

    AURIX™ TC37x Power Management System (PMS) Register Overview - PMS (ascending Offset Address) (cont’d) Table 52 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PMS_MONBISTS SMU_stdby BIST Status 0190 U,SV See Family Spec See Register Family Spec PMS_MONBISTC...

  • Page 132: Connectivity

    AURIX™ TC37x Power Management System (PMS) 11.4 Connectivity Table 53 Connections of PMS Interface Signals connects Description PMS:DCDCSYNCO P32.4:HWOUT(0) DC-DC synchronization output P32.2:ALT(6) P32.4:ALT(2) PMS:ESR0PORST TC37x:ESR0 ESR0 control output during PORST activation PMS:ESR0WKP from TC37x:ESR0 ESR0 pin input PMS:ESR1WKP from TC37x:ESR1 ESR1 pin input PMS:HWCFG1IN from TC37x:P14.5...
  • Page 133 AURIX™ TC37x Power Management System (PMS) Revision History (cont’d) Table 54 Reference Change to Previous Version Comment V2.2.33 – No functional changes. V2.2.34 – No functional changes. User’s Manual 11-8 V2.0.0 PMSV2.2.34 2021-02 OPEN MARKET VERSION...

  • Page 134: Power Management System For Low-End (Pmsle)

    AURIX™ TC37x Power Management System for Low-End (PMSLE) Power Management System for Low-End (PMSLE) This device doesn’t contain a PMSLE module. User’s Manual 12-1 V2.0.0 PMSLE 2021-02 OPEN MARKET VERSION...

  • Page 135: Memory Test Unit (Mtu)

    AURIX™ TC37x Memory Test Unit (MTU) Memory Test Unit (MTU) For the generic description of the Memory Test Unit (MTU) and the SRAM Support Hardware (SSH), please refer to the platform chapter. 13.1 TC37x Specific IP Configuration There is no device specific IP configuration. MTU+SSH is generic across all derivates in the platforms. Only the SSH instances vary.

  • Page 136: Tc37X Specific Register Set

    AURIX™ TC37x Memory Test Unit (MTU) 13.3 TC37x Specific Register Set Register Address Space Table Table 55 Register Address Space - MTU Module Base Address End Address Note F0060000 F006FFFF FPI slave interface Register Overview Table Table 56 Register Overview - MTU (ascending Offset Address) Short Name Long Name Offset...

  • Page 137: Tc37X Specific Registers

    AURIX™ TC37x Memory Test Unit (MTU) Register Overview - MTU (ascending Offset Address) (cont’d) Table 56 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write MTU_MCi_MCON MBIST Control Register 1004 U,SV,16 SV,SE,P,16 Application TROL Reset Family (i=0-95) Spec MTU_MCi_MSTA...
  • Page 138 AURIX™ TC37x Memory Test Unit (MTU) MTU_MEMTESTi (i=0) Memory MBIST Enable Register i (0010 +i*4) Application Reset Value: 0000 0000 RES31 RES30 RES29 RES28 RES27 RES26 RES25 RES24 RES23 RES22 RES21 RES20 RES19 RES18 RES17 RES16 CPU1_ CPU0_ CPU2_ CPU2_ CPU2_ CPU2_ CPU2_...
  • Page 139 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU1_DLMU_ CPU1 STANDBY DLMU SSH instance Enable STBY_EN SSH instance is disabled SSH instance is enabled CPU2_DMEM_ CPU2 DMEM SSH instance Enable SSH instance is disabled SSH instance is enabled CPU2_DTAG_ CPU2 DTAG SSH instance Enable SSH instance is disabled...
  • Page 140 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description DAM0_EN DAM0 SSH instance Enable SSH instance is disabled SSH instance is enabled Reserved - Res Reserved. Not used in this product. Shall be written with zero. SADMA_EN Safety DMA SSH instance Enable SSH instance is disabled SSH instance is enabled MINI_MCDS_E...
  • Page 141 AURIX™ TC37x Memory Test Unit (MTU) MTU_MEMTESTi (i=2) Memory MBIST Enable Register i (0010 +i*4) Application Reset Value: 0000 0000 GIGET GIGET RES31 RES30 RES29 RES28 RES27 RES26 RES25 RES24 RES23 RES22 RES21 RES20 H_TX_ H_RX_ RES17 RES16 ERAY_ SCR_R SCR_X ERAY_ ERAY_...
  • Page 142 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description SCR_XRAM_E SCR XRAM SSH instance Enable SSH instance is disabled SSH instance is enabled SCR_RAMINT_ SCR Internal RAM SSH instance Enable SSH instance is disabled SSH instance is enabled GIGETH_RX_E Gigabit Ethernet RX SSH instance Enable SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1...

  • Page 143: Memmap Implementation

    AURIX™ TC37x Memory Test Unit (MTU) 13.4.2 MEMMAP Implementation The Memory Mapping Enable register MEMMAP has configurable control bits to select memory-mapped test mode for each CPU memory. Cache and Scratchpad memories are physically implemented as a single RAM, but this register function assumes two separate logical RAM partitions.
  • Page 144 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU0_PTMAP 3 CPU0 PTAG Mapping Read only. Mirrors the state of CPU0_PCMAP. CPU P-cache memories may only be mapped simultaneously. Normal cache function Memory-mapped Reserved - Res Reserved. Not used in this product. CPU1_DCMAP 5 CPU1 DCache Mapping Normal cache function...
  • Page 145 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description Reserved - Res Reserved. Not used in this product. 31:29 Reserved - Res Reserved. Not used in this product. User’s Manual 13-11 V2.0.0 MTUV7.4.13 2021-02 OPEN MARKET VERSION...

  • Page 146: Memstat Implementation

    AURIX™ TC37x Memory Test Unit (MTU) 13.4.3 MEMSTAT Implementation The Memory Status Registers MEMSTATx have an implemented bit for each security relevant RAM. The Data- and Program- Cache and Scratchpad memories are physically implemented as a single RAM with a single MBIST.
  • Page 147 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU0_PTAG_ CPU0 PTAG MBIST AutoInitialize Underway This bit indicates whether an automatic data initialization has been triggered by a change of state of MEMTEST.MEMxEN or MEMxMAP but that the intialization sequence has not yet completed. MBIST not running autoinitialize MBIST running autoinitialize Reserved - Res...
  • Page 148 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU2_PMEM_ CPU2 PMEM Partial AutoInitialize of Cache Partition Underway This bit indicates whether an automatic data initialization has been triggered by a change of state of MEMTEST.MEMxEN or MEMxMAP but that the intialization sequence has not yet completed.
  • Page 149 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved. Not used in this product. 31:9 Reserved - Res Reserved. Not used in this product. 1) Please refer to separate section related to handling of the large DMEM on this device. 2) Please refer to separate section related to handling of the large DMEM on this device.

  • Page 150: Memdone Implementation

    AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description 31:18 Reserved - Res Reserved. Not used in this product. 13.4.4 MEMDONE Implementation Memory Test Done Status Register i Each bit in one of the memory test done status registers MEMDONEx reflects the status of the MSTATUS.DONE bit in the corresponding SSH.
  • Page 151 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU1_DTAG_ CPU1 DTAG Test Done Status DONE SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 CPU1_PMEM_ CPU1 PMEM Test Done Status SSH MSTATUS.DONE = 0 DONE SSH MSTATUS.DONE = 1 CPU1_PTAG_ CPU1 PTAG Test Done Status SSH MSTATUS.DONE = 0...
  • Page 152 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description RESz (z=0-1,4- Reserved 5,7,11- Reserved. Not used in this product. 20,22,24,29) CPU0_DMEM1 CPU0 DMEM1 Test Done Status SSH instance is disabled _DONE SSH instance is enabled CPU1_DMEM1 CPU1 DMEM1 Test Done Status SSH instance is disabled _DONE SSH instance is enabled...
  • Page 153 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description MCAN20_DON MCAN20 memory Test Done Status SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 1) Please refer to separate section related to handling of the large DMEM on this device. 2) Please refer to separate section related to handling of the large DMEM on this device.

  • Page 154: Memfda Implementation

    AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved. Not used in this product. SCR_XRAM_D SCR XRAM Test Done Status SSH MSTATUS.DONE = 0 SSH MSTATUS.DONE = 1 SCR_RAMINT_ SCR Internal RAM Test Done Status SSH MSTATUS.DONE = 0...
  • Page 155 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description CPU0_DTAG_ CPU0 DTAG Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 CPU0_PMEM_ CPU0 PMEM Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 CPU0_PTAG_F CPU0 PTAG Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 CPU0_DLMU_...
  • Page 156 AURIX™ TC37x Memory Test Unit (MTU) MTU_MEMFDAi (i=1) Memory Test FDA Status Register i (0060 +i*4) Application Reset Value: 0000 0000 GTM_ GTM_ GTM_ MCAN MCAN GTM_ GTM_ GTM_F DPLL1 MCS1F MCS0F 20_FD 10_FD RES29 DPLL2 DPLL1 RES24 RES22 IFO_F RES20 RES19 RES18 RES17 RES16 BC_FD AST_F...
  • Page 157 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description GTM_DPLL1A GTM DPLL1A memory Test FDA Status _FDA SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 GTM_DPLL1B GTM DPLL1BC memory Test FDA Status SSH MSTATUS.FDA = 0 C_FDA SSH MSTATUS.FDA = 1 GTM_DPLL2_ GTM DPLL2 memory Test FDA Status SSH MSTATUS.FDA = 0...
  • Page 158 AURIX™ TC37x Memory Test Unit (MTU) Field Bits Type Description ERAY_MBF0_F ERAY MBF0 memory Test FDA Status SSH MSTATUS.FDA = 0 SSH MSTATUS.FDA = 1 Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved. Not used in this product. Reserved - Res Reserved.

  • Page 159: Ssh Instances

    AURIX™ TC37x Memory Test Unit (MTU) 13.5 SSH Instances The system SRAMs do not all have the same configuration. shows the Table 57 “SSH instances” on Page 25 instance-specific configurations of the SRAM Support Hardware. The ECC values for all SRAMs are computed only out of the data information*. The base address of an SSH instance MCx can be calculated from the MC_BASE (defined in the platform chapter) as: Base Address of SSH instance x (MCx) = MC_BASE + x*0x100 Table 57...
  • Page 160 AURIX™ TC37x Memory Test Unit (MTU) SSH instances (cont’d) Table 57 (MCx) Module Error Addr Buffer ECC type ECC granularity (ETRR) Depth Factor Reserved Reserved Reserved Reserved CPU0_DMEM1 SECDED CPU1_DMEM1 SECDED 36-37 Reserved DAM0 SECDED Reserved SADMA SECDED MINI_MCDS SECDED Reserved Reserved Reserved...
  • Page 161 AURIX™ TC37x Memory Test Unit (MTU) SSH instances (cont’d) Table 57 (MCx) Module Error Addr Buffer ECC type ECC granularity (ETRR) Depth Factor Reserved ERAY_MBF0 SECDED Reserved SCR_XRAM SECDED SCR_RAMINT SECDED Reserved Reserved Reserved GIGETH_RX_RAM SECDED GIGETH_TX_RAM SECDED Reserved Reserved Reserved Reserved Reserved...

  • Page 162: Ganging For Sram Test And Initialization

    AURIX™ TC37x Memory Test Unit (MTU) 13.5.1 Ganging for SRAM test and initialization Whenever an MBIST test or SRAM initialization is started via the MTU/SSH, there is a certain jump in the current consumption, due to the parallel accesses to the SRAM cells during the test or initialization. This current jump is different for the different SRAMs in the product, and depends on the size of the SRAM, the clock frequency e.t.c.

  • Page 163: Connectivity

    AURIX™ TC37x Memory Test Unit (MTU) Table 60 GANG-2 MCx(x=) Module / SRAM CPU1_DMEM CPU2_DMEM GTM_DPLL1BC PSI5 Table 61 GANG-3 MCx(x=) Module / SRAM CPU0_PMEM CPU0_PTAG CPU1_DLMU_STBY CPU2_DLMU DAM0 GTM_MCS0FAST Table 62 GANG-4 MCx(x=) Module / SRAM CPU1_PMEM CPU1_PTAG CPU2_PMEM CPU2_PTAG SADMA GTM_MCS1FAST...

  • Page 164: Revision History

    AURIX™ TC37x Memory Test Unit (MTU) Table 64 Connections of MTU Interface Signals connects Description MTU:CPU0DCMAP cpu_pfi_pfrwb_0:tc162p CPU dcache mapped indicator per cpu _dcache_map MTU:CPU1DCMAP cpu_pfi_pfrwb_1:tc162p CPU dcache mapped indicator per cpu _dcache_map MTU:CPU2DCMAP cpu_2:tc162p_dcache_ CPU dcache mapped indicator per cpu MTU:CPU0PCMAP cpu_pfi_pfrwb_0:tc162p CPU pcache mapped indicator per cpu...
  • Page 165 AURIX™ TC37x Memory Test Unit (MTU) Table 65 Revision History Reference Change to Previous Version Comment V7.4.10 – No functional changes. V7.4.11 – No functional changes. V7.4.12 – No functional changes. V7.4.13 Page 12 Wrongly mentioned bit field in MTU_MEMSTATi (i=2) fixed. User’s Manual 13-31 V2.0.0...

  • Page 166: General Purpose I/O Ports And Peripheral I/O Lines (Ports)

    AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) General Purpose I/O Ports and Peripheral I/O Lines (Ports) This chapter supplements the family documentation with device specific information for TC37x. 14.1 TC37x Specific IP Configuration The Ports configuration (which Port modules are implemented, their width and functionality) is represented by the device specific register set shown in this chapter.
  • Page 167 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P00 (ascending Offset Address) (cont’d) Table 67 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P00_IOCR0 Port 00 Input/Output U,SV U,SV,P See page Control Register 0 P00_IOCR4...
  • Page 168 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P00 (ascending Offset Address) (cont’d) Table 67 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P00_OMCR8 Port 00 Output Modification U,SV U,SV,P Application Clear Register 8...
  • Page 169 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P01 (ascending Offset Address) (cont’d) Table 68 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P01_ESR Port 01 Emergency Stop U,SV SV,E,P Application Register...
  • Page 170 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P02 (ascending Offset Address) (cont’d) Table 69 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) P02_IOCR0 Port 02 Input/Output U,SV U,SV,P See page...
  • Page 171 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P02 (ascending Offset Address) (cont’d) Table 69 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P02_OMSR Port 02 Output Modification U,SV U,SV,P Application Set Register...
  • Page 172 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P10 (ascending Offset Address) (cont’d) Table 70 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P10_ESR Port 10 Emergency Stop U,SV SV,E,P Application Register...
  • Page 173 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 71 Register Overview - P11 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P11_OUT Port 11 Output Register U,SV U,SV,P Application Reset P11_OMR...
  • Page 174 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P11 (ascending Offset Address) (cont’d) Table 71 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P11_OMSR8 Port 11 Output Modification U,SV U,SV,P Application Set Register 8...
  • Page 175 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P12 (ascending Offset Address) (cont’d) Table 72 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-5) P12_PDR0 Port 12 Pad Driver Mode U,SV SV,E,P See page...
  • Page 176 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P13 (ascending Offset Address) (cont’d) Table 73 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P13_ID Port 13 Identification U,SV Application Register Reset Reserved (004...
  • Page 177 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P13 (ascending Offset Address) (cont’d) Table 73 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P13_ACCEN1 Port 13 Access Enable U,SV SV,SE Application Register 1...
  • Page 178 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P14 (ascending Offset Address) (cont’d) Table 74 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write Reserved (004 Byte) (x=0-1) P14_OMSR0 Port 14 Output Modification U,SV U,SV,P Application...
  • Page 179 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P15 (ascending Offset Address) (cont’d) Table 75 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P15_IOCR0 Port 15 Input/Output U,SV U,SV,P See page Control Register 0 P15_IOCR4...
  • Page 180 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P15 (ascending Offset Address) (cont’d) Table 75 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P15_OMCR Port 15 Output Modification U,SV U,SV,P Application Clear Register...
  • Page 181 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P20 (ascending Offset Address) (cont’d) Table 76 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P20_ESR Port 20 Emergency Stop U,SV SV,E,P Application Register...
  • Page 182 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 77 Register Overview - P21 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P21_OUT Port 21 Output Register U,SV U,SV,P Application Reset P21_OMR...
  • Page 183 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P21 (ascending Offset Address) (cont’d) Table 77 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P21_OMCR Port 21 Output Modification U,SV U,SV,P Application Clear Register...
  • Page 184 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P22 (ascending Offset Address) (cont’d) Table 78 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P22_ESR Port 22 Emergency Stop U,SV SV,E,P Application Register...
  • Page 185 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 79 Register Overview - P23 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P23_OUT Port 23 Output Register U,SV U,SV,P Application Reset P23_OMR...
  • Page 186 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P23 (ascending Offset Address) (cont’d) Table 79 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P23_OMCR Port 23 Output Modification U,SV U,SV,P Application Clear Register...
  • Page 187 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P32 (ascending Offset Address) (cont’d) Table 80 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P32_PCSR Port 32 Pin Controller Select U,SV SV,SE Application...
  • Page 188 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P33 (ascending Offset Address) (cont’d) Table 81 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P33_IOCR8 Port 33 Input/Output U,SV U,SV,P See page Control Register 8 P33_IOCR12...
  • Page 189 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P33 (ascending Offset Address) (cont’d) Table 81 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P33_OMSR Port 33 Output Modification U,SV U,SV,P Application Set Register...
  • Page 190 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P34 (ascending Offset Address) (cont’d) Table 82 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P34_PDISC Port 34 Pin Function U,SV SV,E,P See page Decision Control Register...
  • Page 191 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P40 (ascending Offset Address) (cont’d) Table 83 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P40_IOCR4 Port 40 Input/Output U,SV U,SV,P See page Control Register 4 P40_IOCR8...
  • Page 192 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Register Overview - P40 (ascending Offset Address) (cont’d) Table 83 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write P40_OMCR12 Port 40 Output Modification U,SV U,SV,P Application Clear Register 12...
  • Page 193 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) 14.3 Pn Registers 14.3.1 SPB bus slave interface Port 00 Output Register The port output register determines the value of a GPIO pin when it is selected by Pn_IOCRx as output. Writing a 0 to a Pn_OUT.Px (x = 0-15) bit position delivers a low level at the corresponding output pin.
  • Page 194 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 84 Access Mode Restrictions sorted by descending priority Applies to P00_OUT Applies to P11_OUT Applies to P20_OUT Applies to P33_OUT Applies to P40_OUT Mode Name Access Mode Description Master enabled in rwh Px (x=0-15) write access for enabled masters...
  • Page 195 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 85 Access Mode Restrictions sorted by descending priority Applies to P01_OUT Applies to P21_OUT Applies to P23_OUT Applies to P32_OUT Applies to P34_OUT Mode Name Access Mode Description Master enabled in rwh Px (x=0-7) write access for enabled masters...
  • Page 196 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 86 Access Mode Restrictions sorted by descending priority Applies to P02_OUT Applies to P10_OUT Applies to P14_OUT Applies to P15_OUT Applies to P22_OUT Mode Name Access Mode Description Master enabled in rwh Px (x=0-11) write access for enabled masters...
  • Page 197 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 00 Output Modification Register The port output modification register contains control bits that make it possible to individually set, clear or toggle the logic state of a single port line by manipulating the output register. P00_OMR Port 00 Output Modification Register (004...
  • Page 198 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Note: Register Pn_OMR is virtual and does not contain any flip-flop. A read action delivers the value of 0. One 8 or 16-bits write behaves as a 32-bit write padded with zeros. Table 89 Function of the Bits PCLx and PSx PCLx...
  • Page 199 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 31, 30, 29, 28, 27, 26, 25, 24 Table 90 Access Mode Restrictions sorted by descending priority Applies to P01_OMR...
  • Page 200 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCLx (x=0-11) x+16 Clear Bit x Setting this bit will clear or toggle the corresponding bit in the port output register Pn_OUT. Read as 0. The function of this bit is shown in Table No operation Clears or toggles Pn_OUT.Px.
  • Page 201 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description x+16 PCLx (x=0-3) Clear Bit x Setting this bit will clear or toggle the corresponding bit in the port output register Pn_OUT. Read as 0. The function of this bit is shown in Table No operation Clears or toggles Pn_OUT.Px.
  • Page 202 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_ID Port 00 Identification Register (008 Application Reset Value: 00C8 C0XX P01_ID Port 01 Identification Register (008 Application Reset Value: 00C8 C0XX P02_ID Port 02 Identification Register (008 Application Reset Value: 00C8 C0XX P10_ID Port 10 Identification Register (008...
  • Page 203 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_ID Port 21 Identification Register (008 Application Reset Value: 00C8 C0XX P22_ID Port 22 Identification Register (008 Application Reset Value: 00C8 C0XX P23_ID Port 23 Identification Register (008 Application Reset Value: 00C8 C0XX P32_ID Port 32 Identification Register (008...
  • Page 204 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) The reset values of 1010 1010 and 0000 0000 for Pn_IOCRx registers represents input pull-up and no input pull device (tri-state mode) being activated, respectively. The switching of the intended mode of the device is controlled by HWCFG6.When a cold reset is activated and HWCFG6=1, the port pins except P33.8, P40 and P41 are set to input pull-up mode, P33.8, P40 and P41 are in tri-state mode as long as PORST is activated.If HWCFG6=0, the pins have the default state of tri-state mode.
  • Page 205 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 26:24, Reserved 18:16, 10:8, Read as 0; should be written with 0. Table 93 Access Mode Restrictions sorted by descending priority Applies to P00_IOCR0 Applies to P01_IOCR0 Applies to P02_IOCR0...
  • Page 206 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 95 PCx Coding PCx[4:0] Characteristics Selected Pull-up / Pull-down / Selected Output Function 0XX00 Input – No input pull device connected, tri-state mode 0XX01 Input pull-down device connected 0XX10 Input pull-up device connected 0XX11...
  • Page 207 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_IOCR0 Port 21 Input/Output Control Register 0 (010 Reset Value: Table 97 P22_IOCR0 Port 22 Input/Output Control Register 0 (010 Reset Value: Table 97 P23_IOCR0 Port 23 Input/Output Control Register 0 (010 Reset Value: Table 97...
  • Page 208 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 97 Reset Values variant 1 Applies to P21_IOCR0 Applies to P22_IOCR0 Applies to P23_IOCR0 Applies to P32_IOCR0 Applies to P33_IOCR0 Applies to P34_IOCR0 Reset Type Reset Value Note Application Reset 0000 0000 HWCFG6 is 0 (tri-state mode)
  • Page 209 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_IOCR4 Port 00 Input/Output Control Register 4 (014 Reset Value: Table 100 P01_IOCR4 Port 01 Input/Output Control Register 4 (014 Reset Value: Table 100 P02_IOCR4 Port 02 Input/Output Control Register 4 (014 Reset Value: Table 100...
  • Page 210 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 99 Access Mode Restrictions sorted by descending priority Applies to P00_IOCR4 Applies to P01_IOCR4 Applies to P02_IOCR4 Applies to P10_IOCR4 Applies to P11_IOCR4 Applies to P14_IOCR4 Applies to P15_IOCR4 Applies to P20_IOCR4...
  • Page 211 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P23_IOCR4 Port 23 Input/Output Control Register 4 (014 Reset Value: Table 102 P32_IOCR4 Port 32 Input/Output Control Register 4 (014 Reset Value: Table 102 P33_IOCR4 Port 33 Input/Output Control Register 4 (014 Reset Value: Table 102...
  • Page 212 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 102 Reset Values variant 1 Applies to P23_IOCR4 Applies to P32_IOCR4 Applies to P33_IOCR4 Applies to P34_IOCR4 Reset Type Reset Value Note Application Reset 0000 0000 HWCFG6 is 0 (tri-state mode) Application Reset 1010 1010 HWCFG6 is 1 (input pull-up mode)
  • Page 213 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 8*x-57:8*x- PCx (x=8-11) Port Control for Port 00 Pin x This bit field defines the Port n line x functionality according to Table 26:24, Reserved 18:16, 10:8, Read as 0;...
  • Page 214 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 107 Reset Values of P40_IOCR8 Reset Type Reset Value Note Application Reset 0000 0000 HWCFG6 is 0 (tri-state mode) Application Reset 0000 0000 HWCFG6 is 1 (input pull-up mode) Port 00 Input/Output Control Register 12 Register Pn_IOCR12 controls the Pn.[15:12] port lines P00_IOCR12...
  • Page 215 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 109 Reset Values variant 1 Applies to P00_IOCR12 Applies to P11_IOCR12 Applies to P20_IOCR12 Applies to P33_IOCR12 Reset Type Reset Value Note Application Reset 0000 0000 HWCFG6 is 0 (tri-state mode) Application Reset 1010 1010 HWCFG6 is 1 (input pull-up mode)
  • Page 216 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P01_IN Port 01 Input Register (024 Application Reset Value: 0000 00XX P21_IN Port 21 Input Register (024 Application Reset Value: 0000 00XX P23_IN Port 23 Input Register (024 Application Reset Value: 0000 00XX P32_IN Port 32 Input Register (024...
  • Page 217 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Px (x=0-11) Input Bit x This bit indicates the level at the input pin Pn.x. The input level of Pn.x is 0. The input level of Pn.x is 1. 15, 14, 13, Reserved Read as 0;...
  • Page 218 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 00 Pad Driver Mode Register 0 P00_PDR0 Port 00 Pad Driver Mode Register 0 (040 Reset Value: Table 112 P01_PDR0 Port 01 Pad Driver Mode Register 0 (040 Reset Value: Table 112 P02_PDR0...
  • Page 219 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 111 Access Mode Restrictions sorted by descending priority Applies to P00_PDR0 Applies to P01_PDR0 Applies to P02_PDR0 Applies to P10_PDR0 Applies to P11_PDR0 Applies to P14_PDR0 Applies to P15_PDR0 Applies to P20_PDR0...
  • Page 220 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 114 Pad Driver Mode Selection for Fast Pads PDx.1 PDx.0 Speed Grade Driver Setting Strong driver, sharp edge (“ss”) Strong driver, medium edge (“sm”) Medium driver (“m”) TC39x A-Step: Medium driver (“m”) Else: Reserved when operating as output.

  • Page 221: Type Description

    AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) The boot software configures the reset value of Pn_PDR0 and Pn_PDR1 registers from 0000 0000 to 2222 2222 except for analog ports and if the package doesn’t make any of the related pins available. The resulting value depends on the implemented port width.
  • Page 222 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 118 Reset Values variant 1 Applies to P23_PDR0 Applies to P32_PDR0 Applies to P33_PDR0 Applies to P34_PDR0 Reset Type Reset Value Note After SSW execution 2222 2222 Initial value in largest package After SSW execution ––––...
  • Page 223 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 120 Access Mode Restrictions sorted by descending priority Applies to P12_PDR0 Applies to P13_PDR0 Mode Name Access Mode Description Master enabled in PDx (x=0-3), PLx (x=0-3) write access for enabled masters ACCEN and Supervisor Mode and ENDINIT...
  • Page 224 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 122 Access Mode Restrictions sorted by descending priority Applies to P00_PDR1 Applies to P11_PDR1 Applies to P20_PDR1 Applies to P33_PDR1 Applies to P40_PDR1 Mode Name Access Mode Description Master enabled in PDx (x=8-15), PLx (x=8-15) write access for enabled masters...
  • Page 225 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 4*x-31:4*x- PDx (x=8-11) Pad Driver Mode for Pin x PLx (x=8-11) 4*x-29:4*x- Pad Level Selection for Pin x 31:28, Reserved 27:24, Read as 0; should be written with 0. 23:20, 19:16 Table 125 Access Mode Restrictions sorted by descending priority Applies to...
  • Page 226 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 00 Emergency Stop Register P00_ESR Port 00 Emergency Stop Register (050 Application Reset Value: 0000 0000 P11_ESR Port 11 Emergency Stop Register (050 Application Reset Value: 0000 0000 P20_ESR Port 20 Emergency Stop Register (050...
  • Page 227 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) • Emergency stop function enabled (ENx = 1): The mapped output function is disconnected and the safe state is entered by switching to input function with internal pull-up connected or tri-state, depending on the configured reset value of the corresponding Pn_IOCR register through PMSWCR5.TRISTREQ or setting of HWCFG[6].(the content of the corresponding PCx bit fields in register Pn_IOCR will not be considered).
  • Page 228 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description ENx (x=0-7) Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines. If the emergency stop condition is met and enabled, the output selection is automatically switched from alternate output function to GPIO input function.
  • Page 229 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description ENx (x=0-11) Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines. If the emergency stop condition is met and enabled, the output selection is automatically switched from alternate output function to GPIO input function.
  • Page 230 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description ENx (x=0-3) Emergency Stop Enable for Pin x This bit enables the emergency stop function for all GPIO lines. If the emergency stop condition is met and enabled, the output selection is automatically switched from alternate output function to GPIO input function.
  • Page 231 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 8, 2, 31:16 Table 131 Access Mode Restrictions of P21_ESR sorted by descending priority Mode Name...
  • Page 232 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P40_ESR Port 40 Emergency Stop Register (050 Application Reset Value: 0000 0000 Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 8, 7, 6, 5, 4, 3, 2, 1, 0, 31:16...
  • Page 233 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_PDISC Port 00 Pin Function Decision Control Register (060 Reset Value: Table 135 P11_PDISC Port 11 Pin Function Decision Control Register (060 Reset Value: Table 135 P20_PDISC Port 20 Pin Function Decision Control Register (060 Reset Value: Table 135 P33_PDISC...
  • Page 234 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 135 Reset Values variant 1 Applies to P00_PDISC Applies to P11_PDISC Applies to P20_PDISC Applies to P33_PDISC Reset Type Reset Value Note After SSW execution 0000 0000 Initial value in largest package After SSW execution 0000 ––––...
  • Page 235 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 137 Access Mode Restrictions sorted by descending priority Applies to P01_PDISC Applies to P21_PDISC Applies to P23_PDISC Applies to P32_PDISC Applies to P34_PDISC Mode Name Access Mode Description Master enabled in PDISx (x=0-7) write access for enabled masters...
  • Page 236 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PDISx (x=0- Pin Function Decision Control for Pin x This bit selects the function of the port pad. Digital functionality of pad Pn.x is enabled. Digital functionality (including pull resistors) of pad Pn.x is disabled.
  • Page 237 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P12_PDISC Port 12 Pin Function Decision Control Register (060 Reset Value: Table 142 P13_PDISC Port 13 Pin Function Decision Control Register (060 Reset Value: Table 142 PDIS3 PDIS2 PDIS1 PDIS0 Field Bits Type...
  • Page 238 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) • In Ports shared with the standby controller (SCR) it selects if the SCR or the Tricore system control data and control functions of these port lines. • In Ports with analog inputs to the EVADC it enables control of pull by the EVADC for the Pull Down Diagnostics (PDD) / Multiplexer Diagnostics (MD) feature.
  • Page 239 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P01_PCSR Port 01 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P21_PCSR Port 21 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P23_PCSR Port 23 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P32_PCSR...
  • Page 240 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P02_PCSR Port 02 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P10_PCSR Port 10 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P14_PCSR Port 14 Pin Controller Select Register (064 Application Reset Value: 0000 0000 P15_PCSR...
  • Page 241 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P11_PCSR Port 11 Pin Controller Select Register (064 Application Reset Value: 0000 0000 SEL6 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description SELx (x=0-4,6) x Output Select for Pin x This bit enables or disables alternate/fast Ethernet output.
  • Page 242 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15, 14, 13, Reserved 12, 11, 10, 9, Read as 0; should be written with 0. 8, 7, 6, 5, 4, 30:16, Table 147 Access Mode Restrictions sorted by descending priority Applies to P12_PCSR Applies to...
  • Page 243 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P33_PCSR Port 33 Pin Controller Select Register (064 Application Reset Value: 0000 0100 SEL15 SEL14 SEL13 SEL12 SEL11 SEL10 SEL9 SEL8 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type...
  • Page 244 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P34_PCSR Port 34 Pin Controller Select Register (064 Application Reset Value: 0000 0000 SEL1 Field Bits Type Description SELx (x=1) Output Select for Pin x This bit enables or disables SCR control. Tricore selected for data and control of pin x and not SCR.
  • Page 245 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P40_PCSR Port 40 Pin Controller Select Register (064 Application Reset Value: 0000 0000 R13 SEL12 SEL11 SEL10 SEL5 SEL3 SEL2 SEL1 Field Bits Type Description SELx (x=1- Output Select for Pin x This bit enables or disables EVADC control of the pulls for Pull Down 3,5,10-12) Diagnostics (PDD) / Multiplexer Diagnostics (MD) feature.
  • Page 246 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMSR0 Port 00 Output Modification Set Register 0 (070 Application Reset Value: 0000 0000 P01_OMSR0 Port 01 Output Modification Set Register 0 (070 Application Reset Value: 0000 0000 P02_OMSR0 Port 02 Output Modification Set Register 0 (070 Application Reset Value: 0000 0000...

  • Page 247: Type Description

    AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 152 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR0 Applies to P01_OMSR0 Applies to P02_OMSR0 Applies to P10_OMSR0 Applies to P11_OMSR0 Applies to P12_OMSR0 Applies to P13_OMSR0 Applies to P14_OMSR0...
  • Page 248 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 31:4 Reserved Read as 0; should be written with 0. Table 153 Access Mode Restrictions sorted by descending priority Applies to P21_OMSR0 Applies to P22_OMSR0 Applies to P23_OMSR0 Applies to...
  • Page 249 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMSR4 Port 00 Output Modification Set Register 4 (074 Application Reset Value: 0000 0000 P01_OMSR4 Port 01 Output Modification Set Register 4 (074 Application Reset Value: 0000 0000 P02_OMSR4 Port 02 Output Modification Set Register 4 (074 Application Reset Value: 0000 0000...
  • Page 250 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 154 Access Mode Restrictions sorted by descending priority Applies to P00_OMSR4 Applies to P01_OMSR4 Applies to P02_OMSR4 Applies to P10_OMSR4 Applies to P11_OMSR4 Applies to P14_OMSR4 Applies to P15_OMSR4 Applies to P20_OMSR4...
  • Page 251 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 155 Access Mode Restrictions sorted by descending priority Applies to P23_OMSR4 Applies to P32_OMSR4 Applies to P33_OMSR4 Applies to P34_OMSR4 Applies to P40_OMSR4 Mode Name Access Mode Description Master enabled in PSx (x=4-7) write access for enabled masters...
  • Page 252 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=8-11) Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 7:0, Reserved 31:12...
  • Page 253 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=12-15) x Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 11:0, Reserved...
  • Page 254 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMCR0 Port 00 Output Modification Clear Register 0 (080 Application Reset Value: 0000 0000 P01_OMCR0 Port 01 Output Modification Clear Register 0 (080 Application Reset Value: 0000 0000 P02_OMCR0 Port 02 Output Modification Clear Register 0 (080 Application Reset Value: 0000 0000...
  • Page 255 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 158 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR0 Applies to P01_OMCR0 Applies to P02_OMCR0 Applies to P10_OMCR0 Applies to P11_OMCR0 Applies to P12_OMCR0 Applies to P13_OMCR0 Applies to P14_OMCR0...
  • Page 256 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 15:0, Reserved 31:20 Read as 0; should be written with 0. Table 159 Access Mode Restrictions sorted by descending priority Applies to P21_OMCR0 Applies to P22_OMCR0 Applies to P23_OMCR0...
  • Page 257 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_OMCR4 Port 00 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000 P01_OMCR4 Port 01 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000 P02_OMCR4 Port 02 Output Modification Clear Register 4 (084 Application Reset Value: 0000 0000...
  • Page 258 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 160 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR4 Applies to P01_OMCR4 Applies to P02_OMCR4 Applies to P10_OMCR4 Applies to P11_OMCR4 Applies to P14_OMCR4 Applies to P15_OMCR4 Applies to P20_OMCR4...
  • Page 259 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 161 Access Mode Restrictions sorted by descending priority Applies to P23_OMCR4 Applies to P32_OMCR4 Applies to P33_OMCR4 Applies to P34_OMCR4 Applies to P40_OMCR4 Mode Name Access Mode Description Master enabled in PCLx (x=4-7) write access for enabled masters...
  • Page 260 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PCLx (x=8-11) x+16 Clear Bit x Setting this bit will clear the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Clears Pn_OUT.Px 23:0, Reserved...
  • Page 261 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description x+16 PCLx (x=12- Clear Bit x Setting this bit will clear the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Clears Pn_OUT.Px 27:0 Reserved...
  • Page 262 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=0-15) Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 31:16 Reserved Read as 0;...
  • Page 263 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=0-7) Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 15, 14, 13, Reserved 12, 11, 10, 9,...
  • Page 264 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description PSx (x=0-11) Set Bit x Setting this bit will set the corresponding bit in the port output register Pn_OUT. Read as 0. No operation Sets Pn_OUT.Px 15, 14, 13, Reserved Read as 0;...
  • Page 265 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 167 Access Mode Restrictions sorted by descending priority Applies to P12_OMSR Applies to P13_OMSR Mode Name Access Mode Description Master enabled in PSx (x=0-3) write access for enabled masters ACCEN Otherwise (default) r0 PSx (x=0-3)
  • Page 266 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 168 Access Mode Restrictions sorted by descending priority Applies to P00_OMCR Applies to P11_OMCR Applies to P20_OMCR Applies to P33_OMCR Applies to P40_OMCR Mode Name Access Mode Description Master enabled in PCLx (x=0-15) write access for enabled masters...
  • Page 267 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 169 Access Mode Restrictions sorted by descending priority Applies to P01_OMCR Applies to P21_OMCR Applies to P23_OMCR Applies to P32_OMCR Applies to P34_OMCR Mode Name Access Mode Description Master enabled in PCLx (x=0-7) write access for enabled masters...
  • Page 268 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 170 Access Mode Restrictions sorted by descending priority Applies to P02_OMCR Applies to P10_OMCR Applies to P14_OMCR Applies to P15_OMCR Applies to P22_OMCR Mode Name Access Mode Description Master enabled in PCLx (x=0-11) write access for enabled masters...
  • Page 269 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Port 13 LVDS Pad Control Register x The LVDS Pad Control Register controls the RX or TX functions of the LVDS pads. For usage of RX pad, bit field [7:0] are applicable.
  • Page 270 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description 11:10 VDIFFADJ LVDS Output Amplitude Tuning With these two configuration bits the LVDS output current/amplitude can be adjusted. The voltage swing depending on VDIFFADJ setting is documented in the Data Sheet, see parameter V VOSDYN Tune Bit of VOS Control Loop Static/Dynamic...
  • Page 271 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 173 Reset Values Applies to P13_LPCRx (x=0-1) Applies to P22_LPCRx (x=0-1) Reset Type Reset Value Note After SSW execution 0000 5480 Initial value of RX depends on trimming P14_LPCRx (x=5) Port 14 LVDS Pad Control Register x (0A0...
  • Page 272 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description LVDSM LVDS-M Mode Selects reduced frequency mode “LVDS-M” of the receiver. This mode reduces the static current of the RX pad. The max data rate is reduced to 160 Mbps (80 MHz).
  • Page 273 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P21_LPCRx (x=1) Port 21 LVDS Pad Control Register x (0A0 +x*4) Reset Value: Table 177 LVDS REN_C LRXTERM TERM RX_EN Field Bits Type Description REN_CTRL LVDS RX_EN controller The LVDS RX_EN control function can be selected from the Port (default) or HSCT module (where this is connected).
  • Page 274 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description Reserved Read as 0; should be written with 0 11:10, 31:16 Table 176 Access Mode Restrictions of P21_LPCRx (x=1) sorted by descending priority Mode Name Access Mode Description Master enabled in...
  • Page 275 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Field Bits Type Description TEN_CTRL LVDS TX_EN controller The LVDS TX_EN control function can be selected from the Port (default) or HSCT module (where this is connected). Port controlled HSCT controlled TX_EN Enable Transmit LVDS...
  • Page 276 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 178 Access Mode Restrictions of P21_LPCRx (x=2) sorted by descending priority Mode Name Access Mode Description Master enabled in PS, TEN_CTRL, TX_EN, TX_PD, write access for enabled masters ACCEN and TX_PWDPD, VDIFFADJ, Supervisor Mode...
  • Page 277 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_ACCEN1 Port 00 Access Enable Register 1 (0F8 Application Reset Value: 0000 0000 P01_ACCEN1 Port 01 Access Enable Register 1 (0F8 Application Reset Value: 0000 0000 P02_ACCEN1 Port 02 Access Enable Register 1 (0F8 Application Reset Value: 0000 0000 P10_ACCEN1...
  • Page 278 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 180 Access Mode Restrictions sorted by descending priority Applies to P00_ACCEN1 Applies to P01_ACCEN1 Applies to P02_ACCEN1 Applies to P10_ACCEN1 Applies to P11_ACCEN1 Applies to P12_ACCEN1 Applies to P13_ACCEN1 Applies to P14_ACCEN1...
  • Page 279 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 181 Access Mode Restrictions sorted by descending priority Applies to P21_ACCEN1 Applies to P22_ACCEN1 Applies to P23_ACCEN1 Applies to P32_ACCEN1 Applies to P33_ACCEN1 Applies to P34_ACCEN1 Applies to P40_ACCEN1 Mode Name Access Mode...
  • Page 280 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) P00_ACCEN0 Port 00 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P01_ACCEN0 Port 01 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P02_ACCEN0 Port 02 Access Enable Register 0 (0FC Application Reset Value: FFFF FFFF P10_ACCEN0...
  • Page 281 AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 182 Access Mode Restrictions sorted by descending priority Applies to P00_ACCEN0 Applies to P01_ACCEN0 Applies to P02_ACCEN0 Applies to P10_ACCEN0 Applies to P11_ACCEN0 Applies to P12_ACCEN0 Applies to P13_ACCEN0 Applies to P14_ACCEN0...

  • Page 282: Connectivity

    AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) Table 183 Access Mode Restrictions sorted by descending priority Applies to P21_ACCEN0 Applies to P22_ACCEN0 Applies to P23_ACCEN0 Applies to P32_ACCEN0 Applies to P33_ACCEN0 Applies to P34_ACCEN0 Applies to P40_ACCEN0 Mode Name Access Mode...

  • Page 283: Revision History

    AURIX™ TC37x General Purpose I/O Ports and Peripheral I/O Lines (Ports) 14.5 Revision History Table 184 Revision History V1.8.19 to the latest revision Reference Changes to Previous Version Comment V1.8.20 Page 118 Revision History entries up to V1.8.19 removed. Page 38 Removed confusing phrase “, only input selection apply.”...

  • Page 284: Safety Management Unit (Smu)

    AURIX™ TC37x Safety Management Unit (SMU) Safety Management Unit (SMU) This chapter describes the Safety Management Unit (short SMU) module of the TC37x. 15.1 TC37x Specific IP Configuration See features in family spec. User’s Manual 15-1 V2.0.0 SMUV4.0.23 2021-02 OPEN MARKET VERSION...

  • Page 285: Tc37X Specific Register Set

    AURIX™ TC37x Safety Management Unit (SMU) 15.2 TC37x Specific Register Set SMU_core Specific Register Set Register Address Space Table Table 185 Register Address Space - SMU Module Base Address End Address Note F0036800 F0036FFF FPI slave interface Register Overview Table Table 186 Register Overview - SMU (ascending Offset Address) Short Name Long Name...
  • Page 286 AURIX™ TC37x Safety Management Unit (SMU) Table 186 Register Overview - SMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SMU_PCTL Port Control U,SV SV,P,SE,32 PowerOn Reset Family Spec SMU_AFCNT Alarm and Fault Counter U,SV PowerOn Reset Family...

  • Page 287: Tc37X Specific Registers

    AURIX™ TC37x Safety Management Unit (SMU) Table 186 Register Overview - SMU (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SMU_RMEF Register Monitor Error Flags 304 U,SV SV,P,SE,32 Application Reset Family Spec SMU_RMSTS Register Monitor Self Test...

  • Page 288: Tc37X Specific Registers

    AURIX™ TC37x Safety Management Unit (SMU) 15.3.1 TC37x Specific Registers 15.3.1.1 FPI slave interface Alarm Configuration Register SMU_AGiCFj (i=0-1;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF24 CF23 CF22 CF14 CF13 CF12 CF11 CF10 Field Bits Type Description CFz (z=0-2,4- Configuration flag x (x=0-2) for alarm z belonging to alarm group i.
  • Page 289 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description CFz (z=1,4- Configuration flag x (x=0-2) for alarm z belonging to alarm group i. 14,22-24) The configuration flags 0, 1 and 2 must be used together to define the behavior of the SMU_core when a fault state is reported by the alarm n belonging to this group.
  • Page 290 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiCFj (i=6;j=0-2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF25 CF24 CF23 CF21 CF20 CF19 CF18 CF17 CF16 CF15 CF14 CF13 CF12 CF11 CF10 Field Bits Type Description CFz (z=0-2,4- Configuration flag x (x=0-2) for alarm z belonging to alarm group i. The configuration flags 0, 1 and 2 must be used together to define the 8,10-21,23- behavior of the SMU_core when a fault state is reported by the alarm n...
  • Page 291 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiCFj (i=8;j=0,2) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0001 FC00 SMU_AGiCFj (i=8;j=1) Alarm Configuration Register (100 +i*12+j*4) Application Reset Value: 0000 0000 CF31 CF30 CF29 CF28 CF27 CF26 CF25 CF23 CF22 CF21 CF20 CF19 CF18 CF17 CF16 CF12 CF11 CF10 Field Bits...
  • Page 292 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, 22, 21, 20, 19, 18, 14, 13, 12, 11, 10, 9, 8, 7, 6, 4, 2 SMU_AGiCFj (i=10;j=0) Alarm Configuration Register...
  • Page 293 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description CFz (z=0-5,8- Configuration flag x (x=0-2) for alarm z belonging to alarm group i. 10,12-13) The configuration flags 0, 1 and 2 must be used together to define the behavior of the SMU_core when a fault state is reported by the alarm n belonging to this group.
  • Page 294 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiFSP (i=2) SMU_core FSP Configuration Register (190 +i*4) Application Reset Value: 0000 0000 FE24 FE23 FE22 FE14 FE13 FE12 FE11 FE10 Field Bits Type Description FEz (z=1,4- Fault signaling configuration flag for alarm z belonging to alarm 14,22-24) group i.
  • Page 295 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiFSP (i=6) SMU_core FSP Configuration Register (190 +i*4) Application Reset Value: 0000 0000 FE25 FE24 FE23 FE21 FE20 FE19 FE18 FE17 FE16 FE15 FE14 FE13 FE12 FE11 FE10 Field Bits Type Description FEz (z=0-2,4- Fault signaling configuration flag for alarm z belonging to alarm 8,10-21,23- group i.
  • Page 296 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiFSP (i=8) SMU_core FSP Configuration Register (190 +i*4) Application Reset Value: 0000 0000 FE31 FE30 FE29 FE28 FE27 FE26 FE25 FE23 FE22 FE21 FE20 FE19 FE18 FE17 FE16 FE12 FE11 FE10 Field Bits Type Description FEz (z=0- Fault signaling configuration flag for alarm z belonging to alarm...
  • Page 297 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGiFSP (i=10) SMU_core FSP Configuration Register (190 +i*4) Application Reset Value: 0003 0000 FE22 FE21 FE20 FE18 FE17 FE16 FE15 FE14 FE13 FE12 FE11 FE10 Field Bits Type Description FEz (z=0- Fault signaling configuration flag for alarm z belonging to alarm 18,20-22) group i.
  • Page 298 AURIX™ TC37x Safety Management Unit (SMU) Alarm Status Register Refer to Alarm Status Registers for the conditions to set and reset the status flag by software. SMU_AGi (i=0-1) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF24 SF23 SF22 SF14 SF13...
  • Page 299 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGi (i=3-5) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14,...
  • Page 300 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGi (i=7) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF31 SF30 SF29 SF28 SF27 SF26 SF25 SF24 SF23 SF22 SF20 SF17 SF16 SF15 SF14 SF13 SF12 Field Bits Type Description SFz (z=0-2,12- Status flag for alarm z belonging to alarm group i.
  • Page 301 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGi (i=9) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF17 SF16 SF15 Field Bits Type Description SFz (z=0- Status flag for alarm z belonging to alarm group i. Status flag z does not report a fault condition 1,3,5,15-17) Status flag z reports a fault condition 31, 30, 29,...
  • Page 302 AURIX™ TC37x Safety Management Unit (SMU) SMU_AGi (i=11) Alarm Status Register (1C0 +i*4) Application Reset Value: 0000 0000 SF13 SF12 SF10 Field Bits Type Description SFz (z=0-5,8- Status flag for alarm z belonging to alarm group i. Status flag z does not report a fault condition 10,12-13) Status flag z reports a fault condition 31, 30, 29,...
  • Page 303 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 21, 20, 19, 18, 17, 16, 15, 3 SMU_ADi (i=2) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF24 DF23 DF22...
  • Page 304 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description 31, 30, 29, Reserved 28, 27, 26, Read as 0; should be written with 0. 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, SMU_ADi (i=6)
  • Page 305 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description DFz (z=0-2,12- Diagnosis flag for alarm z belonging to alarm group i. 17,20,22-31) The diagnosis registers make a snapshot of the alarm group status registers when either the executed alarm action is a reset or a state machine transition to FAULT state takes place.
  • Page 306 AURIX™ TC37x Safety Management Unit (SMU) Field Bits Type Description DFz (z=0- Diagnosis flag for alarm z belonging to alarm group i. 1,3,5,15-17) The diagnosis registers make a snapshot of the alarm group status registers when either the executed alarm action is a reset or a state machine transition to FAULT state takes place.

  • Page 307: Tc37X Specific Alarm Mapping

    AURIX™ TC37x Safety Management Unit (SMU) SMU_ADi (i=11) Alarm Debug Register (200 +i*4) PowerOn Reset Value: 0000 0000 DF13 DF12 DF10 Field Bits Type Description DFz (z=0-5,8- Diagnosis flag for alarm z belonging to alarm group i. The diagnosis registers make a snapshot of the alarm group status 10,12-13) registers when either the executed alarm action is a reset or a state machine transition to FAULT state takes place.
  • Page 308 AURIX™ TC37x Safety Management Unit (SMU) MTU Pre-Alarm Mapping Table 187 MTU Pre-Alarm Mapping Alarm Source Logic Alarm Index CPU0.DMEM - Correctable error ALM0[9] CPU0.DLMU - Correctable error CPU0.DMEM1 - Correctable error CPU0.DMEM - Uncorrectable Critical error ALM0[10] CPU0.DLMU - Uncorrectable Critical error CPU0.DMEM1 - Uncorrectable Critical error CPU0.DMEM - Miscellaneous error ALM0[11]...
  • Page 309 AURIX™ TC37x Safety Management Unit (SMU) Table 187 MTU Pre-Alarm Mapping (cont’d) Alarm Source Logic Alarm Index DMA - Uncorrectable Critical error ALM6[20] PSI5 - Uncorrectable Critical error SCR.XRAM - Uncorrectable critical error SCR.RAMINT - Uncorrectable Critical error GIGETHERNET.RX0 - Uncorrectable Critical error GIGETHERNET.TX0 - Uncorrectable Critical error DMA - Miscellaneous error ALM6[21]...
  • Page 310 AURIX™ TC37x Safety Management Unit (SMU) Safety Flip-flop Pre-Alarm Mapping Table 188 Safety Flip-flop Pre-Alarm Mapping Alarm Source Logic Alarm Index MTU - Safety flip-flop uncorrectable error ALM10[21] IOM - Safety flip-flop uncorrectable error IR - Safety flip-flop uncorrectable error SCU - Safety flip-flop uncorrectable error PMS - Safety flip-flop uncorrectable error DMA - Safety flip-flop uncorrectable error...

  • Page 311: Tc37X Specific Alarms

    AURIX™ TC37x Safety Management Unit (SMU) Table 191 PMS Pre-Alarm Mapping (cont’d) Alarm Source Logic Alarm Index HSM.VDD - Over Voltage ALM9[16] HSM.VDDP3 - Over Voltage HSM.VEXT - Over Voltage PMS.VDD - Over voltage ALM9[3] PMS.VDDPD - Over voltage PMS.VDDP3 - Over voltage PMS.VDDM - Over voltage PMS.VEXT - Over voltage PMS.VEVRSB - Over voltage...
  • Page 312 AURIX™ TC37x Safety Management Unit (SMU) – The SRAMs monitored are the {PSPR, DSPR, DLMU} SRAMs of each CPU and the LMU SRAMs when available in the product. Alarm Mapping related to ALM0 group Table 192 Alarm Mapping related to ALM0 group Alarm Index Module Safety Mechanism &...
  • Page 313 AURIX™ TC37x Safety Management Unit (SMU) Table 192 Alarm Mapping related to ALM0 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM0[11] Safety Mechanism(s): SRAM Monitor Page 25 Alarm: CPU0 DSPR/DCACHE/DLMU Miscellaneous error detection Alarm Type: Level ALM0[12] Safety Mechanism: SRAM Monitor Alarm: CPU0 DCACHE TAG Single bit error correction Alarm Type: Level...
  • Page 314 AURIX™ TC37x Safety Management Unit (SMU) Table 193 Alarm Mapping related to ALM1 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM1[2] cpu_pfi_pfrwb_1 Safety Mechanism: PFLASH Read Path Monitor Alarm: CPU1 PFLASH1 Read Path Error Alarm Type: Pulse Note: If the CPU side PFLASH bank does not exist, PFLASH read path lockstep still exist.
  • Page 315 AURIX™ TC37x Safety Management Unit (SMU) Table 193 Alarm Mapping related to ALM1 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM1[22] cpu_pfi_pfrwb_1 Safety Mechanism: SRI End-to-End EDC Alarm: CPU1 Instruction Fetch SRI Interface EDC Error Alarm Type: Pulse ALM1[23] cpu_pfi_pfrwb_1 Safety Mechanism: SRI End-to-End EDC...
  • Page 316 AURIX™ TC37x Safety Management Unit (SMU) Table 194 Alarm Mapping related to ALM2 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM2[10] Safety Mechanism: SRAM Monitor Page 25 Alarm: CPU2 DSPR/DCACHE/DLMU Uncorrectable critical error detection Alarm Type: Level ALM2[11] Safety Mechanism(s): SRAM Monitor Page 25...
  • Page 317 AURIX™ TC37x Safety Management Unit (SMU) Alarm Mapping related to ALM4 group Table 196 Alarm Mapping related to ALM4 group Alarm Index Module Safety Mechanism & Alarm Indication ALM4[2:0] Reserved Reserved ALM4[3] Reserved Reserved ALM4[14:4] Reserved Reserved ALM4[21:15] Reserved Reserved ALM4[24:22] Reserved Reserved...
  • Page 318 AURIX™ TC37x Safety Management Unit (SMU) Table 198 Alarm Mapping related to ALM6 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM6[6] Safety Mechanism: Safety Flip-flop Alarm: Safety flip-flop uncorrectable error detected Alarm Type: Level ALM6[7] SMU_CORE Safety Mechanism: Safety Flip-flop Alarm: Safety flip-flop uncorrectable error detected Alarm Type: Level ALM6[8]...
  • Page 319 AURIX™ TC37x Safety Management Unit (SMU) Table 198 Alarm Mapping related to ALM6 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM6[21] Safety Mechanism: SRAM Monitor Page 26 Alarm: MISC Miscellaneous error detection Alarm Type: Level ALM6[22] Reserved Reserved ALM6[23] Safety Mechanism: Safety Flip-flop...
  • Page 320 AURIX™ TC37x Safety Management Unit (SMU) Table 199 Alarm Mapping related to ALM7 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM7[16] MINIMCDS Safety Mechanism: LMU Error Detection Code (EDC) Alarm: EDC Read Phase Error Alarm Type: Pulse ALM7[17] Safety Mechanism: Built-in SRI Error Detection Alarm: XBAR0 Bus Error Event...
  • Page 321 AURIX™ TC37x Safety Management Unit (SMU) Alarm Mapping related to ALM8 group Table 200 Alarm Mapping related to ALM8 group Alarm Index Module Safety Mechanism & Alarm Indication ALM8[0] Safety Mechanism: Clock Monitor Alarm: OSC clock frequency out of range Alarm Type: Pulse ALM8[1] Safety Mechanism: Clock Monitor...
  • Page 322 AURIX™ TC37x Safety Management Unit (SMU) Table 200 Alarm Mapping related to ALM8 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM8[16] Safety Mechanism: Watchdog Alarm: Safety Watchdog Time-out Alarm Type: Pulse ALM8[17] Safety Mechanism: All Watchdogs Alarm: Watchdog Time-out. This alarm is a logical OR over all watchdog time-out alarms Alarm Type: Pulse ALM8[18]...
  • Page 323 AURIX™ TC37x Safety Management Unit (SMU) Table 200 Alarm Mapping related to ALM8 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM8[29] Safety Mechanism: External Alarm Alarm: External Request Unit Alarm 7 Alarm Type: Pulse ALM8[30] Safety Mechanism: Core Domain Die Temperature Sensor Alarm: Under Temperature Alarm Alarm Type: Level ALM8[31]...
  • Page 324 AURIX™ TC37x Safety Management Unit (SMU) Table 201 Alarm Mapping related to ALM9 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM9[27] Reserved Reserved ALM9[28] Reserved Reserved ALM9[29] Reserved Reserved ALM9[30] Reserved Reserved ALM9[31] Reserved Reserved Alarm Mapping related to ALM10 group Table 202 Alarm Mapping related to ALM10 group Alarm Index Module...
  • Page 325 AURIX™ TC37x Safety Management Unit (SMU) Table 202 Alarm Mapping related to ALM10 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM10[11] Software Safety Mechanism: Software Monitor Alarm: Software Alarm 11 Alarm Type: Pulse ALM10[12] Software Safety Mechanism: Software Monitor Alarm: Software Alarm 12 Alarm Type: Pulse ALM10[13]...
  • Page 326 AURIX™ TC37x Safety Management Unit (SMU) Alarm Mapping related to ALM11 group Table 203 Alarm Mapping related to ALM11 group Alarm Index Module Safety Mechanism & Alarm Indication ALM11[0] Safety Mechanism: SRI Error Detection Code (EDC) Page 27 Alarm: EDC Address Phase Error Alarm Type: Pulse ALM11[1] Page 27...
  • Page 327 AURIX™ TC37x Safety Management Unit (SMU) Alarm Mapping related to ALM20 group Table 204 Alarm Mapping related to ALM20 group Alarm Index Module Safety Mechanism & Alarm Indication ALM20[3:0] Reserved Resreved ALM20[4] Safety Mechanism: Voltage Monitor Alarm: VDD Over-voltage Alarm Alarm Type: Level ALM20[5] Safety Mechanism: Voltage Monitor...
  • Page 328 AURIX™ TC37x Safety Management Unit (SMU) Alarm Mapping related to ALM21 group Table 205 Alarm Mapping related to ALM21 group Alarm Index Module Safety Mechanism & Alarm Indication ALM21[0] Safety Mechanism: Voltage Monitor Alarm: VDD Under-voltage Alarm Alarm Type: Level ALM21[1] Safety Mechanism: Voltage Monitor Alarm: VDDP3 Under-voltage Alarm...

  • Page 329: Connectivity

    AURIX™ TC37x Safety Management Unit (SMU) Table 205 Alarm Mapping related to ALM21 group (cont’d) Alarm Index Module Safety Mechanism & Alarm Indication ALM21[14] Safety Mechanism: Voltage Monitor Alarm: EV33 Short to High Alarm Alarm Type: Level ALM21[15] Safety Mechanism: Clock Alive Monitor Alarm: PLLx/fSPB Alive Alarm (provided on fBACK clock with x = 0..2) Alarm Type: Level Note: This alarm is also set if TCU related signals are activated in the...
  • Page 330 AURIX™ TC37x Safety Management Unit (SMU) Table 207 Revision History (cont’d) Reference Change to Previous Version Comment V4.0.19 Added FSI_RAM Alarms ALM7[0:2] which were not documented in the Page previous version Page 36 Added Alarm Types in Alarm Mapping Tables Page 29 Page 2 Typo fixed, no functional change...

  • Page 331: Interrupt Router (Ir)

    AURIX™ TC37x Interrupt Router (IR) Interrupt Router (IR) This chapter supplements the family documentation whith device specific information for TC37x. The Interrupt Router allocates two address ranges • Interrupt Router System and OTGM register address range: 2 * 256 byte address range covering the Interrupt Router system registers, ICU control registers and OTGM registers (Chapter 16.2)

  • Page 332: Tc37X Specific Control Registers

    AURIX™ TC37x Interrupt Router (IR) 16.2 TC37x Specific Control Registers This chapter describes the TC37x specific Interrupt Router system, OTGM and ICU registers List of used Access Protection Register abbreviations • P0 -> ACCEN_SRBx, write protection of the related SRBx register. Number of Service Request Broadcast registers (SRB) and the related ACCEN_SRB registers is equal to the number of implemented TriCore CPUs.
  • Page 333 AURIX™ TC37x Interrupt Router (IR) Table 211 Register Overview - INT (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write INT_ID Module Identification 0008 U,SV Application Register Reset Family Spec INT_SRBx Service Request Broadcast 0010 U,SV SV,P0...
  • Page 334 AURIX™ TC37x Interrupt Router (IR) Table 211 Register Overview - INT (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write INT_ACCEN_SRB Access Enable covering 0104 U,SV SV,SE Application SRBx, Register 1 Reset Family (x=0-2) Spec...

  • Page 335: Tc37X Specific Registers

    AURIX™ TC37x Interrupt Router (IR) 16.3 TC37x Specific Registers 16.3.1 IR Status and Control Registers OTGM IRQ Trace INT_OIT OTGM IRQ Trace (00A0 Application Reset Value: 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 TOS1 TOS0 Field...

  • Page 336: Tc37X Specific Service Request Control (Src) Registers

    AURIX™ TC37x Interrupt Router (IR) 16.4 TC37x Specific Service Request Control (SRC) registers This chapter describes the TC37x Service Request Control (SRC) registers. Table 213 shows all registers associated with the Interrupt Router module in the device. This chapter describes the Service Request Control registers including: •...
  • Page 337 AURIX™ TC37x Interrupt Router (IR) Table 213 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_QSPIxTX QSPIx Transmit Service 000F0 U,SV SV,P1,P2 Application (x=0-4) Request x*14 Reset SRC_QSPIxRX QSPIx Receive Service 000F4...
  • Page 338 AURIX™ TC37x Interrupt Router (IR) Table 213 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_GPT120T3 GPT120 Timer 3 Service 002E8 U,SV SV,P1,P2 Application Request Reset SRC_GPT120T4 GPT120 Timer 4 Service 002EC U,SV...
  • Page 339 AURIX™ TC37x Interrupt Router (IR) Table 213 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_DSADCSRM DSADC SRMx Service 00770 U,SV SV,P1,P2 Application Request Reset (x=0-5) SRC_DSADCSRAx DSADC SRAx Service 00774 U,SV...
  • Page 340 AURIX™ TC37x Interrupt Router (IR) Table 213 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_SCR Stand By Controller Service 008C0 U,SV SV,P1,P2 Application Request Reset SRC_SMUy SMU Service Request y 008D0 U,SV...
  • Page 341 AURIX™ TC37x Interrupt Router (IR) Table 213 Register Overview - SRC (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write SRC_GTMTIMwx TIMw Shared Service 00B90 U,SV SV,P1,P2 Application (w=0-5;x=0-7) Request x w*20 Reset SRC_GTMMCSwx MCSw Shared Service...

  • Page 342: Tc37X Specific Registers

    AURIX™ TC37x Interrupt Router (IR) 16.5 TC37x Specific Registers 16.5.1 IR Service Request Control Registers (SRC) CPUx Software Breakpoint Service Request SRC_CPUxSB (x=0-2) CPUx Software Breakpoint Service Request (00000 + x*4) Debug Reset Value: 0000 0000 SRC_BCUSPB SBCU Service Request [SPB Bus Control Unit) (00020 Debug Reset Value: 0000 0000 SRC_XBAR0 SRI Domain 0 Service Request...
  • Page 343 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 344 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 345 AURIX™ TC37x Interrupt Router (IR) SRC_QSPIxERR (x=0-4) QSPIx Error Service Request (000F8 +x*14 Application Reset Value: 0000 0000 SRC_QSPIxPT (x=0-4) QSPIx Phase Transition Service Request (000FC +x*14 Application Reset Value: 0000 0000 SRC_QSPIxU (x=0-4) QSPIx User Defined Service Request (00100 +x*14 Application Reset Value: 0000 0000 SRC_HSCT0...
  • Page 346 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated CPU2 service is initiated Others, Reserved (no action) 20:16...
  • Page 347 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_I2C0ERR I2C0 Error Service Request...
  • Page 348 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 349 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 350 AURIX™ TC37x Interrupt Router (IR) SRC_GPT120T6 GPT120 Timer 6 Service Request (002F4 Application Reset Value: 0000 0000 SRC_STMxSRy (x=0-2;y=0-1) System Timer x Service Request y (00300 +x*8+y*4) Application Reset Value: 0000 0000 SRC_FCE0 FCE0 Error Service Request (00330 Application Reset Value: 0000 0000 SRC_DMAERRy (y=0-3) DMA Error Service Request y (00340...
  • Page 351 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated CPU2 service is initiated Others, Reserved (no action) 20:16...
  • Page 352 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_VADCG10SRy (y=0-3) EVADC Group 10 Service Request y...
  • Page 353 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 354 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 355 AURIX™ TC37x Interrupt Router (IR) SRC_ERAY0NDAT0 E-RAY 0 New Data 0 Service Request (00810 Application Reset Value: 0000 0000 SRC_ERAY0NDAT1 E-RAY 0 New Data 1 Service Request (00814 Application Reset Value: 0000 0000 SRC_ERAY0MBSC0 E-RAY 0 Message Buffer Status Changed 0 Service Request(00818 Application Reset Value: 0000 0000 SRC_ERAY0MBSC1 E-RAY 0 Message Buffer Status Changed 1 Service Request(0081C...
  • Page 356 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated CPU2 service is initiated Others, Reserved (no action) 20:16...
  • Page 357 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_PMSDTS PMS DTS Service Request...
  • Page 358 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SRPN Service Request Priority Number The SRPN bit field defines the priority of a service request with respect to service requests with to the same service provider (same SRC.TOS configuration): -> Service request is on lowest priority ->...
  • Page 359 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description Interrupt Trigger Overflow Bit The IOV bit is set by HW if a new service request was triggered via interrupt trigger or SETR bit while the SRN has still an pending service request.
  • Page 360 AURIX™ TC37x Interrupt Router (IR) SRC_DAM0ERR DAM0 Error Service Request (00924 Application Reset Value: 0000 0000 SRC_PSI5Sy (y=0-7) PSI5-S Service Request y (00950 +y*4) Application Reset Value: 0000 0000 SRC_GPSRxy (x=0-2;y=0-7) General Purpose Group x Service Request y(00990 +x*20 +y*4) Application Reset Value: 0000 0000 SRC_GTMAEIIRQ AEI Shared Service Request...
  • Page 361 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated CPU2 service is initiated Others, Reserved (no action) 20:16...
  • Page 362 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SWSCLR SW Sticky Clear Bit SWSCLR is required to reset SWS. No action Clear SWS; bit value is not stored; read always returns 0. 9:8, Reserved 15:14, Read as 0; should be written with 0. 23:21, SRC_GTMERR Error Service Request...
  • Page 363 AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description Service Request Enable Service request is disabled Service request is enabled 13:11 Type of Service Control The TOS bit field configuration maps a Service Request to an Interrupt Service Provider: CPU0 service is initiated DMA service is initiated CPU1 service is initiated CPU2 service is initiated...

  • Page 364: Revision History

    AURIX™ TC37x Interrupt Router (IR) Field Bits Type Description SW Sticky Bit The Software Sticky Bit is set when the SRR bit has been set via the SETR bit. This bit can be cleared by writing with 1 to SWSCLR. Writing to SWS has no effect.

  • Page 365: Flexible Crc Engine (Fce)

    AURIX™ TC37x Flexible CRC Engine (FCE) Flexible CRC Engine (FCE) For the general description of the module and the registers, please refer to the family spec. 17.1 TC37x Specific IP Configuration There are no device specific IP configurations. User’s Manual 17-1 V2.0.0 FCE V4.2.9...

  • Page 366: Tc37X Specific Register Set

    AURIX™ TC37x Flexible CRC Engine (FCE) 17.2 TC37x Specific Register Set Table 215 Register Address Space - FCE Module Base Address End Address Note F0000000 F00001FF FPI slave interface Table 216 Register Overview - FCE (ascending Offset Address) Short Name Long Name Offset Access Mode...

  • Page 367: Tc37X Specific Registers

    AURIX™ TC37x Flexible CRC Engine (FCE) Table 216 Register Overview - FCE (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write FCE_LENGTHi CRC Length Register i +i*2 U,SV P,U,SV Application (i=0-7) Reset Family Spec FCE_CHECKi...

  • Page 368: Direct Memory Access (Dma)

    AURIX™ TC37x Direct Memory Access (DMA) Direct Memory Access (DMA) This is the TC37x specific information related to the DMA module of the AURIXTC3XX product family. 18.1 TC37x Specific IP Configuration The TC37x DMA contains 128 DMA channels. 18.2 TC37x Specific Register Set Table 219 Register Address Space - DMA Module...
  • Page 369 AURIX™ TC37x Direct Memory Access (DMA) Register Overview - DMA (ascending Offset Address) (cont’d) Table 220 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_MEm1R ME m Read Register 1 0144 U,SV Application (m=0-1) *1000 Reset Family Spec...
  • Page 370 AURIX™ TC37x Direct Memory Access (DMA) Register Overview - DMA (ascending Offset Address) (cont’d) Table 220 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_MEmCHSR ME m Channel Status 019C U,SV Application (m=0-1) Register m*1000 Reset Family Spec...

  • Page 371: Tc37X Specific Registers

    AURIX™ TC37x Direct Memory Access (DMA) Register Overview - DMA (ascending Offset Address) (cont’d) Table 220 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write DMA_DADRc DMARAM Channel c 200C U,SV SV,Pr Application (c=000-127) Destination Address Reset Family Register...
  • Page 372 AURIX™ TC37x Direct Memory Access (DMA) User’s Manual 18-5 V2.0.0 DMAV0.1.18 2021-02 OPEN MARKET VERSION...

  • Page 373: Signal Processing Unit (Spu)

    AURIX™ TC37x Signal Processing Unit (SPU) Signal Processing Unit (SPU) This device doesn’t contain a SPU module. User’s Manual 19-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 374: Spu Lockstep Comparator (Spulckstp)

    AURIX™ TC37x SPU Lockstep Comparator (SPULCKSTP) SPU Lockstep Comparator (SPULCKSTP) This device doesn’t contain a SPULCKSTP module. User’s Manual 20-1 V2.0.0 SPULCKSTP 2021-02 OPEN MARKET VERSION...

  • Page 375: Extension Memory (Emem)

    AURIX™ TC37x Extension Memory (EMEM) Extension Memory (EMEM) This device doesn’t contain an EMEM module. User’s Manual 21-1 V2.0.0 EMEM 2021-02 OPEN MARKET VERSION...

  • Page 376: Radar Interface (Rif)

    AURIX™ TC37x Radar Interface (RIF) Radar Interface (RIF) This device doesn’t contain a RIF module. User’s Manual 22-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 377: High Speed Pulse Density Modulation Module (Hspdm)

    AURIX™ TC37x High Speed Pulse Density Modulation Module (HSPDM) High Speed Pulse Density Modulation Module (HSPDM) This device doesn’t contain a HSPDM module. User’s Manual 23-1 V2.0.0 HSPDM 2021-02 OPEN MARKET VERSION...

  • Page 378: Camera And Adc Interface (Cif)

    AURIX™ TC37x Camera and ADC Interface (CIF) Camera and ADC Interface (CIF) This device doesn’t contain a CIF module. User’s Manual 24-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 379: System Timer (Stm)

    AURIX™ TC37x System Timer (STM) System Timer (STM) This chapter describes the device specific details in TC37x. 25.1 TC37x Specific IP Configuration See features in family spec 25.2 TC37x Specific Register Set Register Address Space Table The address space for the module registers is defined below Table 223 Register Address Space - STM Module Base Address...

  • Page 380: Revision History

    AURIX™ TC37x System Timer (STM) Table 225 Connections of STM1 (cont’d) Interface Signals connects Description STM1:SR1_INT CAN0:STM1.SR1_INT System Timer Service Request 1 CAN1:STM1.SR1_INT INT:stm1.SR1_INT Table 226 Connections of STM2 Interface Signals connects Description STM2:SR0_INT CAN0:STM2.SR0_INT System Timer Service Request 0 CAN1:STM2.SR0_INT INT:stm2.SR0_INT STM2:SR1_INT...

  • Page 381: Generic Timer Module (Gtm)

    AURIX™ TC37x Generic Timer Module (GTM) Generic Timer Module (GTM) The following chapter describes the specific TC37x GTM configuration. For the GTM IP functionalities, please refer to the Family specification. 26.1 TC37x Specific IP Configuration TC37x GTM Module Cluster0 0..7 ATOM0 DTM4..5 CDTM0...
  • Page 382 AURIX™ TC37x Generic Timer Module (GTM) Table 228 GTM Configuration by AURIX TC37x Product TC37x Modules 6x8 ch. (TIM0-5) 3x16 ch. (TOM0-2) ATOM 6x8 ch. (ATOM0-5) DTM/CDTM 3x4 ch., 2x2 ch./5xCDTM 5x8 ch. (MCS0-4) 2 (SPE0-1) 1 (PSM0) DPLL 4 (TBU0-3) GTM Clusters 6 (CCM0-5) (max speed)
  • Page 383 AURIX™ TC37x Generic Timer Module (GTM) Table 230 TC37x specific configuration of GTM Parameter Number of MCS modules Number of DPLL modules Number of PSM modules Number of TIM modules Number of ATOM DTM modules Number of TOM DTM modules Number of DSADC channels Number of primary EVADC groups Number of secondary EVADC groups...
  • Page 384 AURIX™ TC37x Generic Timer Module (GTM) Table 230 TC37x specific configuration of GTM (cont’d) Parameter List element 3 of MCS List element 4 of MCS List element 5 of MCS Number of Interrupt Groups for registers ICM_IRQG_CLS_k_MEI CCM0_CFG Reset Value 131199 CCM1_CFG Reset Value 131215...

  • Page 385: Tc37X Registers Register Set

    AURIX™ TC37x Generic Timer Module (GTM) 26.2 TC37x Registers Register Set Table 231 Register Address Space - GTM Module Base Address End Address Note F0100000 F01FFFFF FPI slave interface Register Overview Tables of GTM Table 232 Register Overview - GTM (ascending Offset Address) Short Name Long Name Offset...
  • Page 386 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_AEI_STA_X GTM AEI Non Zero Status 00002C U,SV,32 Application Register Reset Family Spec GTM_BRIDGE_M...
  • Page 387 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_TBU_CH0_ TBU Channel 0 Base 000108 U,SV,32 U,SV,32,P Application BASE Register Reset Family Spec...
  • Page 388 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_CMP_IRQ_ CMP Event Notification 000204 U,SV,32 U,SV,32,P Application NOTIFY Register Reset Family Spec GTM_CMP_IRQ_E...
  • Page 389 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_ARU_IRQ_N ARU Interrupt Notification 0002A4 U,SV,32 U,SV,32,P Application OTIFY Register Reset Family Spec GTM_ARU_IRQ_E...
  • Page 390 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_CMU_GCLK CMU Global Clock Control 000304 U,SV,32 U,SV,32,P Application _NUM Numerator Reset Family Spec...
  • Page 391 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_BRC_RST BRC Software Reset Register 000470 U,SV,32 U,SV,32,P Application Reset Family Spec GTM_BRC_EIRQ_ BRC Error Interrupt Enable...
  • Page 392 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_ICM_IRQG_ ICM Interrupt Group 000630 U,SV,32 Application Register for Module Error Reset Family Interrupt Information...
  • Page 393 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_ICM_IRQG_ ICM Interrupt Group ATOM k 000790 U,SV,32 Application ATOM_k_CI for Channel Interrupt +k*4 Reset Family...
  • Page 394 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_SPEi_CMD SPEi Command register 00084C U,SV,32 U,SV,32,P Application (i=0-1) +i*80 Reset Family Spec GTM_MAP_CTRL MAP Control Register...
  • Page 395 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_TIMi_CHx_I TIMi Channel x Interrupt 00102C U,SV,32 U,SV,32,P Application RQ_NOTIFY Notification Register +i*800 Reset Family...
  • Page 396 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_TOMi_CHx_ TOMi Channel x Status 008018 U,SV,32 Application STAT Register +i*800 Reset Family (i=0-2;x=0-15)
  • Page 397 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_TOMi_TGC1 TOMi TGC1 Action Time 008234 U,SV,32 U,SV,32,P Application _ACT_TB Base Register +i*800 Reset Family...
  • Page 398 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_FIFOi_CHz_ FIFOi Channel z Start 018408 U,SV,32 U,SV,32,P Application START_ADDR Address Register +z*40 Reset Family...
  • Page 399 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_CTRL DPLL Control Register 1 028004 U,SV,32 U,SV,32,P Application Reset Family Spec GTM_DPLL_CTRL DPLL Control Register 2...
  • Page 400 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_NTI_ DPLL Number of Active 02803C U,SV,32 U,SV,32,P Application TRIGGER Events to Interrupt Reset Family Spec...
  • Page 401 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_STAT DPLL Status Register 0280FC U,SV,32 U,SV,32,P Application Reset Family Spec GTM_DPLL_ID_P DPLL ID Information for 028100...
  • Page 402 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_TS_S DPLL Actual STATE Time 028410 U,SV,32 U,SV,32,P See Family Spec See Stamp Family Spec...
  • Page 403 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_NMB DPLL Target Number of 028450 U,SV,32 U,SV,32,P See Family Spec See _S_TAR Pulses to be Sent in Family...
  • Page 404 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_MED DPLL Weighted Difference of 02848C U,SV,32 U,SV,32,P See Family Spec See Prediction Errors of STATE Family Spec...
  • Page 405 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_PSTC DPLL Actual Calculated 0285E0 U,SV,32 U,SV,32,P See Family Spec See Position Stamp of TRIGGER Family Spec...
  • Page 406 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_ACB_ DPLL Control Bits Register z 028F00 U,SV,32 U,SV,32,P Application for up to 32 Actions +z*4 Reset Family...
  • Page 407 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_DPLL_DT_S DPLL Start Value of 028F50 U,SV,32 U,SV,32,P Application _START DPLL_DT_S_ACT for the Reset Family First Increment after SIP2 is...
  • Page 408 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_CLC Clock Control Register 09FD00 U,SV SV,E,P Application Reset Family Spec GTM_RESET_CLR Kernel Reset Status Clear 09FD04 U,SV...
  • Page 409 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_OCS OCDS Control and Status 09FD38 U,SV SV,P,OEN Debug Reset Family Spec GTM_TIMnINSEL TIMn Input Select Register...
  • Page 410 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_MSCSETiCO MSC Set i Control j Register 09FF00 U,SV U,SV,P Application +i*10 Reset (i=0;j=0-3)
  • Page 411 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_CCMi_EXT_ CCMi External Capture 0E21E4 U,SV,32 U,SV,32,P Application CAP_EN Trigger Enable Register +i*200 Reset Family...
  • Page 412 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_CDTMi_DT CDTMi DTMj Channel z Dead 0E4014 U,SV,32 U,SV,32,P Application Mj_CHz_DTV Time Reload Values +i*400 Reset...
  • Page 413 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_ATOMi_CHx ATOMi Channel x CCU0 0E8010 U,SV,32 U,SV,32,P Application _CM0 Compare Register +i*800 Reset Family...
  • Page 414 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_ATOMi_AG ATOMi AGC Force Update 0E8058 U,SV,32 U,SV,32,P Application C_FUPD_CTRL Control Register +i*800 Reset Family...
  • Page 415 AURIX™ TC37x Generic Timer Module (GTM) Table 232 Register Overview - GTM (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GTM_MCSi_REG_ MCSi Write Protection 0F0060 U,SV,32 U,SV,32,P Application PROT Register +i*1000 Reset Family (i=0-4)

  • Page 416: Tc37X Specific Registers

    AURIX™ TC37x Generic Timer Module (GTM) 26.3 TC37x Specific Registers 26.3.1 GTM IP Registers Specific Settings GTM Version Control Register Note: The numbers are encoded in BCD. Values "A" - "F" are characters. GTM_REV GTM Version Control Register (000000 Application Reset Value: 3133 15B9 DEV_CODE2 DEV_CODE1 DEV_CODE0...
  • Page 417 AURIX™ TC37x Generic Timer Module (GTM) GTM_CLS_CLK_CFG GTM Cluster Clock Configuration (0000B0 Application Reset Value: 0000 0AAA CLS5_CLK_DI CLS4_CLK_DI CLS3_CLK_DI CLS2_CLK_DI CLS1_CLK_DI CLS0_CLK_DI Field Bits Type Description 2*c+1:2*c CLSc_CLK_DI Cluster c Clock Divider This bit is only writable if bit field RF_PROT of register GTM_CTRL is V (c=0-5) cleared.
  • Page 418 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description ACT_CMUx CMU_CLKx activity (x=0-7) This bit will be cleared on a CPU write access of value 1. A read access leaves the bit unchanged. Bits is set, when a rising edge is detected at the considered clock. ACT_CMUFXx CMU_CLKFXx activity (x=0-4)
  • Page 419 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CADDR_END Set end value of ARU caddr counter The ARU roundtrip counter aru_caddr runs from zero to caddr_end value. Shorten the ARU roundtrip cycle by setting a smaller number than the defined reset value will cause that not all ARU-connected modules will be served.
  • Page 420 AURIX™ TC37x Generic Timer Module (GTM) NOTE: For the Clusters greater than 4, (only 100MHz capable), the only allowed settings for the CLS_CLK_DIV are 00 and 10 (clock divider 2). GTM_CCMi_CFG (i=0) CCMi Configuration Register (0E21F8 +i*200 Application Reset Value: 0002 007F TBU_D TBU_D CLS_CLK_DIV...
  • Page 421 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description EN_BRC Enable BRC This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is cleared. Disable clock signal for module BRC Enable clock signal for module BRC EN_PSM Enable PSM This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is cleared.
  • Page 422 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description EN_TIM Enable TIM This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is cleared. Disable clock signal for sub module TIM Enable clock signal for sub module TIM EN_TOM_SPE Enable TOM, SPE and TDTM _TDTM...
  • Page 423 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description Reserved Read as zero, shall be written as zero. 15:8, 29:18 GTM_CCMi_CFG (i=2) CCMi Configuration Register (0E21F8 +i*200 Application Reset Value: 0002 000F TBU_D TBU_D CLS_CLK_DIV EN_TO EN_AT EN_M EN_TI M_SPE OM_A _TDT...
  • Page 424 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CLS_CLK_DIV 17:16 Cluster Clock Divider The value of this bit field mirrors the bit field CLS[i]_CLK_DIV of register GTM_CLS_CLK_CFG, whereas i equals the cluster index. Cluster is disabled Cluster is enabled without clock divider Cluster is enabled with clock divider 2 Reserved, do not use.
  • Page 425 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description EN_ATOM_AD Enable ATOM and ADTM This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is cleared. Disable clock signal for modules ATOM and their related DTM modules. Enable clock signal for modules ATOM and their related DTM modules.
  • Page 426 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description EN_TIM Enable TIM This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is cleared. Disable clock signal for sub module TIM Enable clock signal for sub module TIM EN_ATOM_AD Enable ATOM and ADTM This bit is only writable if bit field CLS_PROT of register CCM[i]_PROT is...
  • Page 427 AURIX™ TC37x Generic Timer Module (GTM) CMU Control for Clock Source z GTM_CMU_CLK_z_CTRL (z=0-5) CMU Control for Clock Source z (00030C +z*4) Application Reset Value: 0000 0000 CLK_CNT CLK_CNT Field Bits Type Description 23:0 CLK_CNT Clock count Defines count value for the clock divider. Value can only be modified when clock enable EN_CLKz and EN_ECLK1 are disabled.
  • Page 428 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 25:24 CLK_SEL Clock source selection for CMU_CLKz Value can only be modified when clock enable EN_CLKz and EN_ECLK1 are disabled. Note: The existence and interpretation of this bit field depends on z. z>5 Use Clock Source 6 Divider Use signal SUB_INC2 of module DPLL / If no DPLL: Reserved, do not use.
  • Page 429 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SRC_CH0 Defines AUX_IN source of TIM[i] channel 0 SEL_OUT_N_CH0 / SEL_OUT_N_CH0 = 1: CDTM[i].DTM0 output DTM_OUT0 selected / CDTM[i].DTM0 output DTM_OUT1_N selected CDTM[i].DTM4 output DTM_OUT0 selected / CDTM[i].DTM4 output DTM_OUT1_N selected SRC_CH1 Defines AUX_IN source of TIM[i] channel 1 SEL_OUT_N_CH1 = 0 / SEL_OUT_N_CH1 = 1:...
  • Page 430 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SRC_CH7 Defines AUX_IN source of TIM[i] channel 7 SEL_OUT_N_CH7 = 0 / SEL_OUT_N_CH7 = 1: CDTM[i].DTM1 output DTM_OUT3 selected / CDTM[i].DTM0 output DTM_OUT0_N selected CDTM[i].DTM5 output DTM_OUT3 selected / CDTM[i].DTM4 output DTM_OUT0_N selected SEL_OUT_N_ Use DTM_OUT or DTM_OUT_N signals as AUX_IN source of TIM[i]...
  • Page 431 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description TIM_Mj_EIRQ Error interrupt TIMm_EIRQ (m=4*0+j) (j=0-3) This bit is only set when the error interrupt is enabled in the error interrupt enable register of the corresponding sub-module. No error interrupt occurred Error interrupt was raised by the corresponding sub-module MCS_Mj_EIRQ 8*j+1...
  • Page 432 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 24, 16, Reserved 25, 17, 9, Read as zero, shall be written as zero. 26, 18, 10, 2, 27, 19, 11, 3, 31:28, 23:20, 15:12, 7:4 ICM Interrupt Group ATOM k for Channel Interrupt Information of ATOMm GTM_ICM_IRQG_ATOM_k_CI (k=1) ICM Interrupt Group ATOM k for Channel Interrupt Information of ATOMm(000790 +k*4)Application Reset...
  • Page 433 AURIX™ TC37x Generic Timer Module (GTM) ICM Interrupt Group TOM k for Channel Interrupt Information of TOMm GTM_ICM_IRQG_TOM_k_CI (k=1) ICM Interrupt Group TOM k for Channel Interrupt Information of TOMm(0007A0 +k*4) Application Reset Value: 0000 0000 TOM_ TOM_ TOM_ TOM_ TOM_ TOM_ TOM_...
  • Page 434 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:5 Reserved Read as 0, shall be written with 0. Trigger Output Register n GTM_TRIGOUTn (n=0-4) Trigger Output Register n (09FE74 +n*4) Application Reset Value: 0000 0000 TRIG7 TRIG6 TRIG5 TRIG4 TRIG3 TRIG2...
  • Page 435 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description MCSn0 (n=0- MCSn RAM0 Interrupt 0 Status Flag The requested interrupt is SRC_GTMMCSWn0. This bit is cleared whenbit MCSINTCLR.MCSn is set. No interrupt was requested An interrupt was requested 31:5 Reserved Read as 0, shall be written with 0.
  • Page 436 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*k+3:4*k SELk (k=0) Selects which MCS triggers go to FCkBFDAT/SEL TRG0_01, TRIGOUT0_TRIG0/1 TRG1_01, TRIGOUT1_TRIG0/1 TRG2_01, TRIGOUT2_TRIG0/1 TRG3_01, TRIGOUT3_TRIG0/1 TRG4_01, TRIGOUT4_TRIG0/1 Reserved, do not use … Reserved, do not use SELk (k=1) 4*k+3:4*k Selects which MCS triggers go to FCkBFDAT/SEL TRG0_23, TRIGOUT0_TRIG2/3...
  • Page 437 AURIX™ TC37x Generic Timer Module (GTM) Data Exchange Input Control Register GTM_DXINCON Data Exchange Input Control Register (09FED0 Application Reset Value: 0000 0000 DSS4 DSS3 DSS2 DSS1 DSS0 Field Bits Type Description INx (x=0-4) Input 0x Control This bit defines whether register DATAINx is read from the MCS instead of RAM0 or not.
  • Page 438 AURIX™ TC37x Generic Timer Module (GTM) MCS0 Channel 0 Program Counter Register GTM_MCSi_CH0_PC (i=0-4) MCSi Channel 0 Program Counter Register(0F0040 +i*1000 Application Reset Value: 0000 0000 GTM_MCSi_CH1_PC (i=0-4) MCSi Channel 1 Program Counter Register(0F0040 +i*1000 Application Reset Value: 0000 0004 GTM_MCSi_CH2_PC (i=0-4) MCSi Channel 2 Program Counter Register(0F0040 +i*1000...

  • Page 439: Port To Gtm Tim Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.2 Port to GTM TIM Connections TIM0INSEL.CH7SEL..CH0SEL TIM0_7_IN 16:1 Muxes TIM0_0_IN 16:1 to TIM Signals from Ports/ Input EVADC/CAN/SCU/ERU/ TIM1_[7:0]_IN TIM1INSEL.CH7SEL..CH0SEL Muxes ERAY/DSADC-Mux TIM5_[7:0]_IN TIM5INSEL.CH7SEL..CH0SEL GTM_TIMINSEL_TC37x.vsd Figure 6 Port to GTM TIM Connections Overview GTM TIM Input Connections: IMUX Selection TIM0INSEL TIM3INSEL...
  • Page 440 AURIX™ TC37x Generic Timer Module (GTM) TIMn Input Select Register GTM_TIMnINSEL (n=0) TIMn Input Select Register (09FD40 +n*4) Application Reset Value: 0000 0000 CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM.
  • Page 441 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=1) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC1BFL, EVADC boundary flag level of FC channel 1 P00.10, Port pad input (no QFP144) P02.1, Port pad input...
  • Page 442 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=3) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC3BFL, EVADC boundary flag level of FC channel 3 P00.12, Port pad input P02.3, Port pad input...
  • Page 443 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=5) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P02.5, Port pad input P10.8, Port pad input (no QFP144)
  • Page 444 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=7) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P02.7, Port pad input P14.4, Port pad input...
  • Page 445 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC0BFL, EVADC boundary flag level of FC channel 0 P00.9, Port pad input P02.0, Port pad input...
  • Page 446 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=2) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC2BFL, EVADC boundary flag level of FC channel 2 P00.11, Port pad input (no QFP144) P02.2, Port pad input...
  • Page 447 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=4) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P02.4, Port pad input P10.0, Port pad input (no QFP144)
  • Page 448 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=6) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P02.6, Port pad input P10.4, Port pad input (no QFP144)
  • Page 449 AURIX™ TC37x Generic Timer Module (GTM) GTM_TIMnINSEL (n=2) TIMn Input Select Register (09FD40 +n*4) Application Reset Value: 0000 0000 CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module.
  • Page 450 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=1) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC1BFL, EVADC boundary flag level of FC channel 1 P00.1, Port pad input P00.2, Port pad input...
  • Page 451 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=3) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC3BFL, EVADC boundary flag level of FC channel 3 P00.4, Port pad input P11.6, Port pad input...
  • Page 452 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=5) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.6, Port pad input P11.10, Port pad input...
  • Page 453 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=7) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.8, Port pad input P11.12, Port pad input...
  • Page 454 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.0, Port pad input P02.8, Port pad input...
  • Page 455 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=2) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.3, Port pad input P11.3, Port pad input...
  • Page 456 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=4) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.5, Port pad input P11.9, Port pad input...
  • Page 457 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=6) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.7, Port pad input P11.11, Port pad input...
  • Page 458 AURIX™ TC37x Generic Timer Module (GTM) GTM_TIMnINSEL (n=4) TIMn Input Select Register (09FD40 +n*4) Application Reset Value: 0000 0000 CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module.
  • Page 459 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=1) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC1BFL, EVADC boundary flag level of FC channel 1 P00.15, Reserved, do not use P01.1, Reserved, do not use...
  • Page 460 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=3) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. FC3BFL, EVADC boundary flag level of FC channel 3 P01.13, Reserved, do not use P02.10, Port pad input (no QFP)
  • Page 461 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=5) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P01.2, Reserved, do not use P01.3, Port pad input (no QFP)
  • Page 462 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=7) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.14, Reserved, do not use P01.11, Reserved, do not use...
  • Page 463 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=0) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P00.13, Reserved, do not use P01.12, Reserved, do not use...
  • Page 464 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=2) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P01.9, Reserved, do not use P02.13, Reserved, do not use...
  • Page 465 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=4) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use Reserved, do not use P01.8, Reserved, do not use...
  • Page 466 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description CHxSEL (x=6) 4*x+3:4*x TIM Channel x Input Selection This bit defines which input is connected for TIMn channel x of the GTM. The input is either derived from a port pad or from an on-chip module. Reserved, do not use P01.15, Reserved, do not use P01.6, Port pad input (no QFP)
  • Page 467 AURIX™ TC37x Generic Timer Module (GTM) TIMi Channel x Control Register GTM_TIMi_CHx_CTRL (i=1-5;x=0-7) TIMi Channel x Control Register (001024 +i*800 +x*80 Application Reset Value: 0000 0000 FR_EC FLT_M FLT_M EGPR1 EGPR0 FLT_C FLT_C EXT_C FLT_CNT_FR FLT_E TOCTRL NT_OF CLK_SEL ODE_F ODE_R _SEL _SEL...
  • Page 468 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description ARU_EN GPR0 and GPR1 register values routed to ARU Registers content not routed Registers content routed CICTRL Channel Input Control Use signal TIM_IN(x) as input for channel x Use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is GPR0_SEL Selection for GPR0 register If EGPR0_SEL =0 / EGPR0_SEL =1 :...
  • Page 469 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description ECNT_RESET Enables resetting of counter in certain modes If TIM_MODE=0b101 (TGPS) / TIM_MODE=0b000 (TPWM) else ECNT counter operating in wrap around mode; In TIM_MODE=0b110 (TSSM), the bit field ECNT_RESET defines the initial polarity for the shift register.

  • Page 470: Timeout Control

    AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description FR_ECNT_OFL 27 Extended Edge counter overflow behavior Overflow will be signaled on ECNT bit width = 8 Overflow will be signaled on EECNT bit width (full range) EGPR0_SEL Extension of GPR0_SEL bit field Details described in GPR0_SEL bit field.

  • Page 471: Gtm To Port Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.3 GTM to Port Connections TOUTSEL0.SEL7..SEL0 TOUT0 TOM/ATOM/ 16:1 CDTM Outputs Muxes (8 * 16 lines) TOUT7 16:1 Port TOUT[15:8] TOUTSEL1.SEL7..SEL0 Outputs TOM/ATOM/ CDTM Outputs (18 * 8 * 16 lines) TOUT[150..144] TOUTSE L18.SEL6..SEL0 GTM_TOUTSEL_TC37x.vsd Figure 8 GTM to Port Connections Overview...
  • Page 472 AURIX™ TC37x Generic Timer Module (GTM) Table 234 Assignment of TOUTSELn Registers and SELx Bitfields to TOUTn Outputs (cont’d) Register SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 TOUTSEL8, TOUT71 TOUT70 TOUT69 TOUT68 TOUT67 TOUT66 TOUT65 TOUT64 Page 143 TOUTSEL9, TOUT79 TOUT78 TOUT77...
  • Page 473 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 474 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 475 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 476 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 477 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 478 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 479 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 480 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 481 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 482 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 483 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 484 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 485 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 486 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 487 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 488 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 489 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 490 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 491 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 492 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 493 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 494 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 495 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 496 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 497 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 498 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 499 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 500 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 501 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 502 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 503 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 504 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 505 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 506 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 507 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 508 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 509 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 510 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 511 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 512 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 513 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 514 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 515 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 516 AURIX™ TC37x Generic Timer Module (GTM) GTM_TOUTSELn (n=7) Timer Output Select Register (09FD60 +n*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 517 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 518 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 519 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 520 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 521 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 522 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 523 AURIX™ TC37x Generic Timer Module (GTM) GTM_TOUTSELn (n=8) Timer Output Select Register (09FD60 +n*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 524 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 525 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 526 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 527 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 528 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 529 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 530 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 531 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 532 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 533 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 534 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 535 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 536 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 537 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 538 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 539 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 540 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 541 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 542 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 543 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 544 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 545 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 546 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 547 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 548 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 549 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 550 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 551 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 552 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 553 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 554 AURIX™ TC37x Generic Timer Module (GTM) GTM_TOUTSELn (n=13) Timer Output Select Register (09FD60 +n*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 555 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 556 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 557 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 558 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 559 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 560 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 561 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 562 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 563 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 564 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=6) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 565 AURIX™ TC37x Generic Timer Module (GTM) GTM_TOUTSELn (n=15) Timer Output Select Register (09FD60 +n*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 566 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 567 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 568 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 569 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 570 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 571 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 572 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 573 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 574 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 575 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=2) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 576 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 577 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=7) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 578 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 579 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.
  • Page 580 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5) TOUT(n*8 + x) Output Selection This bit field defines which timer output is connected as TOUT(n*8+x). Note: SELx values not explicitly defined here are equivalent to the last defined SELx setting.

  • Page 581: Gtm Dtmauxinsel Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.4 GTM DTMAUXINSEL Connections DTMAU XINSEL.ASEL4..ASEL0 CDTM0_DTM4_AUXIN Port/EDSADC/ EVADC Outputs Muxes (5 * 4 lines) CDTM4_DTM4_AUXIN DTMAU XINSEL.TSEL2..TSEL0 CDTM0_DTM0_AUXIN Port/EVADC Outputs Muxes (3 * 4 lines) CDTM2_DTM0_AUXIN GTM_DTMAU X_TC37x.vsd Figure 10 DTM_AUXIN Connections Overview GTM DTMAUXINSEL Connections DTMAUXINSEL GTM_DTMAUXINSEL_Registers_TC37x.vsd...
  • Page 582 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 2*x+1:2*x ASELx (x=0) CDTMx_DTM4_AUX Input Selection (ATOMx_CH0...3) This bit field defines which GPIO/DSADC/EVADC signal is connected to the CDTMx_DTM4_AUX input. P02.0, Port pad input P02.8, Port pad input SWIB0, EDSADC within-band signal 0 CBFLOUT0, EVADC common boundary flag output 0 2*x+1:2*x ASELx (x=1)
  • Page 583 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 2*x+17:2*x TSELx (x=1) CDTMx_DTM0_AUX Input Selection (TOMx_CH0...3) This bit field defines which GPIO/DSADC/EVADC signal is connected to the CDTMx_DTM0_AUX input. P34.0, Reserved, do not use (TC33x only) P00.5, Port pad input (FC0BFLOUT) P33.0, Port pad input (not QFP144) (FC2BFLOUT) CBFLOUT1, EVADC common boundary flag output 1 2*x+17:2*x...

  • Page 584: Gtm To Msc (Micro Second Channel) Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.5 GTM to MSC (Micro Second Channel) Connections TOM/ 2nd Level ATOM/ MUXes CDTM 1st Level MSC0 Modules MUXes MSC0_ALTINL[15:0] ALTINL[15:0] SET0[15:0] MSC0_ALTINLEXT[15:0] MSC0 SET0 ALTINLEXT[15:0] Selection MSC0_ALTINH[15:0] ALTINH[15:0] SET1[15:0] MSC0_ALTINHEXT[15:0] ALTINHEXT[15:0] SET1 SET2[15:0] SET2 MSC1 MSC1_ALTINL[15:0]...
  • Page 585 AURIX™ TC37x Generic Timer Module (GTM) MSCSET0CON0.SEL3..SEL0 SET0[15] SET0[12] 32:1 MSCSET0CON1.SEL3..SEL0 SET0[11] SET0[8] 32:1 TOM/ATOM/ CDTM Outputs MSCSET0CON2.SEL3..SEL0 (16 * 32 lines) SET0[7] SET0[4] 32:1 MSCSET0CON3.SEL3..SEL0 SET0[3] SET0[0] 32:1 MSCSET1CON0.SEL3..SEL0 TOM/ATOM/ MSCSET1CON1.SEL3..SEL0 CDTM Outputs SET1[15:0] MSCSET1CON2.SEL3..SEL0 (16 * 32 lines) MSCSET1CON3.SEL3..SEL0 MSCSET3CON0.SEL3..SEL0 TOM/ATOM/...
  • Page 586 AURIX™ TC37x Generic Timer Module (GTM) MSCn Selection MSC0INLCON.SEL15..SEL0 MSC0_ALTINL[15] SETi[15] MSC0_ALTINHEXT[15] Muxes MSC0_ALTINL[0] SETi[0] MSC0_ALTINHEXT[0] MSC0INLEXTCON.SEL15..SEL0 MSC0_ALTINLEXT[15 SETi[15] Muxes SETi[0] MSC0_ALTINLEXT[0] MSC0INHCON.SEL15..SEL0 SETi[15] MSC0_ALTINH[15] Muxes SETi[0] MSC0_ALTINH[0] MSC1_ALTINL[15:0] MSC1INLCON.SEL15..SEL0 MSC1_ALTINHEXT[15:0] SETi Outputs MSC1_ALTINLEXT[15:0] MSC1INLEXTCON.SEL15..SEL0 (3 * 16 lines) MSC1_ALTINH[15:0] MSC1INHCON.SEL15..SEL0 GTM_MSC_Connections_Mux2_TC37x.vsd Figure 15...
  • Page 587 AURIX™ TC37x Generic Timer Module (GTM) Table 235 GTM to MSC Connections Registers Overview (cont’d) Register Long Name Selection Bitfields Page MSCSET2CON2 MSC Set 2 Control 2 Register (i=2;j=2) SEL8..SEL11 Page 222 MSCSET2CON3 MSC Set 2 Control 3 Register (i=2;j=3) SEL12..SEL15 Page 224 MSCSET3CON0...
  • Page 588 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 8*k+4:8*k SELk (k=0-3) Set 0[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM0_0, TOM0_0, Dead-time output of TOM0, channel 0 CDTM0_DTM0_1, TOM0_1, Dead-time output of TOM0, channel 1 CDTM0_DTM0_2, TOM0_2, Dead-time output of TOM0, channel 2 CDTM0_DTM0_3, TOM0_3, Dead-time output of TOM0, channel 3...
  • Page 589 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=0;j=1) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 Field Bits Type Description 8*k-28:8*k- SELk (k=4-7) Set 0[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM0_0, TOM0_0, Dead-time output of TOM0, channel 0 CDTM0_DTM0_1, TOM0_1, Dead-time output of TOM0, channel 1 CDTM0_DTM0_2, TOM0_2, Dead-time output of TOM0, channel 2...
  • Page 590 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=0;j=2) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL11 SEL10 SEL9 SEL8...
  • Page 591 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SELk (k=8-11) 8*k-60:8*k- Set 0[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM0_0, TOM0_0, Dead-time output of TOM0, channel 0 CDTM0_DTM0_1, TOM0_1, Dead-time output of TOM0, channel 1 CDTM0_DTM0_2, TOM0_2, Dead-time output of TOM0, channel 2 CDTM0_DTM0_3, TOM0_3, Dead-time output of TOM0, channel 3...
  • Page 592 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=0;j=3) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 Field Bits Type Description 8*k-92:8*k- SELk (k=12- Set 0[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM0_0, TOM0_0, Dead-time output of TOM0, channel 0 CDTM0_DTM0_1, TOM0_1, Dead-time output of TOM0, channel 1 CDTM0_DTM0_2, TOM0_2, Dead-time output of TOM0, channel 2...
  • Page 593 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=1;j=0) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL3 SEL2 SEL1 SEL0...
  • Page 594 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 8*k+4:8*k SELk (k=0-3) Set 1[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM1_DTM0_0, TOM1_0, Dead-time output of TOM1, channel 0 CDTM1_DTM0_1, TOM1_1, Dead-time output of TOM1, channel 1 CDTM1_DTM0_2, TOM1_2, Dead-time output of TOM1, channel 2 CDTM1_DTM0_3, TOM1_3, Dead-time output of TOM1, channel 3...
  • Page 595 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=1;j=1) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 Field Bits Type Description 8*k-28:8*k- SELk (k=4-7) Set 1[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM1_DTM0_0, TOM1_0, Dead-time output of TOM1, channel 0 CDTM1_DTM0_1, TOM1_1, Dead-time output of TOM1, channel 1 CDTM1_DTM0_2, TOM1_2, Dead-time output of TOM1, channel 2...
  • Page 596 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=1;j=2) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL11 SEL10 SEL9 SEL8...
  • Page 597 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SELk (k=8-11) 8*k-60:8*k- Set 1[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM1_DTM0_0, TOM1_0, Dead-time output of TOM1, channel 0 CDTM1_DTM0_1, TOM1_1, Dead-time output of TOM1, channel 1 CDTM1_DTM0_2, TOM1_2, Dead-time output of TOM1, channel 2 CDTM1_DTM0_3, TOM1_3, Dead-time output of TOM1, channel 3...
  • Page 598 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=1;j=3) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 Field Bits Type Description 8*k-92:8*k- SELk (k=12- Set 1[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM1_DTM0_0, TOM1_0, Dead-time output of TOM1, channel 0 CDTM1_DTM0_1, TOM1_1, Dead-time output of TOM1, channel 1 CDTM1_DTM0_2, TOM1_2, Dead-time output of TOM1, channel 2...
  • Page 599 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=2;j=0) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL3 SEL2 SEL1 SEL0...
  • Page 600 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 8*k+4:8*k SELk (k=0-3) Set 2[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM2_DTM0_0, TOM2_0, Dead-time output of TOM2, channel 0 CDTM2_DTM0_1, TOM2_1, Dead-time output of TOM2, channel 1 CDTM2_DTM0_2, TOM2_2, Dead-time output of TOM2, channel 2 CDTM2_DTM0_3, TOM2_3, Dead-time output of TOM2, channel 3...
  • Page 601 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=2;j=1) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 Field Bits Type Description 8*k-28:8*k- SELk (k=4-7) Set 2[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM2_DTM0_0, TOM2_0, Dead-time output of TOM2, channel 0 CDTM2_DTM0_1, TOM2_1, Dead-time output of TOM2, channel 1 CDTM2_DTM0_2, TOM2_2, Dead-time output of TOM2, channel 2...
  • Page 602 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=2;j=2) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL11 SEL10 SEL9 SEL8...
  • Page 603 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SELk (k=8-11) 8*k-60:8*k- Set 2[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM2_DTM0_0, TOM2_0, Dead-time output of TOM2, channel 0 CDTM2_DTM0_1, TOM2_1, Dead-time output of TOM2, channel 1 CDTM2_DTM0_2, TOM2_2, Dead-time output of TOM2, channel 2 CDTM2_DTM0_3, TOM2_3, Dead-time output of TOM2, channel 3...
  • Page 604 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=2;j=3) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 Field Bits Type Description 8*k-92:8*k- SELk (k=12- Set 2[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM2_DTM0_0, TOM2_0, Dead-time output of TOM2, channel 0 CDTM2_DTM0_1, TOM2_1, Dead-time output of TOM2, channel 1 CDTM2_DTM0_2, TOM2_2, Dead-time output of TOM2, channel 2...
  • Page 605 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=3;j=0) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL3 SEL2 SEL1 SEL0...
  • Page 606 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 8*k+4:8*k SELk (k=0-3) Set 3[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM4_0, ATOM0_0, Dead-time output of ATOM0, channel 0 CDTM0_DTM4_1, ATOM0_1, Dead-time output of ATOM0, channel 1 CDTM0_DTM4_2, ATOM0_2, Dead-time output of ATOM0, channel 2 CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel 3...
  • Page 607 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=3;j=1) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 Field Bits Type Description 8*k-28:8*k- SELk (k=4-7) Set 3[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM4_0, ATOM0_0, Dead-time output of ATOM0, channel 0 CDTM0_DTM4_1, ATOM0_1, Dead-time output of ATOM0, channel 1 CDTM0_DTM4_2, ATOM0_2, Dead-time output of ATOM0, channel 2...
  • Page 608 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 GTM_MSCSETiCONj (i=3;j=2) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL11 SEL10 SEL9 SEL8...
  • Page 609 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description SELk (k=8-11) 8*k-60:8*k- Set 3[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM4_0, ATOM0_0, Dead-time output of ATOM0, channel 0 CDTM0_DTM4_1, ATOM0_1, Dead-time output of ATOM0, channel 1 CDTM0_DTM4_2, ATOM0_2, Dead-time output of ATOM0, channel 2 CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel 3...
  • Page 610 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCSETiCONj (i=3;j=3) MSC Set i Control j Register (09FF00 +i*10 +j*4) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 Field Bits Type Description 8*k-92:8*k- SELk (k=12- Set 3[k] Input Selection This bit field defines the GTM timer source configured as Set i signal k out. CDTM0_DTM4_0, ATOM0_0, Dead-time output of ATOM0, channel 0 CDTM0_DTM4_1, ATOM0_1, Dead-time output of ATOM0, channel 1 CDTM0_DTM4_2, ATOM0_2, Dead-time output of ATOM0, channel 2...
  • Page 611 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 31:29, Reserved 23:21, Read as 0, shall be written with 0. 15:13, 7:5 MSCi Input Low Control Register GTM_MSCiINLCON (i=0) MSCi Input Low Control Register (09FF90 +i*12) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13...
  • Page 612 AURIX™ TC37x Generic Timer Module (GTM) MSCi Input Low Extended Control Register GTM_MSCiINLEXTCON (i=0) MSCi Input Low Extended Control Register (09FF98 +i*12) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 SEL11 SEL10 SEL9 SEL8 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0...
  • Page 613 AURIX™ TC37x Generic Timer Module (GTM) GTM_MSCiINHCON (i=1) MSCi Input High Control Register (09FF94 +i*12) Application Reset Value: 0000 0000 SEL15 SEL14 SEL13 SEL12 SEL11 SEL10 SEL9 SEL8 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description SELx (x=0-15) 2*x+1:2*x GTM MSCq High x Output Selection GTM output gtm_mscqaltinh[x] is controlled by the timer output.

  • Page 614: Edsadc To Gtm Tim Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.6 EDSADC to GTM TIM Connections DSADCINSEL0.INSEL7..INSEL0 EDSADC IMUX0_7 SRM0 Channel 0 SAUL0 16:1 SBLL0 Muxes Channel 1 IMUX0_0 16:1 Channel 2 Channel 3 IMUX1_[7:0] Channel 4 DSADCINSEL1.INSEL7..INSEL0 to TIM Channel 5 Input IMUX2_[7:0] DSADCINSEL2.INSEL7..INSEL0 Muxes IMUX3_[7:0]...
  • Page 615 AURIX™ TC37x Generic Timer Module (GTM) DSADC Input Select i Register GTM_DSADCINSELi (i=0) DSADC Input Select i Register (09FE00 +i*4) Application Reset Value: 0000 0000 INSEL7 INSEL6 INSEL5 INSEL4 INSEL3 INSEL2 INSEL1 INSEL0 Field Bits Type Description 4*j+3:4*j INSELj (j=0) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j.
  • Page 616 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=1) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 617 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=3) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 618 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=5) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 619 AURIX™ TC37x Generic Timer Module (GTM) GTM_DSADCINSELi (i=1) DSADC Input Select i Register (09FE00 +i*4) Application Reset Value: 0000 0000 INSEL7 INSEL6 INSEL5 INSEL4 INSEL3 INSEL2 INSEL1 INSEL0 Field Bits Type Description 4*j+3:4*j INSELj (j=0) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j.
  • Page 620 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=1) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 621 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=3) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 622 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=5) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 623 AURIX™ TC37x Generic Timer Module (GTM) GTM_DSADCINSELi (i=2) DSADC Input Select i Register (09FE00 +i*4) Application Reset Value: 0000 0000 INSEL7 INSEL6 INSEL5 INSEL4 INSEL3 INSEL2 INSEL1 INSEL0 Field Bits Type Description 4*j+3:4*j INSELj (j=0) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j.
  • Page 624 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=2) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 625 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=5) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM0, Input signal is DSADC_SRM0 SRM1, Input signal is DSADC_SRM1 SRM2, Input signal is DSADC_SRM2...
  • Page 626 AURIX™ TC37x Generic Timer Module (GTM) GTM_DSADCINSELi (i=3) DSADC Input Select i Register (09FE00 +i*4) Application Reset Value: 0000 0000 INSEL7 INSEL6 INSEL5 INSEL4 INSEL3 INSEL2 INSEL1 INSEL0 Field Bits Type Description 4*j+3:4*j INSELj (j=0) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j.
  • Page 627 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=2) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 628 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=5) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 629 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=0) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 630 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=4) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 631 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=7) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 632 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=1) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...
  • Page 633 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*j+3:4*j INSELj (j=5) In Selection for DSADCn GTM connection This bit field defines which DSADCn output is connected if the channel input mux is configured as DSADC input for TIMi channel j. SRM2, Input signal is DSADC_SRM2 SRM3, Input signal is DSADC_SRM3 SRM4, Input signal is DSADC_SRM4...

  • Page 634: Gtm To Edsadc Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.7 GTM to EDSADC Connections DSADC_TRIG0[3:0] to SENT_TRIG[15:12] DSADCOU TSEL00.SEL5..SEL0 DSADC_TRIG0[5] TOM/ATOM/ 16:1 CDTM Outputs Muxes (6 * 16 lines) DSADC_TRIG0[0] 16:1 TOM/ATOM/ EDSADC CDTM Outputs DSADC_TRIG1[5:0] DSADCOU TSEL10.SEL5..SEL0 Trigger (6 * 16 lines) Inputs TOM/ATOM/ CDTM Outputs...
  • Page 635 AURIX™ TC37x Generic Timer Module (GTM) Table 238 GTM to EDSADC Connections Overview EDSADC/SENT Trigger Inputs Signal SELi x = 0 x = 1 x = 2 x = 3 DSADC_TRIGx_0 SEL0 ITR0A ITR0B ITR0M ITR0N SENT: TRIG12 DSADC_TRIGx_1 SEL1 ITR1A ITR1B ITR1M...
  • Page 636 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-5) Output Selection for DSADCx GTM connection This bit field defines which TOM/ATOM channel output is used as DSADCx trigger i. CDTM0_DTM1_2, TOM0_6, Dead-time output of TOM0, channel 6 CDTM0_DTM1_3, TOM0_7, Dead-time output of TOM0, channel 7 TOM0_13, Output of TOM0, channel 13 TOM0_14, Output of TOM0, channel 14...
  • Page 637 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-5) Output Selection for DSADCx GTM connection This bit field defines which TOM/ATOM channel output is used as DSADCx trigger i. CDTM2_DTM1_2, TOM2_6, Dead-time output of TOM2, channel 6 CDTM2_DTM1_3, TOM2_7, Dead-time output of TOM2, channel 7 TOM2_13, Output of TOM2, channel 13 TOM2_14, Output of TOM2, channel 14...
  • Page 638 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-5) Output Selection for DSADCx GTM connection This bit field defines which TOM/ATOM channel output is used as DSADCx trigger i. CDTM1_DTM1_3, TOM1_7, Dead-time output of TOM1, channel 7 TOM1_14, Output of TOM1, channel 14 Reserved, do not use …...

  • Page 639: Evadc To Gtm Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.8 EVADC to GTM Connections The number of FCxBFL and CBFLOUTx signals from the EVADC to the MCS data inputs is product specific. See the following table for the connections available in this device. Table 239 MCS Data Input Signal Connections MCS Status Input Input...

  • Page 640: Gtm To Evadc Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.9 GTM to EVADC Connections ADCTRIG0OUT0.SEL7..SEL0 ADC_TRIG0[7] TOM/ATOM/ 16:1 CDTM Outputs Muxes (8 * 16 lines) ADC_TRIG0[0] 16:1 to SENT_TRIG[11:0], EVADC and DSADC ADCTRIG0OUT1.SEL3..SEL0 Trigger Inputs TOM/ATOM/ ADC_TRIG0[11] CDTM Outputs Muxes ADC_TRIG0[8] (4 * 16 lines) 16:1 TOM/ATOM/ ADC_TRIG1[7:0]...
  • Page 641 AURIX™ TC37x Generic Timer Module (GTM) Table 240 GTM to EVADC Connections Registers Overview Register Long Name Selection Bitfields Page ADCTRIG0OUT0 ADC Trigger 0 Output Select 0 Register (i=0) SEL0..SEL7 Page 262 ADCTRIG0OUT1 ADC Trigger 0 Output Select 1 Register (i=0) SEL0..SEL3 Page 265 ADCTRIG1OUT0...
  • Page 642 AURIX™ TC37x Generic Timer Module (GTM) Table 241 Connections of ADC_TRIGx Signals to ADC/SENT Modules (cont’d) GTM Trigger EVADC EDSADC SENT Signal ADC_TRIG4 ADC_TRIG4_[3:0] G[3:0]REQGTL G[3:0]REQTRL ADC_TRIG4_[7:4] ADC_TRIG4_[9:8] FC[1:0]REQTRM G[9:8]REQGTL G[9:8]REQTRL ADC_TRIG4_[11:10] - G[11:10]REQGTL G[11:10]REQTRL ADC Trigger i Output Select 0 Register GTM_ADCTRIGiOUT0 (i=0) ADC Trigger i Output Select 0 Register (09FE40...
  • Page 643 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-2) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM1_2, TOM0_6, Dead-time output of TOM0, channel 6 CDTM0_DTM1_3, TOM0_7, Dead-time output of TOM0, channel 7 TOM0_13, Output of TOM0, channel 13 TOM0_14, Output of TOM0, channel 14...
  • Page 644 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3-4) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM1_2, TOM0_6, Dead-time output of TOM0, channel 6 CDTM0_DTM1_3, TOM0_7, Dead-time output of TOM0, channel 7 TOM0_13, Output of TOM0, channel 13 TOM0_14, Output of TOM0, channel 14...
  • Page 645 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5-7) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM2_DTM1_2, TOM2_6, Dead-time output of TOM2, channel 6 CDTM2_DTM1_3, TOM2_7, Dead-time output of TOM2, channel 7 TOM0_13, Output of TOM0, channel 13 TOM0_14, Output of TOM0, channel 14...
  • Page 646 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-3) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx+8 trigger i. No trigger CDTM0_DTM1_2, TOM0_6, Dead-time output of TOM0, channel 6 CDTM0_DTM1_3, TOM0_7, Dead-time output of TOM0, channel 7 TOM0_13, Output of TOM0, channel 13 TOM0_14, Output of TOM0, channel 14...
  • Page 647 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-2) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM1_DTM1_2, TOM1_6, Dead-time output of TOM1, channel 6 CDTM1_DTM1_3, TOM1_7, Dead-time output of TOM1, channel 7 TOM1_13, Output of TOM1, channel 13 TOM1_14, Output of TOM1, channel 14...
  • Page 648 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3-4) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM1_DTM1_2, TOM1_6, Dead-time output of TOM1, channel 6 CDTM1_DTM1_3, TOM1_7, Dead-time output of TOM1, channel 7 TOM1_13, Output of TOM1, channel 13 TOM1_14, Output of TOM1, channel 14...
  • Page 649 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5-7) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger TOM2_14, Output of TOM2, channel 14 TOM2_15, Output of TOM2, channel 15 TOM1_13, Output of TOM1, channel 13 TOM1_14, Output of TOM1, channel 14...
  • Page 650 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-3) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx+8 trigger i. No trigger CDTM1_DTM1_2, TOM1_6, Dead-time output of TOM1, channel 6 CDTM1_DTM1_3, TOM1_7, Dead-time output of TOM1, channel 7 TOM1_13, Output of TOM1, channel 13 TOM1_14, Output of TOM1, channel 14...
  • Page 651 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-2) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM0_3, TOM0_3, Dead-time output of TOM0, channel 3 CDTM0_DTM1_0, TOM0_4, Dead-time output of TOM0, channel 4 CDTM0_DTM1_1(_N), TOM0_5_N, Inverted dead-time output of TOM0, channel 5...
  • Page 652 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5-7) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM0_3, TOM0_3, Dead-time output of TOM0, channel 3 CDTM0_DTM1_0, TOM0_4, Dead-time output of TOM0, channel 4 CDTM0_DTM1_1(_N), TOM0_5_N, Inverted dead-time output of TOM0, channel 5...
  • Page 653 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-3) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx+8 trigger i. No trigger CDTM0_DTM0_3, TOM0_3, Dead-time output of TOM0, channel 3 CDTM0_DTM1_0, TOM0_4, Dead-time output of TOM0, channel 4 CDTM0_DTM1_1(_N), TOM0_5_N, Inverted dead-time output of TOM0, channel 5...
  • Page 654 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-2) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel CDTM0_DTM5_1(_N), ATOM0_5_N, Inverted dead-time output of ATOM0, channel 5 CDTM1_DTM4_3, ATOM1_3, Dead-time output of ATOM1, channel...
  • Page 655 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3-4) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel CDTM0_DTM5_1(_N), ATOM0_5_N, Inverted dead-time output of ATOM0, channel 5 CDTM1_DTM4_3, ATOM1_3, Dead-time output of ATOM1, channel...
  • Page 656 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=5-7) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel CDTM0_DTM5_1(_N), ATOM0_5_N, Inverted dead-time output of ATOM0, channel 5 CDTM1_DTM4_3, ATOM1_3, Dead-time output of ATOM1, channel...
  • Page 657 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-3) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx+8 trigger i. No trigger CDTM0_DTM4_3, ATOM0_3, Dead-time output of ATOM0, channel CDTM0_DTM5_1(_N), ATOM0_5_N, Inverted dead-time output of ATOM0, channel 5 CDTM1_DTM4_3, ATOM1_3, Dead-time output of ATOM1, channel...
  • Page 658 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=0-2) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx trigger i. No trigger CDTM2_DTM0_3, TOM2_3, Dead-time output of TOM2, channel 3 CDTM2_DTM1_0, TOM2_4, Dead-time output of TOM2, channel 4 CDTM2_DTM1_1(_N), TOM2_5_N, Inverted dead-time output of TOM2, channel 5...
  • Page 659 AURIX™ TC37x Generic Timer Module (GTM) GTM_ADCTRIGiOUT1 (i=4) ADC Trigger i Output Select 1 Register (09FE44 +i*8) Application Reset Value: 0000 0000 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0-3) Output Selection for GTM to ADCx connection This bit field defines which TOM/ATOM channel output is used as ADCx+8 trigger i.

  • Page 660: Gtm To Can/Ttcan Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.10 GTM to CAN/TTCAN Connections CANOUTSEL0.SEL3..SEL0 TOM/ATOM/ CAN0_TRIG0[3] CDTM Outputs Muxes CAN0_TRIG0[0] (4 * 16 lines) 16:1 CANOUTSEL0.SEL7..SEL4 TOM/ATOM/ CAN1_TRIG0[3] CANx CDTM Outputs Muxes Trigger CAN1_TRIG0[0] (4 * 16 lines) 16:1 Inputs CANOUTSEL1.SEL3..SEL0 TOM/ATOM/ CAN2_TRIG0[3] CDTM Outputs Muxes...
  • Page 661 AURIX™ TC37x Generic Timer Module (GTM) GTM_CANOUTSEL0 CAN0/CAN1 Output Select Register (09FFDC Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) Output Selection for GTM to CAN connection x This bit field defines which TOM/ATOM channel output is used as CAN0/CAN1 node trigger x.
  • Page 662 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) Output Selection for GTM to CAN connection x This bit field defines which TOM/ATOM channel output is used as CAN0/CAN1 node trigger x. CDTM1_DTM1_0, TOM1_4, Dead-time output of TOM1, channel 4 CDTM1_DTM1_1, TOM1_5, Dead-time output of TOM1, channel 5 TOM1_11, Output of TOM1, channel 11 TOM1_12, Output of TOM1, channel 12...
  • Page 663 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=4-5) Output Selection for GTM to CAN connection x This bit field defines which TOM/ATOM channel output is used as CAN0/CAN1 node trigger x. CDTM1_DTM1_0, TOM1_4, Dead-time output of TOM1, channel 4 CDTM1_DTM1_1, TOM1_5, Dead-time output of TOM1, channel 5 TOM1_11, Output of TOM1, channel 11 TOM1_12, Output of TOM1, channel 12...
  • Page 664 AURIX™ TC37x Generic Timer Module (GTM) GTM_CANOUTSEL1 CAN2 Output Select Register (09FFE0 Application Reset Value: XXXX 0000 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0) Output Selection for GTM to CAN connection x This bit field defines which TOM/ATOM channel output is used as CAN2 node trigger x.
  • Page 665 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1) Output Selection for GTM to CAN connection x This bit field defines which TOM/ATOM channel output is used as CAN2 node trigger x. CDTM1_DTM1_0, TOM1_4, Dead-time output of TOM1, channel 4 CDTM1_DTM1_1, TOM1_5, Dead-time output of TOM1, channel 5 TOM1_11, Output of TOM1, channel 11 TOM1_12, Output of TOM1, channel 12...

  • Page 666: Gtm To Psi5(S) Connections

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.11 GTM to PSI5(S) Connections PSI5OUTSEL.SEL5..SEL0 PSI5_TRIG5 TOM/ATOM/ 16:1 PSI5 CDTM Outputs Trigger Muxes (6 * 16 lines) PSI5_TRIG0 Inputs 16:1 GTM_PSI5_TC37x.vsd Figure 24 GTM to PSI5 Connections Overview PSI5SOUTSEL.SEL3..SEL0 TOM/ATOM/ PSI5S_TRIG3 CDTM Outputs Muxes PSI5S_TRIG0 (4 * 16 lines)
  • Page 667 AURIX™ TC37x Generic Timer Module (GTM) PSI5 Output Select Register GTM_PSI5OUTSEL PSI5 Output Select Register (09FFCC Application Reset Value: 0000 0000 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0-5) Output Selection for GTM to PSI5x connection This bit field defines which TOM/ATOM channel output is used as PSI5 trigger x.

  • Page 668: Type Description

    AURIX™ TC37x Generic Timer Module (GTM) PSI5-S Output Select Register GTM_PSI5SOUTSEL PSI5-S Output Select Register (09FFD0 Application Reset Value: 0000 0000 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 Field Bits Type Description 4*x+3:4*x SELx (x=0,4) Output Selection for GTM to PSI5-S connection This bit field defines which TOM/ATOM channel output is used as PSI5-S trigger x.
  • Page 669 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=1,5) Output Selection for GTM to PSI5-S connection This bit field defines which TOM/ATOM channel output is used as PSI5-S trigger x. No trigger CDTM1_DTM1_2, TOM1_6, Dead-time output of TOM1, channel 6 CDTM1_DTM1_3, TOM1_7, Dead-time output of TOM1, channel 7 TOM1_13, Output of TOM1, channel 13 TOM1_14, Output of TOM1, channel 14...
  • Page 670 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description 4*x+3:4*x SELx (x=3,7) Output Selection for GTM to PSI5-S connection This bit field defines which TOM/ATOM channel output is used as PSI5-S trigger x. No trigger CDTM2_DTM1_2, TOM2_6, Dead-time output of TOM2, channel 6 CDTM2_DTM1_3, TOM2_7, Dead-time output of TOM2, channel 7 TOM2_13, Output of TOM2, channel 13 TOM2_14, Output of TOM2, channel 14...

  • Page 671: Gtm To Lc Dc/Dc Connection

    AURIX™ TC37x Generic Timer Module (GTM) 26.3.12 GTM to LC DC/DC Connection LCDCDCOUTSEL.SEL TOM/ATOM/ CDTM Outputs DCDC_TRIG 16:1 (up to 16 lines) GTM_LCDCDCOUTSEL_TC37x.vsd Figure 27 GTM to LCDCDC Connections Overview GTM to LCDCDC Connections: Trigger Selection LCDCDCOUTSEL0 GTM_LCDCDC_Registers_TC37x.vsd Figure 28 GTM to LCDCDC Connections Registers Overview LCDCDC Output Select Register GTM_LCDCDCOUTSEL...
  • Page 672 AURIX™ TC37x Generic Timer Module (GTM) Field Bits Type Description Output Selection for GTM to LCDCDC connection This bit field defines which TOM/ATOM channel output is used as LCDCDC signal. No trigger CDTM0_DTM4_1, ATOM0_1, Dead-time output of ATOM0, channel CDTM1_DTM4_1, ATOM1_1, Dead-time output of ATOM1, channel CDTM2_DTM4_1, ATOM2_1, Dead-time output of ATOM2, channel CDTM3_DTM4_1, ATOM3_1, Dead-time output of ATOM3, channel CDTM4_DTM4_1, ATOM4_1, Dead-time output of ATOM4, channel...

  • Page 673: Aru Parameters

    AURIX™ TC37x Generic Timer Module (GTM) 26.4 ARU Parameters The following sections list the device-specific parameters of the ARU. 26.4.1 ARU Write Address Overview The ARU write address map for the TC37x is specified in the following table. Table 242 ARU Write Addresses GTM Data Source ARU Address ARU_ACCESS...

  • Page 674: Aru Port Partitioning

    AURIX™ TC37x Generic Timer Module (GTM) 26.4.2 ARU Port Partitioning All GTM sub-modules which are reading from ARU can be connected to one of two ARU read ports. Therefore, it can be read from two different ARU addresses in parallel. Table 243 GTM ARU Partitioning Modules ARU-0 port...
  • Page 675 AURIX™ TC37x Generic Timer Module (GTM) Table 244 GTM Read IDs for TC37x (cont’d) ARU read ARU0 ARU1 GTM read ARU0 ARU1 ID (dec) ID (dec) BRC channel 3 DPLL action 3 ATOM4 channel 7 ATOM3 channel 3 PSM0 channel 3 BRC channel 4 DPLL action 4 ATOM3 channel 4...
  • Page 676 AURIX™ TC37x Generic Timer Module (GTM) Table 244 GTM Read IDs for TC37x (cont’d) ARU read ARU0 ARU1 GTM read ARU0 ARU1 ID (dec) ID (dec) MCS2 channel 5 ATOM1 channel 5 ATOM2 channel 2 DPLL action 22 MCS2 channel 6 ATOM1 channel 6 ATOM2 channel 3 DPLL action 23...

  • Page 677: Revision History

    AURIX™ TC37x Generic Timer Module (GTM) 26.5 Revision History Table 245 Revision History BBBBBBB Reference Change to Previous Version Comment V2.2.10 Page 293 Added tables on ARU Write Addresses, ARU Port Partitioning, and ARU Read ID Corrected tables 1 and 2 Page 2 Corrected block diagram and added connection diagrams and register Page...
  • Page 678 AURIX™ TC37x Generic Timer Module (GTM) (cont’d) Table 245 Revision History BBBBBBB Reference Change to Previous Version Comment DTMAUXINSEL: Corrected. Non existing sideband signals and pins are out of this list. CANOUTSEL corrected to be matching with design. V2.2.19 CCMi_CFG registers completely listed CMU_CLK_z_CTRL registers completely listed V2.2.20 Changes have no impact on this document.

  • Page 679: Capture/Compare Unit 6 (Ccu6)

    AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Capture/Compare Unit 6 (CCU6) This chapter describes the specific properties of the product TC37x, which is a member of the product family TC3XX. The functionality of the CCU6 is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.
  • Page 680 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 247 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_T12PR Timer 12 Period Register 0024 U,SV U,SV,P Application Reset Family Spec CCU60_T12DTC Dead-Time Control Register...
  • Page 681 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 247 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_MODCTR Modulation Control Register 0080 U,SV U,SV,P Application Reset Family Spec CCU60_TRPCTR Trap Control Register 0084...
  • Page 682 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 247 Register Overview - CCU60 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU60_KRSTCLR Kernel Reset Status Clear 00EC U,SV SV,E,P Application Register Reset Family Spec CCU60_KRST1...
  • Page 683 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 248 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_T12DTC Dead-Time Control Register 0028 U,SV U,SV,P Application for Timer12 Reset Family Spec CCU61_CC6xR...
  • Page 684 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 248 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_TRPCTR Trap Control Register 0084 U,SV U,SV,P Application Reset Family Spec CCU61_PSLR Passive State Level Register 0088 U,SV...

  • Page 685: Tc37X Specific Registers

    AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 248 Register Overview - CCU61 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write CCU61_KRST1 Kernel Reset Register 1 00F0 U,SV SV,E,P Application Reset Family Spec CCU61_KRST0 Kernel Reset Register 0...
  • Page 686 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 249 Connections of CCU60 (cont’d) Interface Signals connects Description CCU60:CC61INA from P02.2:IN T12 capture input 61 CCU60:CC62INA from P02.4:IN T12 capture input 62 CCU60:CC60INB from P00.1:IN T12 capture input 60 CCU60:CC61INB from P00.3:IN T12 capture input 61 CCU60:CC62INB from P00.5:IN...
  • Page 687 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 249 Connections of CCU60 (cont’d) Interface Signals connects Description CCU60:COUT62 IOM:MON1(5) T12 PWM channel 62 IOM:REF1(1) P02.5:ALT(7) P11.3:ALT(7) P14.0:ALT(7) P33.15:ALT(7) CCU60:COUT63 IOM:MON1(6) T13 PWM channel 63 IOM:REF1(0) P00.0:ALT(7) P11.2:ALT(7) P14.1:ALT(7) P32.4:ALT(7) P34.1:ALT(7) PMS:dcdc_sync_ccu6 CCU60:CTRAPA from P00.11:IN Trap input capture...
  • Page 688 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 249 Connections of CCU60 (cont’d) Interface Signals connects Description CCU60:T13HRD from GTM:CCU6_TRIG(1) External timer start 13 CCU60:T12HRE from P00.0:IN External timer start 12 CCU60:T12HRF from GPT120:T6OFL External timer start 12 CCU60:T13HRF from GPT120:T6OFL External timer start 13 CCU60:T12HRG from CCU61:SR(2)
  • Page 689 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 250 Connections of CCU61 Interface Signals connects Description CCU61:CC60 IOM:MON1(8) T12 PWM channel 60 IOM:REF1(13) P00.1:ALT(7) P00.7:ALT(7) P20.8:ALT(7) P33.13:ALT(7) CCU61:CC61 IOM:MON1(9) T12 PWM channel 61 IOM:REF1(12) P00.3:ALT(7) P00.8:ALT(7) P20.9:ALT(7) P33.11:ALT(7) CCU61:CC62 IOM:MON1(10) T12 PWM channel 62 IOM:REF1(11) P00.5:ALT(7) P00.9:ALT(7)
  • Page 690 AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 250 Connections of CCU61 (cont’d) Interface Signals connects Description CCU61:CCPOS0C from P33.7:IN Hall capture input 0 CCU61:CCPOS1C from P33.6:IN Hall capture input 1 CCU61:CCPOS2C from P33.5:IN Hall capture input 2 CCU61:CCPOS0D from P40.5:IN Hall capture input 0 CCU61:CCPOS1D from P40.7:IN...

  • Page 691: Revision History

    AURIX™ TC37x Capture/Compare Unit 6 (CCU6) Table 250 Connections of CCU61 (cont’d) Interface Signals connects Description CCU61:SR(3) EVADC:G0REQTRB Service request EVADC:G1REQTRB EVADC:G2REQTRB EVADC:G3REQTRB EVADC:G8REQTRB EVADC:G9REQTRB EVADC:G10REQTRB EVADC:G11REQTRB CCU61:T12HRA from SCU:scu_cctrig0 External timer start 12 CCU61:T13HRA from SCU:scu_cctrig0 External timer start 13 CCU61:T12HRB from P02.6:IN External timer start 12...

  • Page 692: General Purpose Timer Unit (Gpt12)

    AURIX™ TC37x General Purpose Timer Unit (GPT12) General Purpose Timer Unit (GPT12) This chapter describes the specific properties of the product TC37x, which is a member of the product family TC3XX. The functionality of the GPT12 is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 693: Connectivity

    AURIX™ TC37x General Purpose Timer Unit (GPT12) 28.3 Connectivity Table 253 Connections of GPT120 Interface Signals connects Description GPT120:CAPINA from P13.2:IN Trigger input to capture value of timer T5 into CAPREL register GPT120:CAPINB from SCU:E_PDOUT(6) Trigger input to capture value of timer T5 into CAPREL register GPT120:T2EUDA from P00.8:IN...

  • Page 694: Revision History

    AURIX™ TC37x General Purpose Timer Unit (GPT12) Table 253 Connections of GPT120 (cont’d) Interface Signals connects Description GPT120:T2_INT INT:gpt120.T2_INT GPT120 T2 Overflow/Underflow Service Request GPT120:T3_INT INT:gpt120.T3_INT GPT120 T3 Overflow/Underflow Service Request GPT120:T4_INT INT:gpt120.T4_INT GPT120 T4 Overflow/Underflow Service Request GPT120:T5_INT INT:gpt120.T5_INT GPT120 T5 Overflow/Underflow Service Request GPT120:T6_INT...

  • Page 695: Converter Control Block (Convctrl)

    AURIX™ TC37x Converter Control Block (CONVCTRL) Converter Control Block (CONVCTRL) This chapter describes the specific properties of the product TC37x, which is a member of the product family TC3xx. The functionality of the CONVCTRL is described in the TC3xx family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 696: Connectivity

    AURIX™ TC37x Converter Control Block (CONVCTRL) 29.4 Connectivity The CONVCTRL is connected to its environment through a number of input and output signals. Table 257 Digital Connections for Product TC37x Signal Dir. Source/Destin. Description General PHSYNC EVADC, EDSADC Synchronization signal for analog clocks CC_ALARM Alarm signal from safety logic Table 258 List of CONVERTER Interface Signals...

  • Page 697: Enhanced Versatile Analog-To-Digital Converter (Evadc)

    AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Enhanced Versatile Analog-to-Digital Converter (EVADC) This chapter describes the specific properties of the product TC37x, which is a member of the product family TC3XX. The functionality of the EVADC is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.

  • Page 698: Tc37X Specific Register Set

    AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 261 Synchronization Groups (cont’d) ADC Kernel Synchr. Master selected by control input CIx Group G2 (Prim.) G3 (Prim.) G8 (Sec.) G9 (Sec.) G10 (Sec.) G11 (Sec.) 1) The control input is selected by bitfield STSEL in register GxSYNCTR. Select the corresponding ready inputs accordingly by bits EVALRx.

  • Page 699: Connectivity

    AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.3 Connectivity The EVADC is connected to its environment through a number of analog input signals and also digital input and output signals. These connections establish communication with other peripherals, with the system blocks, and with external components.
  • Page 700 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 265 Analog Input Connections for Product TC37x (cont’d) Signal Source Overlay Description G0CH6 (FixRef) G11CH2 analog input channel 6 of group 0 G0CH7 (PDD, FixRef) G11CH3 analog input channel 7 of group 0 Analog Inputs for Group 1 (Primary) G1CH0 (AltRef) G11CH4...
  • Page 701 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 265 Analog Input Connections for Product TC37x (cont’d) Signal Source Overlay Description G8CH8 AN40 analog input channel 8 of group 8 G8CH9 AN41 analog input channel 9 of group 8 G8CH10 AN42 analog input channel 10 of group 8 G8CH11 AN43...
  • Page 702 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 265 Analog Input Connections for Product TC37x (cont’d) Signal Source Overlay Description G10CH12 analog input channel 12 of group 10 G10CH13 analog input channel 13 of group 10 G10CH14 analog input channel 14 of group 10 G10CH15 Selected supervision signal from the EDSADC...
  • Page 703 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.3.2 Digital Module Connections The EVADC module accepts a number of digital input signals and generates a number of output signals. This section summarizes the connection of these signals to other on-chip modules or to external resources via port pins.
  • Page 704 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 266 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description GyREQTRH eru_iout_y [0111 ] ERU interrupt output y (y = 0 - 7) G8REQTRH eru_iout_0 [0111 ] ERU interrupt output 0 G9REQTRH eru_iout_1 [0111...
  • Page 705 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 266 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description GxWR Fast Compare channel, Write signal for GxDATA RIF, GTM EMUX00 P02.6, P33.3 Control of external analog multiplexer interface 0 EMUX01 P02.7, P33.2 EMUX02 P02.8, P33.1...
  • Page 706 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 266 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description FC0BFDAT GTM_MCSTRIG0 Boundary flag (FC channel 0) alternate data FC1BFLOUT P10.1, P33.6 Boundary flag output of FC channel 1 FC1BFL GTM_MCSSTAT1, Boundary flag level of FC channel 1 GTM_tim_0_muxin_1_0 GTM_tim_1_muxin_1_0...
  • Page 707 AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) Table 266 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description C0SR3 ICU, GTM_TIM0_CH6, Service request 3 of common block 0 GTM_TIM1_CH2, GTM_TIM2_CH6 C1SR0 ICU, GTM_TIM0_CH1, Service request 0 of common block 1 GTM_TIM1_CH5, GTM_TIM2_CH1 C1SR1...

  • Page 708: Revision History

    AURIX™ TC37x Enhanced Versatile Analog-to-Digital Converter (EVADC) 30.4 Revision History This is a summary of the modifications that have been applied to this chapter. Table 267 Revision History Reference Change to Previous Version Comment V3.0.0 Page 3 Clarify functionality of channel CH29 (see end of table) V3.0.1 –...

  • Page 709: Enhanced Delta-Sigma Analog-To-Digital Converter (Edsadc)

    AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) This chapter describes the specific properties of the product TC37x, which is a member of the product family TC3XX. The functionality of the EDSADC is described in the TC3XX family documentation. The complete product description consists of the family documentation and this product-specific appendix.
  • Page 710 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) 31.3 Connectivity The EDSADC is connected to its environment through a number of analog input signals and also digital input and output signals. These connections establish communication with other peripherals, with the system blocks, and with external components.
  • Page 711 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 271 Analog Input Connections for Product TC37x (cont’d) Signal Source Overlay Description EDS2NB AN25 G3CH1 (MD) / ] negative analog input of channel 2, pin B SENT1A EDS3PA G0CH0 (AltRef) ] positive analog input of channel 3, pin A EDS3NA G0CH1 (MD) ] negative analog input of channel 3, pin A...
  • Page 712 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) 31.3.2 Digital Module Connections The EDSADC module accepts a number of digital input signals and generates a number of output signals. This section summarizes the connection of these signals to other on-chip modules or to external resources via port pins.
  • Page 713 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 272 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description DATA0[16:0] Result values of channel 0 Write signal for DATA0 Channel 1 DSDIN1A P00.10 [00X ] Data bitstream channel 1 input A DSDIN1B P33.4 [01X...
  • Page 714 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 272 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description DSDIN2D [11X ] Data bitstream channel 2 input D DSCIN2A P00.5 [011 ] Modulator clock channel 2 input A DSCIN2B P33.1 [100 ] Modulator clock channel 2 input B DSCIN2C...
  • Page 715 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 272 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description ITR3B GTM:DSADC_TRIG1(3) [0001 ] GTM DSADC trigger 1 ITR3C GTM:ADC_TRIG0(3) [0010 ] GTM ADC trigger 0 ITR3D GTM:ADC_TRIG1(3) [0011 ] GTM ADC trigger 1 ITR3E P02.8 [0100...
  • Page 716 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 272 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description ITR4G SCU_PDOUT4 [0110 ] ERU pattern detection output 4 ITR4H [0111 ] Trigger/gate, channel 4, input H ITR4I [1000 ] Trigger/gate, channel 4, input I ITR4J [1001 ] Trigger/gate, channel 4, input J...

  • Page 717: Revision History

    AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 272 Digital Connections for Product TC37x (cont’d) Signal Dir. Source/Destin. Description ITR5M GTM:DSADC_TRIG2(5) [1100 ] GTM DSADC trigger 2 ITR5N GTM:DSADC_TRIG3(5) [1101 ] GTM DSADC trigger 3 ITR5O [1110 ] Trigger/gate, channel 5, input O ITR5P [1111 ] Trigger/gate, channel 5, input P...
  • Page 718 AURIX™ TC37x Enhanced Delta-Sigma Analog-to-Digital Converter (EDSADC) Table 273 Revision History (cont’d) Reference Change to Previous Version Comment V3.0.6 – No functional change. User’s Manual 31-10 V2.0.0 EDSADCV3.0.6 2021-02 OPEN MARKET VERSION...

  • Page 719: Inter-Integrated Circuit (I2C)

    AURIX™ TC37x Inter-Integrated Circuit (I2C) Inter-Integrated Circuit (I2C) This chapter describes the Inter-Integrated Circuit (short I2C) Module of the TC37x. 32.1 TC37x Specific IP Configuration See features in family spec. No product specific configuration for I2C 32.2 TC37x Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space...

  • Page 720: Revision History

    AURIX™ TC37x Inter-Integrated Circuit (I2C) 32.5 Revision History Table 276 Revision History Reference Change to Previous Version Comment V2.3.4 Page 1 No functional changes. Formal changes in Connectivity tables. V2.3.5 – No functional changes. V2.3.6 – No functional changes. User’s Manual 32-2 V2.0.0 I2CV2.3.6...

  • Page 721: High Speed Serial Link (Hssl)

    AURIX™ TC37x High Speed Serial Link (HSSL) High Speed Serial Link (HSSL) This section provides information regarding the implementation of the module HSSL specifically for device TC37x. 33.1 TC37x Specific IP Configuration See features in family spec. No product specific configuration for HSSL 33.2 TC37x Specific Register Set 33.2.1...

  • Page 722: Revision History

    AURIX™ TC37x High Speed Serial Link (HSSL) 33.5 Revision History Table 279 Revision History Reference Change to Previous Version Comment V3.0.16 – No changes. V3.0.17 – No functional changes. V3.0.18 – No changes. V3.0.19 – No changes. User’s Manual 33-2 V2.0.0 HSSLV3.0.19 2021-02...

  • Page 723: High Speed Communication Tunnel (Hsct)

    AURIX™ TC37x 33.6 High Speed Communication Tunnel (HSCT) This section provides information regarding the implementation of the module HSCT specifically for device TC37x. 33.6.1 TC37x Specific IP Configuration See features in family spec. No product specific configuration for HSCT No differences between the instances of the HSCT in TC37x. 33.6.2 TC37x Specific Register Set There are no device specific registers in TC37x.

  • Page 724: Revision History

    AURIX™ TC37x 33.6.5 Revision History Table 282 Revision History Reference Change to Previous Version Comment V2.3.11 Page 4 Previous versions removed from revision history. none Page 3 Typo corrected. none V2.3.12 Formal changes in connections table, no functional changes. Page 3 V2.3.13 –...

  • Page 725: Asynchronous Serial Interface (Asclin)

    AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Asynchronous Serial Interface (ASCLIN) Text with reference to family spec. 34.1 TC37x Specific IP Configuration No product specific configuration for ASCLIN User’s Manual 34-1 V2.0.0 ASCLINV3.2.8 2021-02 OPEN MARKET VERSION...

  • Page 726: Tc37X Specific Register Set

    AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) 34.2 TC37x Specific Register Set Register Address Space Table Table 283 Register Address Space - ASCLIN Module Base Address End Address Note ASCLIN0 F0000600 F00006FF FPI slave interface ASCLIN1 F0000700 F00007FF FPI slave interface ASCLIN2 F0000800 F00008FF...
  • Page 727 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN6_CLC Clock Control Register Family Spec ASCLIN7_CLC Clock Control Register Family Spec ASCLIN8_CLC Clock Control Register Family Spec ASCLIN9_CLC...
  • Page 728 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN8_IOCR Input and Output Control Register Family Spec ASCLIN9_IOCR Input and Output Control Register Family Spec ASCLIN10_IOCR Input and Output Control Register Family...
  • Page 729 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN10_ID Module Identification Register Family Spec ASCLIN11_ID Module Identification Register Family Spec ASCLIN0_TXFIFOCON TX FIFO Configuration Register Family Spec ASCLIN1_TXFIFOCON TX FIFO Configuration Register...
  • Page 730 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_RXFIFOCON RX FIFO Configuration Register Family Spec ASCLIN1_RXFIFOCON RX FIFO Configuration Register Family Spec ASCLIN2_RXFIFOCON RX FIFO Configuration Register Family Spec ASCLIN3_RXFIFOCON RX FIFO Configuration Register...
  • Page 731 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_BITCON Bit Configuration Register Family Spec ASCLIN3_BITCON Bit Configuration Register Family Spec ASCLIN4_BITCON Bit Configuration Register Family Spec ASCLIN5_BITCON...
  • Page 732 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_FRAMECON Frame Control Register Family Spec ASCLIN5_FRAMECON Frame Control Register Family Spec ASCLIN6_FRAMECON Frame Control Register Family Spec ASCLIN7_FRAMECON Frame Control Register...
  • Page 733 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN6_DATCON Data Configuration Register Family Spec ASCLIN7_DATCON Data Configuration Register Family Spec ASCLIN8_DATCON Data Configuration Register Family Spec ASCLIN9_DATCON...
  • Page 734 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN8_BRG Baud Rate Generation Register Family Spec ASCLIN9_BRG Baud Rate Generation Register Family Spec ASCLIN10_BRG Baud Rate Generation Register Family Spec ASCLIN11_BRG...
  • Page 735 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN10_BRD Baud Rate Detection Register Family Spec ASCLIN11_BRD Baud Rate Detection Register Family Spec ASCLIN0_LINCON LIN Control Register Family Spec ASCLIN1_LINCON...
  • Page 736 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_LINBTIMER LIN Break Timer Register Family Spec ASCLIN1_LINBTIMER LIN Break Timer Register Family Spec ASCLIN2_LINBTIMER LIN Break Timer Register Family Spec ASCLIN3_LINBTIMER LIN Break Timer Register...
  • Page 737 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_LINHTIMER LIN Header Timer Register Family Spec ASCLIN3_LINHTIMER LIN Header Timer Register Family Spec ASCLIN4_LINHTIMER LIN Header Timer Register Family Spec ASCLIN5_LINHTIMER LIN Header Timer Register...
  • Page 738 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_FLAGS Flags Register Family Spec ASCLIN5_FLAGS Flags Register Family Spec ASCLIN6_FLAGS Flags Register Family Spec ASCLIN7_FLAGS Flags Register Family Spec...
  • Page 739 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN6_FLAGSSET Flags Set Register Family Spec ASCLIN7_FLAGSSET Flags Set Register Family Spec ASCLIN8_FLAGSSET Flags Set Register Family Spec ASCLIN9_FLAGSSET...
  • Page 740 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN8_FLAGSCLEA Flags Clear Register Family Spec ASCLIN9_FLAGSCLEA Flags Clear Register Family Spec ASCLIN10_FLAGSCLE Flags Clear Register Family Spec ASCLIN11_FLAGSCLE...
  • Page 741 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN10_FLAGSENA Flags Enable Register Family Spec ASCLIN11_FLAGSENA Flags Enable Register Family Spec ASCLIN0_TXDATA Transmit Data Register Family Spec ASCLIN1_TXDATA...
  • Page 742 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_RXDATA Receive Data Register Family Spec ASCLIN1_RXDATA Receive Data Register Family Spec ASCLIN2_RXDATA Receive Data Register Family Spec ASCLIN3_RXDATA...
  • Page 743 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_CSR Clock Selection Register Family Spec ASCLIN3_CSR Clock Selection Register Family Spec ASCLIN4_CSR Clock Selection Register Family Spec ASCLIN5_CSR...
  • Page 744 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN4_RXDATAD Receive Data Debug Register Family Spec ASCLIN5_RXDATAD Receive Data Debug Register Family Spec ASCLIN6_RXDATAD Receive Data Debug Register Family Spec ASCLIN7_RXDATAD...
  • Page 745 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN6_OCS OCDS Control and Status Family Spec ASCLIN7_OCS OCDS Control and Status Family Spec ASCLIN8_OCS OCDS Control and Status Family Spec ASCLIN9_OCS...
  • Page 746 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN8_KRSTCLR Kernel Reset Status Clear Register Family Spec ASCLIN9_KRSTCLR Kernel Reset Status Clear Register Family Spec ASCLIN10_KRSTCLR Kernel Reset Status Clear Register Family...
  • Page 747 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN10_KRST1 Kernel Reset Register 1 Family Spec ASCLIN11_KRST1 Kernel Reset Register 1 Family Spec ASCLIN0_KRST0 Kernel Reset Register 0 Family Spec ASCLIN1_KRST0...
  • Page 748 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN0_ACCEN1 Access Enable Register 1 Family Spec ASCLIN1_ACCEN1 Access Enable Register 1 Family Spec ASCLIN2_ACCEN1 Access Enable Register 1 Family Spec ASCLIN3_ACCEN1...

  • Page 749: Tc37X Specific Registers

    AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 284 Register Overview - ASCLIN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ASCLIN2_ACCEN0 Access Enable Register 0 Family Spec ASCLIN3_ACCEN0 Access Enable Register 0 Family Spec ASCLIN4_ACCEN0 Access Enable Register 0 Family Spec ASCLIN5_ACCEN0...
  • Page 750 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 285 Connections of ASCLIN0 (cont’d) Interface Signals connects Description ASCLIN0:ARTS P14.7:ALT(2) Ready to send output ASCLIN0:ACTSD ASCLIN0:ARXA from P14.1:IN Receive input ASCLIN0:ARXB from P15.3:IN Receive input ASCLIN0:ARXD from P33.10:IN Receive input ASCLIN0:ASCLK P14.0:ALT(6) Shift clock output P15.2:ALT(6) ASCLIN0:ATX...
  • Page 751 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 286 Connections of ASCLIN1 (cont’d) Interface Signals connects Description ASCLIN1:ASLSO P14.3:ALT(4) Slave select signal output P20.8:ALT(2) P33.10:ALT(4) ASCLIN1:ATX IOM:MON2(13) Transmit output IOM:REF2(13) P02.2:ALT(2) P11.12:ALT(2) P14.10:ALT(4) P15.0:ALT(2) P15.1:ALT(2) P15.4:ALT(2) P15.5:ALT(2) P20.10:ALT(2) P33.12:ALT(2) P33.13:ALT(2) ASCLIN1:sleep_n from SCU:scu_syst_sleep_n Negative turn-off request ASCLIN1:TX_INT...
  • Page 752 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 287 Connections of ASCLIN2 (cont’d) Interface Signals connects Description ASCLIN2:ASCLK P02.4:ALT(2) Shift clock output P10.6:ALT(2) P14.2:ALT(6) P33.7:ALT(2) P33.9:ALT(4) ASCLIN2:ASLSO P02.3:ALT(2) Slave select signal output P10.5:ALT(6) P33.6:ALT(2) ASCLIN2:ATX IOM:MON2(14) Transmit output IOM:REF2(14) P02.0:ALT(2) P02.9:ALT(2) P10.5:ALT(2) P14.2:ALT(2) P14.3:ALT(2)
  • Page 753 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 288 Connections of ASCLIN3 (cont’d) Interface Signals connects Description ASCLIN3:ASCLK P00.0:ALT(2) Shift clock output P00.2:ALT(2) P11.1:ALT(2) P11.4:ALT(2) P15.6:ALT(6) P15.8:ALT(6) P20.0:ALT(3) P21.5:ALT(2) P21.7:ALT(3) P32.3:ALT(4) P33.2:ALT(2) ASCLIN3:ASLSO P00.3:ALT(2) Slave select signal output P12.1:ALT(2) P14.3:ALT(5) P21.2:ALT(2) P21.6:ALT(2) P33.1:ALT(2) ASCLIN3:ATX...
  • Page 754 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 289 Connections of ASCLIN4 Interface Signals connects Description ASCLIN4:ACTSD from ASCLIN4:ARTS Clear to send input ASCLIN4:ARTS ASCLIN4:ACTSD Ready to send output ASCLIN4:ARXA from P00.12:IN Receive input ASCLIN4:ARXB from P34.2:IN Receive input ASCLIN4:ARXC from P22.6:IN Receive input ASCLIN4:ARXD from P22.9:IN...
  • Page 755 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 290 Connections of ASCLIN5 (cont’d) Interface Signals connects Description ASCLIN5:TX_INT INT:asclin5.TX_INT ASCLIN Transmit Service Request ASCLIN5:RX_INT INT:asclin5.RX_INT ASCLIN Receive Service Request ASCLIN5:ERR_INT INT:asclin5.ERR_INT ASCLIN Error Service Request Table 291 Connections of ASCLIN6 Interface Signals connects Description ASCLIN6:ACTSD...
  • Page 756 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 293 Connections of ASCLIN8 Interface Signals connects Description ASCLIN8:ACTSD from ASCLIN8:ARTS Clear to send input ASCLIN8:ARTS ASCLIN8:ACTSD Ready to send output ASCLIN8:ARXA from P02.9:IN Receive input ASCLIN8:ARXB from P02.10:IN Receive input ASCLIN8:ARXC from P33.1:IN Receive input ASCLIN8:ARXD from P33.6:IN...
  • Page 757 AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) Table 295 Connections of ASCLIN10 Interface Signals connects Description ASCLIN10:ACTSD from ASCLIN10:ARTS Clear to send input ASCLIN10:ARTS ASCLIN10:ACTSD Ready to send output ASCLIN10:ARXA from P00.4:IN Receive input ASCLIN10:ARXB from P00.8:IN Receive input ASCLIN10:ARXC from P13.0:IN Receive input ASCLIN10:ARXD from P13.1:IN...

  • Page 758: Revision History

    AURIX™ TC37x Asynchronous Serial Interface (ASCLIN) 34.5 Revision History Table 297 Revision History Reference Change to Previous Version Comment V3.2.6 Page 2 Register tables updated. No functional change in connectivity tables. V3.2.7 – No functional changes. V3.2.8 – No functional changes. User’s Manual 34-34 V2.0.0...

  • Page 759: Queued Synchronous Peripheral Interface (Qspi)

    AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Queued Synchronous Peripheral Interface (QSPI) 35.1 TC37x Specific IP Configuration Table 298 TC37x specific configuration of QSPI Parameter QSPI0 QSPI1 QSPI2 QSPI3 QSPI4 QSPI module has HSIC User’s Manual 35-1 V2.0.0 QSPIV3.0.20 2021-02 OPEN MARKET VERSION...

  • Page 760: Tc37X Specific Register Set

    AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) 35.2 TC37x Specific Register Set Register Address Space Table Table 299 Register Address Space - QSPI Module Base Address End Address Note QSPI0 F0001C00 F0001CFF Register block QSPI0 QSPI1 F0001D00 F0001DFF Register block QSPI1 QSPI2 F0001E00 F0001EFF...
  • Page 761 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 300 Register Overview - QSPI0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI0_SSOC Slave Select Output Control U,SV SV,P Application Register Reset Family Spec QSPI0_FLAGSCLE...
  • Page 762 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 300 Register Overview - QSPI0 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI0_ACCEN1 Access Enable Register 1 U,SV SV,SE Application Reset Family Spec QSPI0_ACCEN0 Access Enable Register 0...
  • Page 763 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 301 Register Overview - QSPI1 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI1_XXLCON Extra Large Data U,SV U,SV,P Application Configuration Register Reset Family Spec QSPI1_MIXENTRY MIX_ENTRY Register...
  • Page 764 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 302 Register Overview - QSPI2 (ascending Offset Address) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI2_CLC Clock Control Register U,SV SV,E,P Application Reset Family Spec QSPI2_PISEL Port Input Select Register U,SV SV,P...
  • Page 765 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 302 Register Overview - QSPI2 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI2_DATAENT DATA_ENTRY Register x U,SV U,SV,P Application Reset Family (x=0-7) Spec QSPI2_RXEXIT RX_EXIT Register...
  • Page 766 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 303 Register Overview - QSPI3 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI3_ID Module Identification U,SV Application Register Reset Family Spec QSPI3_GLOBALC Global Configuration U,SV SV,P...
  • Page 767 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 303 Register Overview - QSPI3 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI3_RXEXITD RX_EXIT Debug Register U,SV Application Reset Family Spec QSPI3_MC Move Counter Register U,SV U,SV,P...
  • Page 768 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 304 Register Overview - QSPI4 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI4_GLOBALC Global Configuration U,SV SV,P Application Register 1 Reset Family Spec QSPI4_BACON Basic Configuration Register 018...
  • Page 769 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 304 Register Overview - QSPI4 (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write QSPI4_MCCON Move Counter control U,SV U,SV,P Application Register Reset Family Spec QSPI4_OCS OCDS Control and Status...

  • Page 770: Tc37X Specific Registers

    AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) 35.3 TC37x Specific Registers 35.3.1 Register block QSPI Port Input Select Register The PISEL register controls the input signal selection of the SSC module. QSPI0_PISEL Port Input Select Register (004 Application Reset Value: 0000 0000 SLSIS SCIS SRIS...
  • Page 771 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description 14:12 SLSIS Slave Mode Slave Select Input Selection The SLSIS must be programmed properly before the slave mode is set with GLOBALCON.MODE and the module is set to RUN mode. The following signal sources are available in this product (if supported by the package!) no input...
  • Page 772 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description 10:8 SCIS Slave Mode Clock Input Select SCIS selects one out of eight module kernel SCLK input lines that is used as clock input line in slave mode. Note that not all inputs are used in every device of the family.
  • Page 773 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description SRIS Slave Mode Receive Input Select SRIS selects one out of eight MTSR receive input lines, used in Slave Mode. Note that not all inputs are used in every device of the family. Selecting an unused input returns a continuous low value.
  • Page 774 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description MRIS Master Mode Receive Input Select MRIS selects one out of eight MRST receive input lines, used in Master Mode. Note that not all inputs are used in every device of the family. Selecting an unused input returns a continuous low value.
  • Page 775 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) QSPI4_PISEL Port Input Select Register (004 Application Reset Value: 0000 0000 SLSIS SCIS SRIS MRIS Field Bits Type Description MRIS Master Mode Receive Input Select MRIS selects one out of eight MRST receive input lines, used in Master Mode.

  • Page 776: Connectivity

    AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Field Bits Type Description Reserved Read as 0; should be written with 0. 31:15 35.4 Connectivity The tables below list all the connections of QSPI instances. Table 305 Connections of QSPI0 Interface Signals connects Description QSPI0:MRST...
  • Page 777 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 305 Connections of QSPI0 (cont’d) Interface Signals connects Description QSPI0:SLSO(6) P20.10:ALT(3) Master slave select output QSPI0:SLSO(7) P33.5:ALT(2) Master slave select output QSPI0:SLSO(8) P20.6:ALT(3) Master slave select output QSPI0:SLSO(9) P20.3:ALT(3) Master slave select output QSPI0:SLSO(10) P22.11:ALT(4) Master slave select output...
  • Page 778 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 306 Connections of QSPI1 (cont’d) Interface Signals connects Description QSPI1:SLSO(2) P20.13:ALT(4) Master slave select output QSPI1:SLSO(3) P11.10:ALT(4) Master slave select output QSPI1:SLSO(4) P11.11:ALT(4) Master slave select output QSPI1:SLSO(5) P11.2:ALT(4) Master slave select output QSPI1:SLSO(6) P33.10:ALT(2) Master slave select output...
  • Page 779 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 307 Connections of QSPI2 (cont’d) Interface Signals connects Description QSPI2:MTSRN P13.2:ALT(3) Master SPI data output (LVDS N line) QSPI2:SCLK P13.1:ALT(3) Master SPI clock output P15.3:ALT(3) P15.6:ALT(5) P15.8:ALT(3) P33.1:ALT(3) P33.14:ALT(3) QSPI2:SCLKA from P15.3:IN Slave SPI clock inputs QSPI2:SCLKB from P15.8:IN...
  • Page 780 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 308 Connections of QSPI3 Interface Signals connects Description QSPI3:MRST IOM:MON2(3) Slave SPI data output IOM:REF2(3) P01.5:ALT(4) P02.5:ALT(3) P10.7:ALT(3) QSPI3:MRSTA from P02.5:IN Master SPI data input QSPI3:MRSTB from P10.7:IN Master SPI data input QSPI3:MRSTC from P01.5:IN Master SPI data input...
  • Page 781 AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 308 Connections of QSPI3 (cont’d) Interface Signals connects Description QSPI3:ERR_INT INT:qspi3.ERR_INT QSPI Error Service Request QSPI3:PT_INT INT:qspi3.PT_INT QSPI Phase Transition Service Request QSPI3:U_INT INT:qspi3.U_INT QSPI User Defined Service Request QSPI3:HC_INT INT:qspi3.HC_INT QSPI High Speed Capture Service Request Table 309 Connections of QSPI4 Interface Signals connects...

  • Page 782: Revision History

    AURIX™ TC37x Queued Synchronous Peripheral Interface (QSPI) Table 309 Connections of QSPI4 (cont’d) Interface Signals connects Description QSPI4:SLSO(6) P23.1:ALT(3) Master slave select output QSPI4:SLSO(7) P02.1:ALT(2) Master slave select output P33.7:ALT(3) QSPI4:TX_INT INT:qspi4.TX_INT QSPI Transmit Service Request QSPI4:RX_INT INT:qspi4.RX_INT QSPI Receive Service Request QSPI4:ERR_INT INT:qspi4.ERR_INT QSPI Error Service Request...

  • Page 783: Micro Second Channel (Msc)

    AURIX™ TC37x Micro Second Channel (MSC) Micro Second Channel (MSC) This chapter describes the Micro Second Channel (MSC) Module of the TC37x. 36.1 TC37x Specific IP Configuration See features in family spec. No product specific configuration for MSC 36.2 TC37x Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space...
  • Page 784 AURIX™ TC37x Micro Second Channel (MSC) Connections of MSC0 (cont’d) Table 312 Interface Signals connects Description MSC0:FCLN P13.0:ALT(5) Shift-clock inverted part of the differential signal MSC0:FCLP SCU:E_REQ0(3) Shift-clock direct part of the differential signal P11.6:ALT(5) P13.1:ALT(5) P13.2:ALT(4) MSC0:INJ0 from P00.0:IN Injection signal from port MSC0:INJ1 from P10.5:IN...

  • Page 785: Revision History

    AURIX™ TC37x Micro Second Channel (MSC) Connections of MSC1 (cont’d) Table 313 Interface Signals connects Description MSC1:SDI(0) from P23.1:IN Upstream asynchronous input signal MSC1:SDI(1) from P02.3:IN Upstream asynchronous input signal MSC1:SDI(2) from P32.4:IN Upstream asynchronous input signal MSC1:SON P22.2:ALT(5) Data output - inverted part of the differential signal MSC1:SOP P22.3:ALT(5)
  • Page 786 AURIX™ TC37x Single Edge Nibble Transmission (SENT) Single Edge Nibble Transmission (SENT) This document describes the SENT Interface specific appendix for the product TC37x. 37.1 TC37x Specific IP Configuration See features in family spec. Table 315 TC37x specific configuration of SENT Parameter SENT Number of SENT channels for this device...

  • Page 787: Interrupt And Dma Controller Service Requests

    AURIX™ TC37x Single Edge Nibble Transmission (SENT) 37.2 TC37x Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space Table. Table 316 Register Address Space - SENT Module Base Address End Address Note SENT...
  • Page 788 AURIX™ TC37x Single Edge Nibble Transmission (SENT) Connections of SENT (cont’d) Table 317 Interface Signals connects Description SENT:SENT10A from P40.10:IN Receive input channel 10 SENT:SENT11A from P40.11:IN Receive input channel 11 SENT:SENT12A from P40.12:IN Receive input channel 12 SENT:SENT13A from P40.13:IN Receive input channel 13 SENT:SENT14A from P40.14:IN...

  • Page 789: Revision History

    AURIX™ TC37x Single Edge Nibble Transmission (SENT) Connections of SENT (cont’d) Table 317 Interface Signals connects Description SENT:SPC(1) P02.7:ALT(6) Transmit output SENT:SPC(2) P00.3:ALT(6) Transmit output SENT:SPC(3) P00.4:ALT(6) Transmit output SENT:SPC(4) P00.5:ALT(6) Transmit output SENT:SPC(5) P00.6:ALT(6) Transmit output SENT:SPC(6) P00.7:ALT(6) Transmit output SENT:SPC(7) P00.8:ALT(6) Transmit output...

  • Page 790: Can Interface (Mcmcan)

    AURIX™ TC37x CAN Interface (MCMCAN) CAN Interface (MCMCAN) This section describes the MCMCAN Interface specific appendix for the product TC37x. 38.1 TC37x Specific IP Configuration Table 319 TC37x specific configuration of CAN Parameter CAN0 CAN1 1024 1024 Node size in byte Number of CAN Nodes Number of TTCAN Nodes 32768...

  • Page 791: Tc37X Specific Register Set

    AURIX™ TC37x CAN Interface (MCMCAN) 38.2 TC37x Specific Register Set Register Address Space Table Table 320 Register Address Space - CAN Module Base Address End Address Note CAN0 F0200000 F0208FFF Bus Interface CAN1 F0210000 F0218FFF Bus Interface Register Overview Table Table 321 Register Overview - CAN (ascending Offset Address) Short Name Long Name...
  • Page 792 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_ACCENCTR0 Access Enable Register Control 0 0080DC Family Spec CAN1_ACCENCTR0 Access Enable Register Control 0 0080DC Family Spec CAN0_OCS OCDS Control and Status...
  • Page 793 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_STARTADRi Start Address Node i 008108 +i*400 (i=0-3) Family Spec CAN1_STARTADRi Start Address Node i 008108 +i*400 (i=0-3) Family Spec...
  • Page 794 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_NTBTTRi Node i Timer B Transmit Trigger Register 008128 +i*400 (i=0-3) Family Spec CAN1_NTBTTRi Node i Timer B Transmit Trigger Register 008128 +i*400 (i=0-3)
  • Page 795 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_DBTPi Data Bit Timing & Prescaler Register i 00820C +i*40 (i=0-3) Family Spec CAN0_TESTi Test Register i 008210 +i*400 (i=0-3)
  • Page 796 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_TOCCi Timeout Counter Configuration i 008228 +i*400 (i=0-3) Family Spec CAN0_TOCVi Timeout Counter Value i 00822C +i*40 (i=0-3) Family Spec...
  • Page 797 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_GFCi Global Filter Configuration i 008280 +i*400 (i=0-3) Family Spec CAN0_SIDFCi Standard ID Filter Configuration i 008284 +i*400 (i=0-3) Family...
  • Page 798 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_RXF0Ci Rx FIFO 0 Configuration i 0082A0 +i*40 (i=0-3) Family Spec CAN0_RXF0Si Rx FIFO 0 Status i 0082A4 +i*40 (i=0-3)
  • Page 799 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_RXESCi Rx Buffer/FIFO Element Size Configuration i 0082BC +i*40 (i=0-3) Family Spec CAN0_TXBCi Tx Buffer Configuration i 0082C0 +i*40 (i=0-3)
  • Page 800 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN1_TXBTOi Tx Buffer Transmission Occurred i 0082D8 +i*40 (i=0-3) Family Spec CAN0_TXBCFi Tx Buffer Cancellation Finished i 0082DC +i*40 (i=0-3)
  • Page 801 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_TTRMCi TT Reference Message Configuration i 008304 (i=0) Family Spec CAN0_TTOCFi TT Operation Configuration i 008308 (i=0) Family Spec CAN0_TTMLMi...
  • Page 802 AURIX™ TC37x CAN Interface (MCMCAN) Table 321 Register Overview - CAN (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number CAN0_TTCPTi TT Capture Time i 00833C (i=0) Family Spec CAN0_TTCSMi TT Cycle Sync Mark i 008340 (i=0) Family Spec User’s Manual...

  • Page 803: Tc37X Specific Registers

    AURIX™ TC37x CAN Interface (MCMCAN) 38.3 TC37x Specific Registers 38.3.1 Bus Interface Module Control Register The Module Control Register MCR contains basic settings that determine the operation of the MCMCAN module. The write access to the lowest byte of the MCR register becomes only valid, if and only if, MCR.CCCE and MCR.CI are already set during write access.

  • Page 804: Connectivity

    AURIX™ TC37x CAN Interface (MCMCAN) Field Bits Type Description CLKSEL0 Clock Select 0 This bitfield is MCR.CI and MCR.CCCE protected. No clock supplied The asynchronous clock source is switched on The synchronous clock source is switched on Both clock sources are switched on CLKSEL1 Clock Select 1 This bitfield is MCR.CI and MCR.CCCE protected.
  • Page 805 AURIX™ TC37x CAN Interface (MCMCAN) Table 322 Connections of CAN0 Interface Signals connects Description CAN0:DSTDBG from DMU:SCU_ENTERED_DE Destructive Debug entered ST_DBG CAN0:DXSCLK TCU:dxs_clk DXS Clock, DAP module clock CAN0:ECTT(1) from P02.4:IN External CAN time trigger input CAN0:ECTT(2) from P02.5:IN External CAN time trigger input CAN0:ECTT(4:3) from SCU:E_IOUT(3:2) External CAN time trigger input...
  • Page 806 AURIX™ TC37x CAN Interface (MCMCAN) Table 323 Connections of CAN00 Interface Signals connects Description CAN00:RXDA from P02.1:IN CAN receive input node 0 CAN00:RXDB from P20.7:IN CAN receive input node 0 CAN00:RXDC from P12.0:IN CAN receive input node 0 CAN00:RXDD from P33.12:IN CAN receive input node 0 CAN00:RXDE from P33.7:IN...
  • Page 807 AURIX™ TC37x CAN Interface (MCMCAN) Table 325 Connections of CAN1 (cont’d) Interface Signals connects Description CAN1:STM1_SR1_INT from STM1:SR1_INT System Timer Service Request 1 CAN1:STM2_SR0_INT from STM2:SR0_INT System Timer Service Request 0 CAN1:STM2_SR1_INT from STM2:SR1_INT System Timer Service Request 1 CAN1:TRIG(3:0) from GTM:CAN1.TRIG(3:0) GTM timer output vector CAN1:INT(15:0)
  • Page 808 AURIX™ TC37x CAN Interface (MCMCAN) Table 328 Connections of CAN10 Interface Signals connects Description CAN10:RXDA from P00.1:IN CAN receive input node 0 CAN10:RXDB from P14.7:IN CAN receive input node 0 CAN10:RXDC from P23.0:IN CAN receive input node 0 CAN10:RXDD from P13.1:IN CAN receive input node 0 CAN10:TXD P00.0:ALT(5)

  • Page 809: Revision History

    AURIX™ TC37x CAN Interface (MCMCAN) Table 331 Connections of CAN13 (cont’d) Interface Signals connects Description CAN13:TXD P11.4:ALT(5) CAN transmit output node 3 P14.6:ALT(4) P22.4:ALT(6) P33.4:ALT(7) Note: For the connectivity of the MCMCAN module to the STM module, please refer to the User Manual, chapter MCMCAN User Interface under CAN Transmit Trigger Inputs section.

  • Page 810: Flexray™ Protocol Controller (E-Ray)

    AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) FlexRay™ Protocol Controller (E-Ray) Text with reference to family spec. 39.1 TC37x Specific IP Configuration No product specific configuration for ERAY User’s Manual 39-1 V2.0.0 E-RayV3.2.11 2021-02 OPEN MARKET VERSION...

  • Page 811: Tc37X Specific Register Set

    AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) 39.2 TC37x Specific Register Set Register Address Space Table Table 333 Register Address Space - ERAY Module Base Address End Address Note ERAY0 F001C000 F001CFFF FPI slave interface Register Overview Table Table 334 Register Overview - ERAY (ascending Offset Address) Short Name Long Name Offset...
  • Page 812 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_SILS Status Service Request Line Select 002C Family Spec ERAY0_EIES Error Service Request Enable Set 0030 Family Spec ERAY0_EIER...
  • Page 813 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_PRTC1 PRT Configuration Register 1 0090 Family Spec ERAY0_PRTC2 PRT Configuration Register 2 0094 Family Spec ERAY0_MHDC MHD Configuration Register 0098...
  • Page 814 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_CCSV Communication Controller Status Vector 0100 Family Spec ERAY0_CCEV Communication Controller Error Vector 0104 Family Spec ERAY0_SCV Slot Counter Value 0110...
  • Page 815 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_FRFM FIFO Rejection Filter Mask 0308 Family Spec ERAY0_FCL FIFO Critical Level 030C Family Spec ERAY0_MHDS Message Handler Status 0310 Family...
  • Page 816 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_MBSC1 Message Buffer Status Changed 1 0340 Family Spec ERAY0_MBSC2 Message Buffer Status Changed 2 0344 Family Spec ERAY0_MBSC3...
  • Page 817 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_WRDSn Write Data Section n 0400 +(n-1)*4 See (n=01-64) Family Spec ERAY0_WRHS1 Write Header Section 1 0500 Family Spec...

  • Page 818: Tc37X Specific Registers

    AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 334 Register Overview - ERAY (ascending Offset Address) (cont’d) Short Name Long Name Offset Page Address Number ERAY0_OCS OCDS Control and Status 08E8 Family Spec ERAY0_KRSTCLR Kernel Reset Status Clear Register 08EC Family Spec ERAY0_KRST1 Kernel Reset Register 1...

  • Page 819: Revision History

    AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 335 Connections of ERAY0 (cont’d) Interface Signals connects Description ERAY0:TXDA P02.0:ALT(6) Transmit Channel A P11.3:ALT(4) P14.0:ALT(3) P14.10:ALT(6) ERAY0:TXDB P02.2:ALT(6) Transmit Channel B P11.12:ALT(4) P14.0:ALT(4) P14.5:ALT(6) ERAY0:TXENA P02.4:ALT(6) Transmit Enable Channel A P11.6:ALT(4) P14.9:ALT(6) ERAY0:TXENB P02.5:ALT(6) Transmit Enable Channel B...
  • Page 820 AURIX™ TC37x FlexRay™ Protocol Controller (E-Ray) Table 336 Revision History (cont’d) Reference Change to Previous Version Comment V3.2.11 – No functional change. User’s Manual 39-11 V2.0.0 E-RayV3.2.11 2021-02 OPEN MARKET VERSION...

  • Page 821: Peripheral Sensor Interface (Psi5)

    AURIX™ TC37x Peripheral Sensor Interface (PSI5) Peripheral Sensor Interface (PSI5) This chapter describes the Peripheral Sensor Interface (short PSI5) Module of the TC37x. 40.1 TC37x Specific IP Configuration See features in family spec. Table 337 TC37x specific configuration of PSI5 Parameter PSI5 Number of PSI5 channels for this device...
  • Page 822 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_FDRT Fractional Divider Register SV,U SV,E,P Application for Time Stamp Reset Family Spec PSI5_TSRA...
  • Page 823 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_SFTSCx Start of Frame Time Stamp SV,U Application (x=0-1) Capture Register x Reset Family Spec...
  • Page 824 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_INTSTATAx Interrupt Status Register A x 310 SV,U Application (x=0-1) Reset Family Spec PSI5_INTSTATBx...
  • Page 825 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_KRSTCLR Kernel Reset Status Clear U,SV SV,P,E Application Register Reset Family Spec PSI5_RFCx Receive FIFO Control...
  • Page 826 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_TEISETx TEI Overview Set Register x 4E8 SV,U,P Application (x=0-1) Reset Family Spec PSI5_CRCISETx...

  • Page 827: Tc37X Specific Registers

    AURIX™ TC37x Peripheral Sensor Interface (PSI5) Register Overview - PSI5 (ascending Offset Address) (cont’d) Table 339 Short Name Long Name Offset Access Mode Reset Page Address Number Read Write PSI5_RDMLxy Receive Data Memory Low SV,U Application (x=0-3;y=0-31) Reset Family Spec PSI5_RDMHxy Receive Data Memory High SV,U...
  • Page 828 AURIX™ TC37x Peripheral Sensor Interface (PSI5) Table 341 Revision History Reference Change to Previous Version Comment No functional changes. Page 7 Formal changes in Connectivity tables. Revision History entries up to V1.17.10 removed. V1.17.12 Page 1 Second sentence changed to internal audience only due to customer confusion.

  • Page 829: Peripheral Sensor Interface With Serial Phy Connection (Psi5-S)

    AURIX™ TC37x Peripheral Sensor Interface with Serial PHY Connection (PSI5-S) Peripheral Sensor Interface with Serial PHY Connection (PSI5-S) This chapter describes the Peripheral Sensor Interface with Serial PHY Connection (short PSI5-S) Module of the TC37x. 41.1 TC37x Specific IP Configuration See features in family spec.

  • Page 830: Revision History

    AURIX™ TC37x Peripheral Sensor Interface with Serial PHY Connection (PSI5-S) Table 344 Connections of PSI5S (cont’d) Interface Signals connects Description PSI5S:TRIG(7:0) from GTM:PSI5S.TRIG(7:0) GTM timer output vector PSI5S:TRIGO(7:0) INT:psi5s.TRIGO(7:0) PSI5-S Service Request 41.5 Revision History Table 345 Revision History Reference Change to Previous Version Comment V1.12.10 Page 1...

  • Page 831: Gigabit Ethernet Mac (Geth)

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) Gigabit Ethernet MAC (GETH) This document describes the GETH Interface specific appendix for the product TC37x. 42.1 TC37x Specific IP Configuration No product specific configuration for GETH 42.2 TC37x Specific Register Set Register Address Space Table The address space for the module registers is defined in Register Address Space Table.
  • Page 832 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_VLA MAC VLAN Hash Table 0058 U,SV U,SV,P Application N_HASH_TABLE Register Reset Family Spec...
  • Page 833 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_RWK MAC Wake-up Packet Filter 00C4 U,SV U,SV,P Application _PACKET_FILTER Register Reset Family Spec...
  • Page 834 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_HW_ MAC Hardware Feature 0124 U,SV U,SV,P Application FEATURE2 Register 2 Reset Family Spec...
  • Page 835 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MMC_TX_I MMC Transmit Interrupts 0710 U,SV U,SV,P Application NTERRUPT_MAS Mask Register Reset Family Spec...
  • Page 836 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_TX_BROA Good And Bad Transmitted 0744 U,SV U,SV,P Application DCAST_PACKETS Broadcast Packets Count Reset Family _GOOD_BAD...
  • Page 837 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RX_PACKE Good And Bad Received 0780 U,SV U,SV,P Application TS_COUNT_GOO Packets Count Register Reset Family D_BAD...
  • Page 838 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RX_256TO Good And Bad 256to511 07B8 U,SV U,SV,P Application 511OCTETS_PAC Octets Packets Received Reset Family KETS_GOOD_BA...
  • Page 839 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_TX_LPI_TR Transmitted LPI Transition 07F0 U,SV U,SV,P Application AN_CNTR Count Register Reset Family Spec...
  • Page 840 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RXUDP_E Received UDP Error Packets 0834 U,SV U,SV,P Application RROR_PACKETS Count Register Reset Family Spec...
  • Page 841 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_RXUDP_E Received UDP Error Octets 0874 U,SV U,SV,P Application RROR_OCTETS Count Register Reset Family Spec...
  • Page 842 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_TIME MAC Timestamp Status 0B20 U,SV U,SV,P Application STAMP_STATUS Register Reset Family Spec GETH_MAC_TX_T...
  • Page 843 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MAC_PPS MAC PPS 0 Interval Register 0B88 U,SV U,SV,P Application 0_INTERVAL Reset Family Spec...
  • Page 844 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MTL_RXQ MTL Queue 0 Receive 0D3C U,SV U,SV,P Application 0_CONTROL Control Register Reset Family Spec...
  • Page 845 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_MTL_RXQi MTL Queue i Receive Missed 0D74 U,SV U,SV,P Application _MISSED_PACKE Packet and Overflow -1)*40 Reset...
  • Page 846 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_DMA_CHi_ DMA Channel i Transmit 1120 U,SV U,SV,P Application TXDESC_TAIL_P Descriptor Tail Pointer Reset Family OINTER...
  • Page 847 AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_DMA_CHi_ DMA Channel i Current 115C U,SV U,SV,P Application CURRENT_APP_R Application Receive Buffer Reset Family XBUFFER...

  • Page 848: Tc37X Specific Registers

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 347 Register Overview - GETH (ascending Offset Address) (cont’d) Short Name Long Name Offset Access Mode Reset Page Address Number Read Write GETH_ACCEN1Dx Access Enable Register 1 for 2024 U,SV SV,SE Application (x=0-3) DMAx Reset Family...

  • Page 849: Dma Burst Lengths Limitations By The System

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) Table 348 Connections of GETH (cont’d) Interface Signals connects Description GETH:RXCLKA from P11.12:IN Receive Clock MII and RGMII TC37x:P11.12 GETH:RXCLKB from P11.4:IN Receive Clock MII and RGMII GETH:RXCLKC from P12.0:IN Receive Clock MII and RGMII GETH:RXD0A from P11.10:IN Receive Data 0 MII, RMII and RGMII (RGMII can...

  • Page 850: Buffer And Descriptor Alignment

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) 42.6 Buffer and Descriptor Alignment The GETH is implemented as a 32 bit peripheral. Nevertheless it is connected to 64 bit wide bus (SRI). To make full use of the possible performance of SRI and its bridges, the data buffers and the descriptors need to be aligned to 64 bit addresses.

  • Page 851: Clocks

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) 42.10 Clocks The module has multiple clock inputs and outputs connecting it to the system. They are connected to the system as shown in Table 351. If the application wants to use the IP in RGMII mode the appliction has to execute the following steps: •...

  • Page 852: Revision History

    AURIX™ TC37x Gigabit Ethernet MAC (GETH) 42.11 Revision History Table 352 Revision History Reference Change to Previous Version Comment V1.3.10 Page 18 Missing connections table fixed. Page 22 Previous versions removed from revision history. V1.3.11 – No functional changes. – V1.3.12 changed to f as connection of clk_ptp_ref_i.

  • Page 853: External Bus Unit (Ebu)

    AURIX™ TC37x External Bus Unit (EBU) External Bus Unit (EBU) This device doesn’t contain an EBU module. User’s Manual 43-1 V2.0.0 2021-02 OPEN MARKET VERSION...

  • Page 854: Sd- And Emmc Interface (Sdmmc)

    AURIX™ TC37x SD- and eMMC Interface (SDMMC) SD- and eMMC Interface (SDMMC) This device doesn’t contain an SDMMC module. User’s Manual 44-1 V2.0.0 SDMMC 2021-02 OPEN MARKET VERSION...

  • Page 855: Hardware Security Module (Hsm)

    The HSM is a separate processor subsystem dedicated for security tasks. It is connected as master and slave to the SPB bus. For security reasons this module is described in a separate documentation. Please contact your Infineon representative for further information.

  • Page 856: Input Output Monitor (Iom)

    AURIX™ TC37x Input Output Monitor (IOM) Input Output Monitor (IOM) This document describes the IOM specific appendix for the product TC37x. 46.1 TC37x Specific IP Configuration Table 353 TC37x specific configuration of IOM Parameter Number of FPC channels Number of GTM inputs Number of LAM Number of ECM 46.2...
  • Page 857 AURIX™ TC37x Input Output Monitor (IOM) Connections of IOM (cont’d) Table 355 Interface Signals connects Description IOM:MON1(6) from CCU60:COUT63 Monitor input 1 IOM:MON1(7) from CCU61:COUT63 Monitor input 1 IOM:MON1(8) from CCU61:CC60 Monitor input 1 IOM:MON1(9) from CCU61:CC61 Monitor input 1 IOM:MON2(0) from QSPI0:MRST Monitor input 2...
  • Page 858 AURIX™ TC37x Input Output Monitor (IOM) Connections of IOM (cont’d) Table 355 Interface Signals connects Description IOM:PIN(12) from P33.12:IN GPIO pad input to FPC IOM:PIN(13) from P20.12:IN GPIO pad input to FPC IOM:PIN(14) from P20.13:IN GPIO pad input to FPC IOM:PIN(15) from P20.14:IN GPIO pad input to FPC...
  • Page 859 AURIX™ TC37x Input Output Monitor (IOM) 46.5 Revision History Table 356 Revision History Reference Change to Previous Version Comment V2.1.15 – No changes. User’s Manual 46-4 V2.0.0 IOMV2.1.15 2021-02 OPEN MARKET VERSION...
  • Page 860 AURIX™ TC37x 8-Bit Standby Controller (SCR) 8-Bit Standby Controller (SCR) The description of the SCR for all devices is covered by the family specification. User’s Manual 47-1 V2.0.0 2021-02 OPEN MARKET VERSION...
  • Page 861 AURIX™ TC37x Revision history Document Date of Description of changes version release • Version comparison table updated. V2.0.0 2021-02 • For further changes see respective revision history of each chapter. The version comparison table below gives an overview. • Version comparison table updated. V1.6.0 2020-08 •...
  • Page 862 AURIX™ TC37x Chapter name UM V1.6.0 UM V2.0.0 Content changes chapter version chapter version • SBCU, EBCU V1.2.8 V1.2.9 No functional changes V1.1.20 V1.1.21 No functional changes NVM Subsystem V2.0.7 V2.0.7 • V2.0.11 V2.0.12 No functional changes • V2.0.6 V2.0.6 –...
  • Page 863 AURIX™ TC37x Chapter name UM V1.6.0 UM V2.0.0 Content changes chapter version chapter version SENT V2.1.10 V2.1.10 MCMCAN V1.19.13 V1.19.13 E-Ray V3.2.10 V3.2.11 No functional changes PSI5 V1.17.12 V1.17.12 PSI5-S V1.12.10 V1.12.10 GETH V1.3.14 V1.3.15 No functional changes – SDMMC –...
  • Page 864 Infineon Technologies, Infineon Technologies in customer's applications. Infineon Technologies’ products may not be used in Document reference The data contained in this document is exclusively any applications where a failure of the product or any intended for technically trained staff.

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