Infineon AURIX TC33xEXT Manuals

Manuals and User Guides for Infineon AURIX TC33xEXT. We have 1 Infineon AURIX TC33xEXT manual available for free PDF download: Manual

Infineon AURIX TC33xEXT Manual (457 pages)

Brand: Infineon | Category: Microcontrollers | Size: 3 MB

Table of Contents
2
Introduction
8
Memory Maps (MEMMAP)
9
Overview
9
Functional Description
9
Segments
9
Bus Fabric SRI
10
Bus Instance SPB
15
Bus Instance BBB
17
Revision History
19
Tc33Xext Firmware
20
Checker Software Exit Information for ALL CHECKS PASSED
20
Revision History
20
On-Chip System Connectivity {And Bridges
22
Tc33Xext Specific IP Configuration
22
Tc33Xext Specific Register Set
23
Tc33Xext Specific Registers
25
Sri Slave Interface
25
Connectivity
25
Interconnection Matrices
25
Domain 0 Interconnection Matrix
25
Revision History
26
FPI Bus Control Units (SBCU, EBCU)
27
Tc33Xext Specific IP Configuration
27
SBCU Control Unit Registers
27
SBCU Control Registers Descriptions
30
SBCU OCDS Registers Descriptions
31
EBCU Control Unit Registers
38
EBCU Control Registers Descriptions
41
EBCU OCDS Registers Descriptions
42
Connectivity
49
SBCU Connectivity
49
EBCU Connectivity
49
Revision History
49
CPU Subsystem (CPU)
50
Tc33Xext Specific Configuration
50
Tc33Xext Specific Register Set
50
Tc33Xext Specific Registers
66
SRI Slave Interface for SFR+CSFR
66
Connectivity
66
Revision History
67
Non Volatile Memory (NVM) Subsystem
68
Overview
68
Revision History
71
Data Memory Unit (DMU)
72
Tc33Xext Specific Register Set
72
Tc33Xext Specific Registers
78
SRI Slave Interface - Register Address Space
78
Connectivity
83
Revision History
83
Non Volatile Memory (NVM)
84
Tc33Xext Specific Register Set
84
Connectivity
85
Revision History
85
Local Memory Unit (LMU)
86
System Control Unit (SCU)
88
Tc33Xext Specific IP Configuration
88
LBIST Considerations for Tc33Xext
88
Tc33Xext AA
88
Tc33Xext Specific Register Set
89
Tc33Xext Specific Registers
97
SCU: Connections to FPI/BPI Bus
97
Connectivity
109
Revision History
111
Clocking System
113
Power Management System (PMS)
114
Tc33Xext Specific IP Configuration
114
Tc33Xext Specific Register Set
115
Tc33Xext Specific Registers
115
FPI Slave Interface
115
Connectivity
120
Revision History
120
Power Management System for Low-End (PMSLE)
122
Memory Test Unit (MTU)
123
Tc33Xext Specific IP Configuration
123
Handling of Large DSPR Srams
123
Tc33Xext Specific Register Set
124
Tc33Xext Specific Registers
125
MEMTEST Implementation
125
MEMMAP Implementation
130
MEMSTAT Implementation
132
MEMDONE Implementation
135
MEMFDA Implementation
139
SSH Instances
144
Ganging for SRAM Test and Initialization
147
Connectivity
148
Revision History
149
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
150
Tc33Xext Specific IP Configuration
150
Tc33Xext Specific Register Set
150
Pn Registers
172
SPB Bus Slave Interface
172
Device Specific Connectivity Documentation
246
Revision History
247
Safety Management Unit (SMU)
248
Tc33Xext Specific IP Configuration
248
Tc33Xext Specific Register Set
249
Tc33Xext Specific Registers
251
Tc33Xext Specific Registers
252
15.3.1.1 FPI Slave Interface
252
Tc33Xext Specific Alarm Mapping
269
Tc33Xext Specific Pre-Alarms
269
Tc33Xext Specific Alarms
272
Connectivity
289
Revision History
290
Interrupt Router (IR)
291
Tc33Xext Specific Interrupt Router Configuration
291
Tc33Xext Specific Control Registers
292
Tc33Xext Specific Registers
294
Tc33Xext Specific Service Request Control (SRC) Registers
295
Tc33Xext Specific Registers
299
IR Service Request Control Registers (SRC)
299
Revision History
313
Flexible CRC Engine (FCE)
315
Tc33Xext Specific IP Configuration
315
Tc33Xext Specific Register Set
316
Tc33Xext Specific Registers
317
Connectivity
317
Revision History
317
Direct Memory Access (DMA)
318
Tc33Xext Specific IP Configuration
318
Tc33Xext Specific Register Set
318
Tc33Xext Specific Registers
321
Connectivity
321
Revision History
321
Signal Processing Unit (SPU)
323
Tc33Xext Specific IP Configuration
323
Tc33Xext Specific Register Set
323
Tc33Xext Specific Registers
328
Connectivity
328
Revision History
329
SPU Lockstep Comparator (SPULCKSTP)
330
Extended Memory (EMEM)
331
Tc33Xext Specific IP Configuration
331
Tc33Xext Specific Register Set
331
Tc33Xext Specific Registers
333
Connectivity
333
Revision History
334
Radar Interface (RIF)
335
Tc33Xext Specific IP Configuration
335
Tc33Xext Specific Register Set
335
Address Map
335
Tc33Xext Specific Registers
335
Connectivity
335
Revision History
336
High Speed Pulse Density Modulation Module (HSPDM)
338
Tc33Xext Specific IP Configuration
338
Tc33Xext Specific Register Set
338
Address Map
338
Tc33Xext Specific Registers
338
Connectivity
338
Connections Regarding Hardware Run Feature
338
Pinning and Layout
339
Revision History
339
Camera and ADC Interface (CIF)
340
System Timer (STM)
341
Tc33Xext Specific IP Configuration
341
Tc33Xext Specific Register Set
341
Tc33Xext Specific Registers
341
Connectivity
341
Revision History
342
Generic Timer Module (GTM)
343
Capture/Compare Unit 6 (CCU6)
344
Tc33Xext Specific Register Set
344
Tc33Xext Specific Registers
350
Connectivity
350
Revision History
355
General Purpose Timer Unit (GPT12)
356
Tc33Xext Specific Register Set
356
Tc33Xext Specific Registers
356
Connectivity
357
Revision History
358
Converter Control Block (CONVCTRL)
359
Tc33Xext-Specific IP Configuration
359
Tc33Xext Specific Register Set
359
Tc33Xext Specific Registers
359
Connectivity
360
Revision History
360
Enhanced Versatile Analog-To-Digital Converter (EVADC)
361
Tc33Xext-Specific IP Configuration
361
Tc33Xext Specific Register Set
362
Connectivity
363
Analog Module Connections
363
Digital Module Connections
366
Revision History
368
Enhanced Delta-Sigma Analog-To-Digital Converter (EDSADC)
369
Inter-Integrated Circuit (I2C)
370
High Speed Serial Link (HSSL)
371
Asynchronous Serial Interface (ASCLIN)
372
Tc33Xext Specific IP Configuration
372
Tc33Xext Specific Register Set
373
Tc33Xext Specific Registers
385
Connectivity
385
Revision History
389
Queued Synchronous Peripheral Interface (QSPI)
390
Tc33Xext Specific IP Configuration
390
Tc33Xextspecific Register Set
391
Tc33Xext Specific Registers
399
Register Block QSPI
399
Connectivity
403
Revision History
407
Micro Second Channel (MSC)
408
Single Edge Nibble Transmission (SENT)
409
Tc33Xext Specific IP Configuration
409
Tc33Xext Specific Register Set
410
Tc33Xext Specific Registers
410
Connectivity
410
Interrupt and DMA Controller Service Requests
410
Trigger Inputs
410
Connections of SENT
410
Revision History
411
CAN Interface (MCMCAN)
412
Tc33Xext Specific IP Configuration
412
Tc33Xext Specific Register Set
413
Tc33Xext Specific Registers
418
Connectivity
418
Revision History
421
Flexray™ Protocol Controller (E-Ray)
422
Peripheral Sensor Interface (PSI5)
423
Peripheral Sensor Interface with Serial PHY Connection (PSI5-S)
424
Gigabit Ethernet MAC (GETH)
425
Tc33Xext Specific IP Configuration
425
Tc33Xext Specific Register Set
425
Tc33Xext Specific Registers
442
Connectivity
442
DMA Burst Lengths Limitations by the System
443
Buffer and Descriptor Alignment
443
Embedded Fifos
444
Master TAG ID
444
Interrupt Service Requests
444
Clocks
444
Revision History
446
External Bus Unit (EBU)
447
SD- and Emmc Interface (SDMMC)
448
Tc33Xext Specific Register Set
449
Tc33Xext Specific Registers
449
Connectivity
449
Revision History
450
Hardware Security Module (HSM)
451
Input Output Monitor (IOM)
452
47 8-Bit Standby Controller (SCR)
453
Revision History
454

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Infineon AURIX TC33xEXT Manual (457 pages)

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