Omron MX2 COMPONET OPTION BOARD User Manual page 42

Mx2 componet option board
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Flexible Format
4-7-2
Operating the Motor
Step 8
Step 9
Step 10
Step 11
Step 12
4-7-3
Faults and Trips
!WARNING
!WARNING
28
Set A001 = 3 and A002 = 3 so that the Inverter can be controlled using the
Modbus registers in Flexible mode.
Set the Opr bit to put the Inverter in run mode. The RUN indicator on the
Inverter should light up at this point. If this is not the case, check your source
selection.
Change F001 in the Output data to the desired frequency (E.g. 1000 for
10.00 Hz)
Table 20 Flex Mode Output Area with Motor Running Forward
Word offset
+0
+1
Register
Coil data 0
F001 (0001h/0002h)
dec
2
Value
hex
0002
0000
Bit
15
14
*1
Name
-
-
Value
0
0
The motor accelerates until it reaches the desired frequency. Notice that the
FA1 bit is set once the inverter has reached the desired reference frequency.
Table 21 Flex Mode Input Area with Motor Running Forward
Word offset
+0
+1
Register
Invstat C
Coil data 1
dec
3
26
Value
hex
0003
001A
Bit
15
14
Name
ONT RNT TRQ UV
Value
0
0
Set Dir to reverse the direction of the motor. The motor decelerates, stops and
then accelerates in the opposite direction. The FA1 bit clears as soon as the
reference frequency is changed. Once the new reference frequency is
reached, the FA1 bit is once again set.
Clear the Opr bit to stop the motor. The motor decelerates and comes to a
halt.
User trips can be generated by setting the EXT bit in coil data 0. You must
always immediately clear the Opr bit in your PLC program when the Unit indi-
cates it is in Trip status (for example when AL bit is set ON). If the Opr bit is set
when the trip condition is cleared, the Inverter will immediately start running!
Always clear the Opr bit in your PLC program when the AL bit is set ON by the
Inverter. Not doing so may result in the motor starting unexpectedly when the
trip is cleared.
Set and clear the RS bit in coil data 0 to clear a trip.
Always clear the RS bit after setting it. Not doing so will result in new trip con-
ditions automatically being cleared.
+2
+3
+4
-
-
+1000
0
0
03E8
0000
0000
13
12
11
10
9
8
In7 In6 In5 In4 In3 In2 In1
0
0
0
0
0
0
+2
+3
+4
d001 (1001h/1002h)
-
+1000
0
0000
03E8
0000
13
12
11
10
9
8
- OTQ FA3 AL OD OL FA2 FA1 RUN -
0
0
0
0
0
0
Section 4-7
+5
+6
+7
-
-
-
0
0
0
0000
0000
0000
7
6
5
4
3
2
-
-
RS EXT Dir Opr
0
0
0
0
0
0
+5
+6
+7
-
-
-
0
0
0
0000
0000
0000
7
6
5
4
3
2
1
Rdy Dir
0
0
0
1
1
0
1
1
0
-
1
0
0
0

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