Sign In
Upload
Manuals
Brands
GigaDevice Semiconductor Manuals
Microcontrollers
GD32L233 Series
GigaDevice Semiconductor GD32L233 Series Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32L233 Series. We have
1
GigaDevice Semiconductor GD32L233 Series manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32L233 Series User Manual (837 pages)
Arm Cortex-M23 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Microcontrollers
| Size: 6 MB
Table of Contents
Table of Contents
2
Gd32L23X User Manual List of Figures
19
List of Figures
19
List of Tables
27
Arm ® Cortex ® -M23 Processor
30
System and Memory Architecture
30
Figure 1-1. the Structure of the Arm
31
System Architecture
31
Table 1-1. Bus Interconnection Matrix
31
Figure 1-2. Series System Architecture of Gd32L23X(X=3) Series
33
Figure 1-3. Series System Architecture of Gd32L23X(X=5) Series
34
Memory Map
34
Table 1-2. Memory Map of Gd32L23X(X=3) Series
35
Table 1-3. Memory Map of Gd32L23X(X=5) Series
37
On-Chip Flash Memory
40
On-Chip SRAM Memory
40
Boot Configuration
41
System Configuration Controller (SYSCFG)
41
Table1-4. Boot Modes
41
System Configuration Register 0 (SYSCFG_CFG0)
42
System Configuration Registers
42
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
45
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
46
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
47
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
49
System Configuration Register 1 (SYSCFG_CFG1)
50
IRQ Latency Register (SYSCFG_CPU_IRQ_LAT)
51
Timerx Configuration Register (Syscfg_Timerxcfg, X=0)
52
Timerx Configuration Register (Syscfg_Timerxcfg, X=1, 2)
54
Timerx Configuration Register (Syscfg_Timerxcfg, X=8, 11)
56
Timerx Configuration Register (Syscfg_Timerxcfg, X=14, 40)
58
Device Electronic Signature
60
Memory Density Information
60
Unique Device ID (96 Bits)
60
Characteristics
62
Flash Memory Architecture
62
Flash Memory Controller (FMC)
62
Function Overview
62
Overview
62
Table 2-1. 256KB Flash Base Address and Size for Flash Memory
63
Table 2-2. 128KB Flash Base Address and Size for Flash Memory
63
Table 2-3. 64KB Flash Base Address and Size for Flash Memory
63
Error Checking and Correcting (ECC) (Only Available in Gd32L235Xx)
64
Table 2-4. 32KB Flash Base Address and Size for Flash Memory
64
Table 2-5. Flash Base Address and Size for Flash Memory
64
Read Operations
65
Table 2-6. the Relation between WSCNT and AHB Clock Frequency When LDO Is 1.1V for Gd32L233Xx
65
Table 2-7. the Relation between WSCNT and AHB Clock Frequency When LDO Is 0.9V for
66
Table 2-8. the Relation between WSCNT and AHB Clock Frequency When LDO Is 1.1V for
66
Page Erase
67
Unlock the FMC_CTL Register
67
Figure 2-1. Process of Page Erase Operation
68
Mass Erase
68
Figure 2-2. Process of Mass Erase Operation
69
Main Flash Programming
70
Figure 2-3. Process of Program Operation
72
Main Flash Fast Programming (Only Available in Gd32L233Xx)
72
Figure 2-4. Process of Fast Program Operation
74
Option Bytes Erase
75
Option Bytes Modify
75
OTP Programming
75
Option Bytes Description
76
Table 2-9. Option Bytes
76
Page Erase / Program Protection
77
LVE Sequence (Only Available in Gd32L233Xx)
78
Security Protection
78
Register Definition
79
Wait State Register (FMC_WS)
79
Option Bytes Unlock Key Register (FMC_OBKEY)
81
Unlock Key Register (FMC_KEY)
81
Status Register (FMC_STAT)
82
Control Register (FMC_CTL)
84
Address Register (FMC_ADDR)
87
ECC Control and Status Register (FMC_ECCCS)
87
Erase/Program Protection Register (FMC_WP)
89
Option Bytes Status Register (FMC_OBSTAT)
89
Product ID Register (FMC_PID)
90
Unlock Flash Sleep/Power-Down Mode Key Register (FMC_SLPKEY)
90
Characteristics
91
Figure 3-1. Power Supply Overview of Gd32L233Xx Devices
91
Overview
91
Power Management Unit (PMU)
91
Function Overview
93
Battery Backup Domain
94
Figure 3-2. Power Supply Overview of Gd32L235Xx Devices
94
Figure 3-3. Waveform of the BOR0
95
VDD / V Dda
95
Figure 3-4. Waveform of the BOR
96
Figure 3-5. Waveform of the LVD Threshold
97
Power Domain
97
Power Saving Modes
99
Table 3-1. Power Saving Mode Summary (for Gd32L233Xx Devices)
102
Table 3-2. Power Saving Mode Summary(for Gd32L235Xx Devices)
103
Control Register 0 (PMU_CTL0)
105
Register Definition
105
Control and Status Register (PMU_CS)
108
Control Register 1 (PMU_CTL1)
112
Status Register (PMU_STAT)
114
Parameter Register (PMU_PAR)
116
Function Overview
118
Overview
118
Reset and Clock Unit (RCU)
118
Reset Control Unit (RCTL)
118
Clock Control Unit (CCTL)
119
Figure 4-1. the System Reset Circuit
119
Overview
119
Figure 4-2. Clock Tree of Gd32L233Xx Devices
120
Figure 4-3. Clock Tree of Gd32L235Xx Devices
121
Characteristics
122
Function Overview
122
Figure 4-4. HXTAL Clock Source
123
Figure 4-5. HXTAL Clock Source in Bypass Mode
123
Table 4-1. Clock Source Select
126
Control Register (RCU_CTL)
128
Register Definition
128
Configuration Register 0 (RCU_CFG0)
130
Interrupt Register (RCU_INT)
133
APB2 Reset Register (RCU_APB2RST)
136
APB1 Reset Register (RCU_APB1RST)
138
AHB Enable Register (RCU_AHBEN)
143
APB2 Enable Register (RCU_APB2EN)
145
APB1 Enable Register (RCU_APB1EN)
146
Backup Domain Control Register (RCU_BDCTL)
152
Reset Source /Clock Register (RCU_RSTSCK)
153
AHB Reset Register (RCU_AHBRST)
155
Configuration Register 1 (RCU_CFG1)
156
Configuration Register 2 (RCU_CFG2)
157
AHB2 Enable Register (RCU_AHB2EN)
161
AHB2 Reset Register (RCU_AHB2RST)
162
Voltage Key Register (RCU_VKEY)
162
Low Power Bandgap Mode Register (RCU_LPB)
163
Characteristics
165
Clock Trim Controller (CTC)
165
Figure 5-1. CTC Overview
165
Function Overview
165
Overview
165
CTC Trim Counter
166
REF Sync Pulse Generator
166
Figure 5-2. CTC Trim Counter
167
Frequency Evaluation and Automatically Trim Process
167
Software Program Guide
168
Control Register 0 (CTC_CTL0)
170
Register Definition
170
Control Register 1 (CTC_CTL1)
171
Status Register (CTC_STAT)
172
Interrupt Clear Register (CTC_INTC)
174
Characteristics
176
Function Overview
176
Interrupt / Event Controller (EXTI)
176
Overview
176
Table 6-1. NVIC Exception Types in Cortex ® -M23
177
Table 6-2. Interrupt Vector Table for Gd32L233Xx Devices
177
Table 6-3. Interrupt Vector Table for Gd32L235Xx Devices
179
External Interrupt and Event Block Diagram
181
Figure 6-1. Block Diagram of EXTI for Gd32L233Xx Devices
181
External Interrupt and Event Function Overview
182
Figure 6-2. Block Diagram of EXTI for Gd32L235Xx Devices
182
Table 6-4. EXTI Source for Gd32L233Xx Devices
182
Table 6-5. EXTI Source for Gd32L235Xx Devices
184
Interrupt Enable Register (EXTI_INTEN)
186
Register Definition
186
Event Enable Register (EXTI_EVEN)
187
Rising Edge Trigger Enable Register (EXTI_RTEN)
188
Falling Edge Trigger Enable Register (EXTI_FTEN)
189
Software Interrupt Event Register (EXTI_SWIEV)
190
Pending Register (EXTI_PD)
191
Characteristics
192
Function Overview
192
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
192
Overview
192
Figure 7-1. Basic Structure of a General-Pupose I/O
193
Table 7-1. GPIO Configuration Table
193
Additional Functions
194
Alternate Functions (AF)
194
External Interrupt / Event Lines
194
GPIO Pin Configuration
194
Input Configuration
194
Analog Configuration
195
Figure 7-2. Basic Structure of Input Configuration
195
Figure 7-3. Basic Structure of Output Configuration
195
Output Configuration
195
Alternate Function (AF) Configuration
196
Figure 7-4. Basic Structure of Analog Configuration
196
Figure 7-5. Basic Structure of Alternate Function Configuration
196
GPIO Locking Function
197
GPIO Single Cycle Toggle Function
197
Port Control Register (Gpiox_Ctl, X=A
198
Register Definition
198
Port Output Mode Register (Gpiox_Omode, X=A
199
Port Output Speed Register (Gpiox_Ospd, X=A
201
Port Pull-Up/Down Register (Gpiox_Pud, X=A
203
Port Bit Operate Register (Gpiox_Bop, X=A
205
Port Input Status Register (Gpiox_Istat, X=A
205
Port Output Control Register (Gpiox_Octl, X=A
205
Port Configuration Lock Register (Gpiox_Lock, X=A
206
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
207
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
208
Bit Clear Register (Gpiox_Bc, X=A
209
Port Bit Toggle Register (Gpiox_Tg, X=A
210
Characteristics
211
Cyclic Redundancy Checks Management Unit (CRC)
211
Overview
211
Figure 8-1. Block Diagram of CRC Calculation Unit
212
Function Overview
212
Data Register (CRC_DATA)
214
Free Data Register (CRC_FDATA)
214
Register Definition
214
Control Register (CRC_CTL)
215
Initialization Data Register (CRC_IDATA)
215
Polynomial Register (CRC_POLY)
216
Characteristics
217
Figure 9-1. TRNG Block Diagram
217
Function Overview
217
Overview
217
True Random Number Generator (TRNG)
217
Error Flags
218
Operation Flow
218
Control Register (TRNG_CTL)
219
Register Definition
219
Status Register (TRNG_STAT)
219
Data Register (TRNG_DATA)
220
Characteristics
222
Cryptographic Acceleration Unit (CAU)
222
Overview
222
CAU Data Type and Initialization Vectors
223
Data Type
223
Figure 10-1. DATAM no Swapping and Half-Word Swapping
223
Cryptographic Acceleration Processor
224
Figure 10-2. DATAM Byte Swapping and Bit Swapping
224
Figure 10-3. CAU Diagram
224
Initialization Vectors
224
DES / TDES Cryptographic Acceleration Processor
225
Figure 10-4. des / TDES ECB Encryption
226
Figure 10-5. des / TDES ECB Decryption
227
Figure 10-6. des / TDES CBC Encryption
228
AES Cryptographic Acceleration Processor
229
Figure 10-7. des / TDES CBC Decryption
229
Figure 10-8. AES ECB Encryption
230
Figure 10-9. AES ECB Decryption
231
Figure 10-10. AES CBC Encryption
232
Figure 10-11. AES CBC Decryption
233
Figure 10-12. Counter Block Structure
233
Figure 10-13. AES CTR Encryption/Decryption
233
Operating Modes
237
CAU DMA Interface
238
CAU Interrupts
238
CAU Suspended Mode
239
Control Register (CAU_CTL)
241
Register Definition
241
Data Input Register (CAU_DI)
243
Status Register 0 (CAU_STAT0)
243
Data Output Register (CAU_DO)
244
DMA Enable Register (CAU_DMAEN)
244
Interrupt Enable Register (CAU_INTEN)
245
Status Register 1 (CAU_STAT1)
245
Interrupt Flag Register (CAU_INTF)
246
Key Registers (CAU_KEY0
246
Initial Vector Registers (CAU_IV0
249
GCM or CCM Mode Context Switch Register X (Cau_Gcmccmctxsx) (X=0
250
GCM Mode Context Switch Register X (Cau_Gcmctxsx) (X=0
251
Characteristics
252
Direct Memory Access Controller (DMA)
252
Overview
252
Block Diagram
253
DMA Operation
253
Figure 11-1. Block Diagram of DMA
253
Function Overview
253
Table 11-1. DMA Transfer Operation
254
Arbitration
255
Figure 11-2. Handshake Mechanism
255
Peripheral Handshake
255
Address Generation
256
Channel Configuration
256
Circular Mode
256
Memory to Memory Mode
256
Figure 11-3. DMA Interrupt Logic
257
Interrupt
257
Table 11-2. Interrupt Events
257
DMA Request Mapping
258
Interrupt Flag Clear Register (DMA_INTC)
259
Interrupt Flag Register (DMA_INTF)
259
Register Definition
259
Channel X Control Register (Dma_Chxctl)
260
Channel X Counter Register (Dma_Chxcnt)
262
Channel X Memory Base Address Register (Dma_Chxmaddr)
263
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
263
Characteristics
265
DMA Request Multiplexer (DMAMUX)
265
Overview
265
Block Diagram
266
Figure 12-1. Block Diagram of DMAMUX
266
Signal Description
266
DMAMUX Request Multiplexer
267
Function Overview
267
Figure 12-2. Synchronization Mode
268
Figure 12-3. Event Generation
269
Channel Configurations
270
DMAMUX Request Generator
270
DMAMUX Mapping
271
Interrupt
271
Table 12-1. Interrupt Events
271
Table 12-2. Request Multiplexer Input Mapping for Gd32L233X
271
Table 12-3. Request Multiplexer Input Mapping for Gd32L235Xx
273
Table 12-4. Trigger Input Mapping
276
Table 12-5. Synchronization Input Mapping
276
Register Definition
278
Request Multiplexer Channel X Configuration Register (Dmamux_Rm_Chxcfg)
278
Request Multiplexer Channel Interrupt Flag Register (DMAMUX_RM_INTF)
280
Request Multiplexer Channel Interrupt Flag Clear Register (DMAMUX_RM_INTC)
281
Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
282
Request Generator Channel Interrupt Flag Register (DMAMUX_RG_INTF)
283
Rquest Generator Channel Interrupt Flag Clear Register (DMAMUX_RG_INTC)
283
Debug (DBG)
285
Debug Hold Function Overview
285
Debug Support for Power Saving Mode
285
Overview
285
Pin Assignment
285
SW Function Overview
285
Debug Support for TIMER, LPTIMER, I2C, RTC, WWDGT and FWDGT
286
Control Register 0 (DBG_CTL0)
287
ID Code Register (DBG_ID)
287
Register Definition
287
Control Register 1 (DBG_CTL1)
291
Analog to Digital Converter (ADC)
294
Characteristics
294
Overview
294
Figure 14-1. ADC Module Block Diagram
295
Pins and Internal Signals
295
Table 14-1. ADC Internal Input Signals
295
Table 14-2. ADC Input Pins Definition
295
Foreground Calibration Function
296
Function Overview
296
ADC Enable
297
Dual Clock Domain Architecture
297
Single-Ended and Differential Input Channels
297
Figure 14-2. Single Operation Mode
298
Operation Modes
298
Routine Sequence
298
Figure 14-3. Continuous Operation Mode
299
Figure 14-4. Scan Operation Mode, Continuous Disable
300
Figure 14-5. Scan Operation Mode, Continuous Enable
300
Conversion Result Threshold Monitor Function
301
Data Storage Mode
301
Figure 14-6. Discontinuous Operation Mode
301
Figure 14-7. Data Storage Mode of 12-Bit Resolution
301
Figure 14-10. Data Storage Mode of 6-Bit Resolution
302
Figure 14-8. Data Storage Mode of 10-Bit Resolution
302
Figure 14-9. Data Storage Mode of 8-Bit Resolution
302
Sample Time Configuration
302
ADC Internal Channels
303
DMA Request
303
External Trigger Configuration
303
Table 14-3. External Trigger Source for ADC
303
Battery Voltage Monitoring
304
Figure 14-11. 20-Bit to 16-Bit Result Truncation
305
On-Chip Hardware Oversampling
305
SLCD Voltage Monitoring
305
Figure 14-12. a Numerical Example with 5-Bit Shifting and Rounding
306
Table 14-4. Maximum Output Results for N and M Combimations (Grayed Values Indicates Truncation)
306
ADC Interrupts
307
Programmable Resolution (DRES)
307
Table 14-5. T CONV
307
Control Register 0 (ADC_CTL0)
308
Register Definition
308
Status Register (ADC_STAT)
308
Control Register 1 (ADC_CTL1)
310
Sample Time Register 0 (ADC_SAMPT0)
314
Sample Time Register 1 (ADC_SAMPT1)
315
Routine Sequence Register 0 (ADC_RSQ0)
316
Watchdog High Threshold Register (ADC_WDHT)
316
Watchdog Low Threshold Register (ADC_WDLT)
316
Routine Sequence Register 1 (ADC_RSQ1)
317
Routine Data Register (ADC_RDATA)
318
Routine Sequence Register 2 (ADC_RSQ2)
318
Oversampling Control Register (ADC_OVSAMPCTL)
319
Charge Control Register (ADC_CCTL)
320
Differential Mode Control Register (ADC_DIFCTL)
321
Characteristics
322
Digital-To-Analog Converter (DAC)
322
Figure 15-1. DAC Block Diagram
322
Overview
322
Table 15-1. DAC I/O Description
322
DAC Enable
323
DAC Output Buffer
323
Function Overview
323
Table 15-2. DAC Triggers and Outputs Summary
323
DAC Conversion
324
DAC Data Configuration
324
DAC Noise Wave
324
DAC Trigger
324
Table 15-3. Triggers of DAC
324
DAC Output Voltage
325
Figure 15-2. DAC LFSR Algorithm
325
Figure 15-3. DAC Triangle Noise Wave
325
DMA Request
326
Dacx Control Register 0 (DAC_CTL0)
327
Register Definition
327
Dacx Software Trigger Register (DAC_SWT)
328
Dacx_Out0 12-Bit Left-Aligned Data Holding Register (DAC_OUT0_L12DH)
329
Dacx_Out0 12-Bit Right-Aligned Data Holding Register (DAC_OUT0_R12DH)
329
Dacx_Out0 8-Bit Right-Aligned Data Holding Register (DAC_OUT0_R8DH)
330
Dacx_Out0 Data Output Register (DAC_OUT0_DO)
330
Dacx Status Register 0 (DAC_STAT0)
331
Characteristics
332
Free Watchdog Timer (FWDGT)
332
Function Overview
332
Overview
332
Watchdog Timer (WDGT)
332
Figure 16-1. Free Watchdog Block Diagram
333
Table 16-1. Min/Max FWDGT Timeout Period at 32Khz (IRC32K)
334
Register Definition
335
Characteristics
339
Figure 16-2. Window Watchdog Timer Block Diagram
339
Function Overview
339
Overview
339
Window Watchdog Timer (WWDGT)
339
Figure 16-3. Window Watchdog Timing Diagram
340
Table 16-2. Min-Max Timeout Value at 64 Mhz
341
Register Definition
342
Characteristics
345
Overview
345
Real Time Clock (RTC)
345
Block Diagram
346
Figure 17-1. Block Diagram of RTC
346
Function Overview
346
Clock Source and Prescalers
347
Configurable and Field Maskable Alarm
347
Shadow Registers Introduction
347
Configurable Periodic Auto-Wakeup Counter
348
RTC Initialization and Configuration
348
Calendar Reading
349
Resetting the RTC
351
RTC Shift Function
351
RTC Reference Clock Detection
352
RTC Smooth Digital Calibration
352
Tamper Detection
354
Time-Stamp Function
354
Alarm Output
357
Calibration Clock Output
357
RTC Pin Configuration
357
Table 17-1 RTC Pin PC13 Configuration
357
RTC Power Saving Mode Management
358
Table 17-2 RTC Functions in All Lowpower Modes
358
Table 17-3 RTC Power Saving Mode Management
358
RTC Interrupts
359
Table 17-4 RTC Interrupts Control
359
Date Register (RTC_DATE)
360
Register Definition
360
Time Register (RTC_TIME)
360
Control Register (RTC_CTL)
361
Status Register (RTC_STAT)
364
Prescaler Register (RTC_PSC)
366
Wakeup Timer Register (RTC_WUT)
366
Alarm 0 Time and Date Register (RTC_ALRM0TD)
367
Alarm 1 Time and Date Register (RTC_ALRM1TD)
368
Write Protection Key Register (RTC_WPK)
369
Shift Function Control Register (RTC_SHIFTCTL)
370
Sub Second Register (RTC_SS)
370
Time of Time Stamp Register (RTC_TTS)
371
Date of Time Stamp Register (RTC_DTS)
372
Sub Second of Time Stamp Register (RTC_SSTS)
372
High Resolution Frequency Compensation Register (RTC_HRFC)
373
Tamper Register (RTC_TAMP)
374
Alarm 0 Sub Second Register (RTC_ALRM0SS)
377
Alarm 1 Sub Second Register (RTC_ALRM1SS)
378
Backup Registers (Rtc_Bkpx) (X=0
379
Table 18-1. Timers (Timerx) Are Devided into Five Sorts
380
Timer (Timerx)
380
Advanced Timer (Timerx,X=0)
381
Characteristics
381
Overview
381
Block Diagram
382
Figure 18-1. Advanced Timer Block Diagram
382
Function Overview
382
Figure 18-2. Normal Mode, Internal Clock Divided by 1
383
Figure 18-3. Counter Timing Diagram with Prescaler Division Change from 1 to 2
384
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/1
384
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
386
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/1
386
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
388
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
389
Figure 18-10. Repetition Counter Timing Chart of up Counting Mode
390
Figure 18-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
390
Figure 18-11. Repetition Counter Timing Chart of down Counting Mode
391
Figure 18-12. Input Capture Logic
392
Figure 18-13. Output Compare Logic (with Complementary Output, X=0,1,2)
393
Figure 18-14. Output Compare Logic (CH3_O)
393
Figure 18-15. Output-Compare in Three Modes
394
Figure 18-16. Timing Chart of EAPWM
395
Figure 18-17. Timing Chart of CAPWM
395
Table 18-2. Complementary Outputs Controlled by Parameters
398
Figure 18-18. Complementary Output with Dead Time Insertion
399
Figure 18-19. Output Behavior of the Channel in Response to a Break (the Break High Active)
400
Figure 18-20. Example of Counter Operation in Quadrature Decoder Interface Mode
401
Figure 18-21. Example of Quadrature Decoder Interface Mode with CI0FE0 Polarity Inverted
401
Table 18-3. Counting Direction Versus Quadrature Decoder Signals
401
Figure 18-22. Hall Sensor Is Used to BLDC Motor
402
Figure 18-23. Hall Sensor Timing between Two Timers
404
Table 18-4. Examples of Slave Mode
404
Figure 18-24. Restart Mode
405
Figure 18-25. Pause Mode
406
Figure 18-26. Event Mode
406
Figure 18-27. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X60
407
Figure 18-28. Triggering TIMER0 with Enable of TIMER2
408
Figure 18-29. Triggering TIMER0 with Update Signal of TIMER2
408
Figure 18-30. Pause TIMER0 with Enable of TIMER2
409
Figure 18-31. Pause TIMER0 with O0Cpreof TIMER2
410
Timerx Registers(X=0)
411
Block Diagram
438
Characteristics
438
Figure 18-32. General Level 0 Timer Block Diagram for GD32L233
438
General Level0 Timer (Timerx, X=1, 2)
438
Overview
438
Figure 18-33. General Level 0 Timer Block Diagram for GD32L235
439
Figure 18-34. Timing Chart of Internal Clock Divided by 1
440
Function Overview
440
Figure 18-35. Timing Chart of Internal Clock Divided by 1
442
Figure 18-36. Timing Chart of PSC Value Change from 0 to 2
443
Figure 18-37. Timing Chart of up Counting Mode, PSC=0/2
443
Figure 18-38. Timing Chart of up Counting, Change Timerx_Car Ongoing
444
Figure 18-39. Timing Chart of down Counting Mode, PSC=0/2
445
Figure 18-40. Timing Chart of down Counting Mode, Change Timerx_Car Ongoing
446
Figure 18-41. Timing Chart of Center-Aligned Counting Mode
447
Figure 18-42. Channel Input Capture Principle
448
Figure 18-43. Channel Output Compare Principle (X=0,1,2,3)
449
Figure 18-44. Output-Compare under Three Modes
450
Figure 18-45. Timing Chart of EAPWM
451
Figure 18-46. Timing Chart of CAPWM
451
Table 18-5. Counting Direction in Different Quadrature Decoder Mode
453
Figure 18-47. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
454
Figure 18-48. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
454
Figure 18-49. Restart Mode
455
Table 18-6. Slave Mode Example Table for GD32L233
455
Figure 18-50. Pause Mode
456
Figure 18-51. Event Mode
456
Table 18-7. Slave Mode Example Table for GD32L235
456
Figure 18-52. Restart Mode
457
Figure 18-53. Pause Mode
457
Figure 18-54. Event Mode
458
Figure 18-55. Single Pulse Mode Timerx_Chxcv = 4 Timerx_Car=99
458
Timerx Registers(X=1, 2)
461
Characteristics
486
General Level1 Timer (Timerx, X=8, 11)
486
Overview
486
Block Diagram
487
Figure 18-56. General Level 1 Timer Block Diagram for GD32L233
487
Figure 18-57. General Level 1 Timer Block Diagram for GD32L235
487
Figure 18-58. Timing Chart of Internal Clock Divided by 1
488
Function Overview
488
Figure 18-59. Timing Chart of Internal Clock Divided by 1
489
Figure 18-60. Timing Chart of PSC Value Change from 0 to 2
490
Figure 18-61. Up-Counter Timechart, PSC=0/2
490
Figure 18-62. Up-Counter Timechart, Change Timerx_Car on the Go
491
Figure 18-63. Channel Input Capture Principle
492
Figure 18-64. Output-Compare under Three Modes
493
Figure 18-65. EAPWM Timechart
495
Figure 18-66. CAPWM Timechart
495
Table 18-8.Slave Mode Example Table for GD32L233
496
Figure 18-67. Restart Mode
497
Figure 18-68. Pause Mode
497
Figure 18-69. Event Mode
498
Figure 18-70. Restart Mode
498
Table 18-9.Slave Mode Example Table for GD32L235
498
Figure 18-71. Pause Mode
499
Figure 18-72. Event Mode
499
Figure 18-73. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
500
Timerx Registers(X=8, 11)
501
Block Diagram
515
Characteristics
515
Figure 18-74. General Level3 Timer Block Diagram
515
General Level3 Timer (Timerx, X=14,40)
515
Overview
515
Function Overview
516
Figure 18-75. Normal Mode, Internal Clock Divided by 1
517
Figure 18-76. Counter Timing Diagram with Prescaler Division Change from 1 to 2
518
Figure 18-77. Timing Chart of up Counting Mode, PSC=0/1
518
Figure 18-78. Up-Counter Timechart, Change Timerx_Car Ongoing
520
Figure 18-79. Repetition Counter Timing Chart of up Counting Mode
521
Figure 18-80. Input Capture Logic
522
Figure 18-81. Output Compare Logic (with Complementary Output, X=0)
523
Figure 18-82. Output Compare Logic (CH1_O)
523
Figure 18-83. Output-Compare in Three Modes
524
Figure 18-84. PWM Mode Timechart
525
Table 18-10. Complementary Outputs Controlled by Parameters
527
Figure 18-85. Complementary Output with Dead-Time Insertion
528
Figure 18-86. Output Behavior in Response to a Break(the Break High Active)
529
Figure 18-87. Restart Mode
530
Figure 18-88. Pause Mode
530
Table 18-11. Slave Mode Example Table
530
Figure 18-89. Event Mode
531
Figure 18-90. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
532
Timerx Registers(X=14,40)
534
Basic Timer (Timerx, X=5, 6)
553
Block Diagram
553
Characteristics
553
Figure 18-91. Basic Timer Block Diagram
553
Function Overview
553
Overview
553
Figure 18-92. Timing Chart of Internal Clock Divided by 1
554
Figure 18-93. Timing Chart of PSC Value Change from 0 to 2
555
Figure 18-94. Timing Chart of up Counting Mode, PSC=0/2
555
Figure 18-95. Timing Chart of up Counting Mode, Change Timerx_Car Ongoing
556
Timerx Registers(X=5,6)
558
Characteristics
563
Low Power Timer (LPTIMER)
563
Overview
563
Block Diagram
564
Clock Selection
564
Figure 19-1. LPTIMER Block Diagram
564
Function Overview
564
Figure 19-2. LPTIMER Clock Source Selection
565
Figure 19-3. Internal Clock Mode1 (CKSSEL = 0 and CNTMEN = 1 and PSC[2:0] = 000)
566
Table 19-1. Prescaler Division Factor
566
Figure 19-4. Input Filter Timing Diagram (Eckflt=2'B01)
567
Figure 19-5. External Inputs High Level Counter
568
Table 19-2. External Trigger Mapping
569
Figure 19-6. LPTIMER Output with SMST = 1(32-Bit)
570
Figure 19-7. LPTIMER Output with OMSEL = 1(32-Bit)
570
Figure 19-8. LPTIMER Output with CTNMST = 1(32-Bit)
571
Figure 19-9. LPTIMER_O Output Mode with OPSEL Bit(32-Bit)
572
Figure 19-10. LPTIMER Timeout Mode(32-Bit)
573
Figure 19-11. Counter Operation in Decoder Mode 0 with Rising-Edge-Mode
574
Table 19-3. Counting Direction Versus Decoder Signals
574
Figure 19-12. Counter Operation in Decoder Mode 0 with Falling-Edge-Mode
575
Figure 19-13. Counter Operation in Decoder Mode 1 with Non-Inverted
576
Figure 19-14. Counter Operation in Decoder Mode 1 with Non-Inverted(IN1EIF)
576
Figure 19-15. Counter Operation in Decoder Mode 1 with Non-Inverted(IN0EIF)
577
Figure 19-16. Counter Operation in Decoder Mode 1 with Non-Inverted(INRFOEIF)
577
Figure 19-17. Counter Operation in Decoder Mode 1 with Non-Inverted(INHLOEIF)
577
Table 19-4. LPTIMER Works in Low-Power Modes
578
Table 19-5. LPTIMER Interrupt Events
579
Figure 20-1. USART Module Block Diagram
597
Table 20-1. Description of USART Important Pins
597
Figure 20-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
598
Table 20-2. Configuration of Stop Bits
598
Figure 20-3. USART Transmit Procedure
600
Figure 20-4. Oversampling Method of a Receive Frame Bit (OSB=0)
601
Figure 20-5. Configuration Step When Using DMA for USART Transmission
602
Figure 20-6. Configuration Step When Using DMA for USART Reception
603
Figure 20-7. Hardware Flow Control between Two Usarts
603
Figure 20-8. Hardware Flow Control
604
Figure 20-10. Break Frame Occurs During a Frame
606
Figure 20-9. Break Frame Occurs During Idle State
606
Figure 20-11. Example of USART in Synchronous Mode
607
Figure 20-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
607
Figure 20-13. Irda SIR ENDEC Module
608
Figure 20-14. Irda Data Modulation
608
Figure 20-15. ISO7816-3 Frame Format
609
Figure 20-16. USART Receive FIFO Structure
612
Table 20-3. USART Interrupt Requests
612
Figure 20-17. USART Interrupt Mapping Diagram
614
Table 21-1. Description of LPUART Important Pins
635
Figure 21-1. LPUART Module Block Diagram
636
Figure 21-2. LPUART Character Frame
636
Figure 21-3. LPUART Transmit Procedure
638
Figure 21-4. Configuration Step When Using DMA for LPUART Transmission
640
Figure 21-5. Configuration Step When Using DMA for LPUART Reception
641
Figure 21-6. Hardware Flow Control between Two Lpuarts
641
Figure 21-7. Hardware Flow Control
642
Table 21-2. the Driver Enable Assertion Time and De-Assertion Time
642
Table 21-3. LPUART Interrupt Requests
644
Figure 21-8. LPUART Interrupt Mapping Diagram
645
Figure 22-1. I2C Module Block Diagram
659
Table 22-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
660
Figure 22-2. Data Validation
661
Figure 22-3. START and STOP Signal
662
Figure 22-4. I2C Communication Flow with 10-Bit Address (Master Transmit)
662
Figure 22-5. I2C Communication Flow with 7-Bit Address (Master Transmit)
663
Figure 22-6. I2C Communication Flow with 7-Bit Address (Master Receive)
663
Figure 22-7. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
663
Figure 22-8. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
663
Figure 22-9. Data Hold Time
664
Figure 22-10. Data Setup Time
665
Table 22-2. Data Setup Time and Data Hold Time
666
Figure 22-11. Data Transmission
667
Figure 22-12. Data Reception
667
Table 22-3. Communication Modes to be Shut down
667
Figure 22-13. I2C Initialization in Slave Mode
670
Figure 22-14. Programming Model for Slave Transmitting When SS=0
671
Figure 22-15. Programming Model for Slave Transmitting When SS=1
672
Figure 22-16. Programming Model for Slave Receiving
673
Figure 22-17. I2C Initialization in Master Mode
674
Figure 22-18. Programming Model for Master Transmitting (N<=255)
675
Figure 22-19. Programming Model for Master Transmitting (N>255)
676
Figure 22-20. Programming Model for Master Receiving (N<=255)
677
Figure 22-21. Programming Model for Master Receiving (N>255)
678
Figure 22-22. Smbus Master Transmitter and Slave Receiver Communication Flow
682
Figure 22-23. Smbus Master Receiver and Slave Transmitter Communication Flow
682
Table 22-4. I2C Error Flags
683
Table 22-5. I2C Interrupt Events
683
Figure 23-1. Block Diagram of SPI
700
Table 23-1. SPI Signal Description
700
Table 23-2. Quad-SPI Signal Description
701
Figure 23-2. SPI0 Timing Diagram in Normal Mode
702
Figure 23-3. SPI0 Data Frame Right-Aligned Diagram
702
Figure 23-4. SPI1 Timing Diagram in Normal Mode
702
Figure 23-5. SPI0 Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
703
Figure 23-6. Transmission and Reception FIFO
703
Table 23-3. NSS Function in Slave Mode
704
Table 23-4. NSS Function in Master Mode
705
Table 23-5. SPI Operation Modes
706
Figure 23-7. a Typical Full-Duplex Connection
707
Figure 23-8. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
707
Figure 23-9. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
707
Figure 23-10. a Typical Bidirectional Connection
708
Figure 23-11. Timing Diagram of TI Master Mode with Discontinuous Transfer
710
Figure 23-12. Timing Diagram of TI Master Mode with Continuous Transfer
710
Figure 23-13. Timing Diagram of TI Slave Mode
711
Figure 23-14. Timing Diagram of NSS Pulse with Continuous Transmit
712
Figure 23-15. Timing Diagram of Quad Write Operation in Quad-SPI Mode
713
Figure 23-16. Timing Diagram of Quad Read Operation in Quad-SPI Mode
714
Table 23-6. SPI Interrupt Requests
717
Figure 23-17. Block Diagram of I2S
718
Figure 23-18. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
719
Figure 23-19. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
720
Figure 23-20. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
720
Figure 23-21. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
720
Figure 23-22. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
720
Figure 23-23. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
720
Figure 23-24. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
721
Figure 23-25. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
721
Figure 23-26. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
721
Figure 23-27. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
721
Figure 23-28. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
722
Figure 23-29. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
722
Figure 23-30. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
722
Figure 23-31. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
722
Figure 23-32. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
722
Figure 23-33. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
722
Figure 23-34. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
723
Figure 23-35. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
723
Figure 23-36. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
723
Figure 23-37. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
723
Figure 23-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
724
Figure 23-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
724
Figure 23-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
724
Figure 23-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
724
Figure 23-42. PCM Standard Short Frame Synchronization Mode Timing Diagram
724
Figure 23-43. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
725
Figure 23-44. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
725
Figure 23-45. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
725
Figure 23-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
725
Figure 23-47. PCM Standard Long Frame Synchronization Mode Timing Diagram
725
Figure 23-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
726
Figure 23-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
726
Figure 23-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
726
Figure 23-51. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
726
Figure 23-52. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
726
Figure 23-53. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
727
Figure 23-54. Block Diagram of I2S Clock Generator
727
Table 23-7. I2S Bitrate Calculation Formulas
727
Table 23-8. Audio Sampling Frequency Calculation Formulas
728
Table 23-9. Direction of I2S Interface Signals for each Operation Mode
728
Figure 23-55. I2S Initialization Sequence
729
Figure 23-56. I2S Master Reception Disabling Sequence
731
Table 23-10. I2S Interrupt
733
Figure 24-1. Precision Reference Connection for Gd32L233Xx
746
Figure 24-2. Precision Reference Connection for Gd32L235Xx
747
Table 24-1 VREF MODES
747
Figure 25-1. SLCD Block Diagram
751
Figure 25-2. 1/3 Bias, 1/4 Duty
752
Table 25-1. the Odd Frame Voltage
753
Table 25-2. the Even Frame Voltage
753
Table 25-3. the All Common Signal Driver
753
Figure 25-3. 1/4 Bias, 1/6 Duty
754
Figure 25-4. SLCD Dead Time (1/3 Bias, 1/4 Duty)
754
Figure 25-5. SLCD Resistr Divider Network for GD32L233 Series
756
Figure 25-6. SLCD Resistr Divider Network for GD32L235 Series
756
Figure 26-1. CMP Block Diagram
771
Table 26-1 CMP Inputs and Outputs Summary
772
Figure 26-2. CMP Hysteresis
773
Figure 26-3 the CMP Outputs Signal Blanking
774
Figure 27-1. CAN Module Block Diagram
781
Figure 27-2. Transmission Register
783
Figure 27-3. State of Transmit Mailbox
784
Figure 27-4. Reception Register
785
Figure 27-5. 32-Bit Filter
786
Figure 27-10. 16-Bit List Mode Filter
787
Figure 27-6. 16-Bit Filter
787
Figure 27-7. 32-Bit Mask Mode Filter
787
Figure 27-8. 16-Bit Mask Mode Filter
787
Figure 27-9. 32-Bit List Mode Filter
787
Table 27-1. 32-Bit Filter Number
787
Table 27-2. Filtering Index
789
Figure 27-11. the Bit Time
791
Figure 28-1. USBD Block Diagram
813
Table 28-1. USBD Signal Description
814
Figure 28-2. an Example with Buffer Descriptor Table Usage (USBD_BADDR = 0)
816
Table 28-2. Double-Buffering Buffer Flag Definition
817
Table 28-3. Double Buffer Usage
817
Table 28-4. Reception Status Encoding
830
Table 28-5. Endpoint Type Encoding
830
Table 28-6. Endpoint Kind Meaning
830
Table 28-7. Transmission Status Encoding
830
Table 29-1. List of Abbreviations Used in Register
835
Table 29-2. List of Terms
835
Table 30-1. Revision History
836
Advertisement
Advertisement
Related Products
GigaDevice Semiconductor GD32L23 Series
GigaDevice Semiconductor GD32L233K-START
GigaDevice Semiconductor GD32L235 Series
GigaDevice Semiconductor GD32E23 Series
GigaDevice Semiconductor GD32F30 Series
GigaDevice Semiconductor GD32E503
GigaDevice Semiconductor GD32E51 Series
GigaDevice Semiconductor GD32G553
GigaDevice Semiconductor GD32E513 Series
GigaDevice Semiconductor GD32F3x0
GigaDevice Semiconductor Categories
Microcontrollers
Computer Hardware
Motherboard
Semiconductors
Adapter
More GigaDevice Semiconductor Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL