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SECTION
II
Theory of Operation
2-1.
FUNCTIONAL DESCRIPTION
2-3.
The PMS consists of 5 primary circuits:
Buffer Circuit
MAR (Memory Address Register)
I/0 Decode Logic
RAM (Random Access Memory)
Power Supply
2-4,
The PMS is organized into 2 major assemblies:
2 8K-Byte banks of RAM
Power Supply
Address/Latch Counter
Timing Logic
Control Logic
Bank Enable Logic
Enable Clock Logic
Write Enable Logic
RAM Select Logic
Bidirectional Buffer
0 Unidirectional Buffer
0 EMI (Electro-Magnetic Interference) circuit
o Cable
2-1
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