Advertisement
Theory of Operation
HP 82713A
2-23.
The Bank Enable Logic decodes the I/0 address to determine which
bank is being addressed. Only 2 addresses in the range FF40- FFU4F will
will enable a bank of RAM. (see table 2-1). Either bank can be enabled
by a read or write to the appropriate I/0 address. Any bank not being
addressed when a clock pulse is recieved from the Enable Clock Logic
will be disabled. When a bank is enabled by this circuit and the enable
write (EW) line is not asserted, the bank can only be read from.
PWO
ry)CE rr
a
5
3H
2
$2
—
—
uD
a2
: Jur
elo alo
A3
Ul4
AD
D
SH
EB
FF4X
AO
CLK3
Figure 2-9.
Bank Enable Logic
2-24,
The Write Enable Logic allows the RAM to be written to. This circuicv
is set by accessing any even address the Enable Clock Logic recognizes.
(see table 2-1). The HP=T5 can write to the PMS when the enable write
(EW) line is asserted and a bank is selected (from the Bank Enable
Logic).
am——
5
4
'
READ
9 vio
D
Q
AD
Ute
Figure 2-8.
Write Enable Logic
2-8
Advertisement
