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HP 82T713A
Theory of Operation
[ET
Figure 2-6.
RAM Select Logic
2-19.
I/0 Decode Logic
2-20.
The I/0 Decode Logic consists of 3 circuits:
o Enable Clock Logic
o Bank Enable Logic
0 Write Enable Logic
2-21.
The I/0 Decode Logic monitors the address lines and several control
control lines from the HP-T75 bus. It decodes this information and enables
or disables the appropriate bank of RAM. It also determines whether the
bank is to be read or written to.
2-22.
The Enable Clock Logic monitors
the address lines looking for an
address in the range FF40 to FFU4F, and any even address in the range
FF50 to FF5F. If either a read or write command is issued to any of these
addresses, a clock pulse is generated to the Bank Enable Logic, and the
Write &nable Logic.
FF A7 AW FF4aX
9
¢
/
2
3
Ul
us
CLK3
4
Aa —LUa
5
AS —3248
6
Ae —3c
7
AO
Figure 2-7.
Enable Clock Logic
2-7
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