Processor Technology 8KRA Assembly And Test Instructions page 54

CALI
RETURN
JUMP
C3 JMP 1
CD CALL^
C9 RET .
C2 JNZ
C4 CNZ CO RNZ
CA JZ
CC CZ C8 RZ
02 JNC
D4 CNC DO RNC
DA JC
* Ad
DC CC 1 Adr D8 RC
E2 JPO
E4 CPO EO RPO
EA JPE EC CPE
E8 RPE
F2 JP
F4 CP FO RP
FA JM J
FC CM j F8 RM
ES PCHL
MOVE Acc
LOAD
IMMEDIATE
IMMEDIATE* IMMEDIATE
06 MVI B '
C6 ADI ' 01 LXI 8
OE MVI C. CE ACI
11 LXI D.
16 MVI O 06 SUI
21 LXI H
IE MVI E
I Dfi DE SBI
D8 31 LXI SP.
26 MVI
H
' D8 E6 ANI
2E MVI L EE XRI
36 MVI M F6 ORI
3E
MVI ' A ,
FE CPI >
DOUBLE ADD*
09 DAD 8
19 DAD D
29 DAO H
INCREMENT
DECREMENT** 39 DAD SP
04 INR
£3 05 DCR B
0C INR C OD DCR C
14 INR 0 15 DCR
D LOAD/STORE
1C INR
E ID OCR E
' 4 INR H 25 DCR H QA LDAX B
2C INR
L 2D DCR L 1 A LDAX D
34 INR M 35 DCR M 2A LHLD Adr
3C INR A 3D DCR A 3A LOA Adr
03 INX B OB OCX 8 02 STAX 8
13 INX D 18 OCX D 12 STAX D
23 INX
H
28 OCX
H 22 SHLD Adr
33 INX SP 38 DCX
SP 32 STA Adr
08 constant, or logical arithmetic expression that evaluates
to an 8 bit data quantity
• ail Flags IC.Z.S.Pl affected
RESTART ROTATE* MOVE (cont) ACCUMULATOR
C7 RST 0 07 RLC 58
CF RST 1 OF RRC 59
07 RST 2 17 RAL SA
DF RST 3 IF RAR 58
E7 RST 4 SC
EF RST 5 5D
F7 RST 6 SE
FF RST 7
CONTROL
5F
00 NOP
60
76 HLT
61
F3 DI
62
FB El
63
64
STACK OPS
65
66
C5 PUSH 8
MOVE
67
DS
PUSH D
D16 E5
PUSH H
40 MOV 8.8 68
F5
PUSH PSW
41 MOV B.C 69
42 MOV B.D 6A
Cl POP 8
43 MOV B.E 68
Di POP D
44 MOV B.H 6C
El POP
H
45 MOV B.L
6D
Fl
POP
PSW
46
MOV B.M 6E
47 MOV 8. A 6F
E3 XTHL
48 MOV C.B
70
F9 SPHL
49 MOV C.C
71
4A
MOV CD
72
48
MOV C.E
73
SPECIALS
4C MOV C.H
74
4D MOV
C.L
75
E8 XCHG
4E MOV CM
27 DAA"
4F MOV C.A
77
2F CMA
37 STC» 50 MOV D.B 78
3F CMC» 51 MOV DC 79
52 MOV D.D 7A
53 MOV DE 78
INPUT/OUTPUT
54 MOV O.H 7C
55 MOV D.L 7D
D3 OUT D8 56 MOV DM 7E
08
IN
D8
57
MOV D.A 7F
MOV E 8 80 ADD
8
AS XRA B
MOV E.C 81 ADD C AS XRA C
MOV ED 82 ADD D AA XRA 0
MOV E.E 83 ADD E AB XRA E
MOV E.H
84
ADD
H
AC XRA H
MOV E.L 85 ADD L AD XRA L
MOV EM 86 ADD M AE XRA M
MOV E.A
87
ADD
A
AF XRA A
MOV H.B 88 ADC B BO ORA
B
MOV H.C 89 ADC C Bl ORA c
MOV H.D 8A ADC D 82 ORA D
MOV H.E 8B ADC E 83 ORA E
MOV H.H 8C ADC
H B4
ORA H
MOV H.L 8D ADC L 85 ORA L
MOV H.M
SE
ADC
M
86 ORA M
MOV H.A
8F
ADC
A 87
ORA A
MOV LB 90 SUB 8 BS CMP B
MOV L.C 91 SUB C BS CMP C
MOV L.D 92 SUB D
BA
CMP D
MOV L.E 93 SUB E BB CMP E
MOV L.H 94
SUB
H BC CMP
H
MOV L.L 95 SUB L BD CMP
L
MOV L.M 96 SUB M BE CMP M
MOV LA 97 SUB
A BF
CMP A
MOV MB 98 SBB 8
MOV M.C 99 S8B C
PSEUDO
MOV M.D
9A
SBB D
INSTRUCTION
MOV M.E
98 SBB
E
MOV
M.H SC SBB H
ORG
Adr
MOV
ML
9D SBB L
END
SE SBB M
EOU D16
MOV MA 9F SBB A
DS
D16
MOV A.B AO ANA B DB
08 1 1
MOV AC Al ANA C DW
016 I 1
MOV A.D A 2 ANA 0
MOV A.E A3 ANA E
MOV A.H A4 ANA H
MOV A.L A5 ANA L
MOV A.M A6 ANA M
MOV A,A
A7
ANA
A
CONSTANT
DEFINITION
OBDH
1AH
Hex
1050
105
Decimal
720
720
Octal
110118
001108
Binary
TEST
A B
ASCII
OPERATORS
STANDARD
SETS
A SET 7
8 SET 0
C SET 1
D SET 2
E SET 3
H SET 4
L SET 5
M SET 6
SP SET 6
PSWSET 6
D16 » constant, or logical/arithmetic expression that evaluates
to a 16 bit data quantity
» « only CARRY affected
Adr -- 16 bit address
" = all Flags except CARRY affected;
(exception INX & OCX affect no Flags)
AP 1DIX
TT-2