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PROCESSOR TECHNOLOGY CORPORATION
8KRA STATIC READ/WRITE MEMORY MODULE
SECTION IV
Al 2 bits in the module address to the actual corresponding bus ad
dress bits in order to provide the page selection inputs (A, B, C)
for IC67, a 3-to-8 line decoder.
The fourth section in IC68 adds
any carry from the Al 2 addition and the Al 3 bus address bit to pro
vide the input on pin 1 of IC70.
The first two sections of IC71 add
"1" to the A14 and Al 5 bits in the module address and supply the sums
to pins 4 and 10 of IC70.
Since the Address Switches reflect the complement of the three
most significant bits in the module address, the three corresponding
outputs of IC68 and IC71 will reflect the Al 3 through Al 5 bits in the
module address if, and only if, that address is presented on the ad
dress lines.
When this is the case, pins 3, 6
and 8 of IC70 are
high, as will be the output on pin 13 of IC71.
(Pin 13 of IC71 is
low only if an address not within the selected range for the module
appears on the address lines.)
Pin 11 of IC70 will also be high for
a read (or write) operation.
(Note that the fourth section in IC70
is used only to invert SOUT.)
Pin 6 of IC72 and pin 8 of IC75 are now low by virtue of SMEMR
and PDBIN being high, pin 10 of IC71 is high, and the wire OR'ed out
put of IC70 is high.
The low on pin 6 of 1072 enables the data-in
bus (DI0 through DI7 ) drivers, IC69 and IC76.
The low on pin 8 of
IC75 provides the second enable required by IC67 to decode its inputs
and enable the eight RAM's in the selected page.
If the 8KRA is used at address zero with a Processor Technology
ALL-8 Firmware Module, the Area C jumper will be in.
When the ALL-8
generates PHANTOM, the B2 (pin 2) input to IC71 goes low.
The output
on pin 13 will be low for all combinations of Al 4 and A15.
Pins 8_
and 6 of IC72 and pin 8 of IC75 will thus all be high to disable WE,
IC67 and the data input bus drivers, IC69 and IC76.
That is, the
8KRA is disabled.
4.3
WRITE OPERATION
A write operation is similar to the read operation except MWRT
is high instead of SMEMR.
IC69 and IC76 are disabled and pin 13 of
1069 is low for the duration of the MWRT pulse.
The CPU controls the
timing of this pulse.
With pin 13 of 1069 low, all RAM's are partial
ly enabled to read data from the DO bus.
The page to be written into
is selected by A10 and All.
In order for pin 13 of 1069 to be low, pin 6 of IC75 must be
high and the module must be selected (all outputs of 1070 and the Z3
output of 1071 are high).
Three gates in IC75 and one in 1074 are
connected as a latch which is set or reset by the PROT and UNPROT
signals on Bus Pins 70 and 20.
When PROT goes high to set the latch,
pin 3 of 1075 goes high and pin 6 of 1075 goes low.
This low inhib
its WE and provides an active low PS signal on pin 13 of 1076.
A low
PZ^ turns the computer PROT light on to indicate that the page of
IV- 2
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