Processor Technology 8KRA Assembly And Test Instructions page 46

PROCESSOR TECHNOLOGY CORPORATION
8KRA STATIC READ/WRITE MEMORY MODULE
APPENDIX VI
( ) Step 1 . (continued)
NOTE 2
When the 8KRA is not being tested, it
can be addressed at any of the sixty-
four 1K intervals specified in Table
3-1 in Section III of this manual.
( ) Step 2 . Load test program into memory starting at location
0000.
( ) Step 3 . Set the starting address selected in Step 1 for the
8KRA to be tested into Sense Switches 13 through 15. (These
Sense Switches are set to the highest order bits that are
recognized by the 8KRA under test; namely A15, A14 and A13.)
NOTE
Sense Switch settings for the seven possible starting address ­
es are as follows:
ADDRESS
(Hex)
SENSE SWITCH SETTINGS
15 14 13
2000 Down Down Up
4000 Down Up Down
6000 Down Up Up
8000 Up Down
Down
A000 Up
Down Up
C000 Up
Up Down
E000 Up
Up Up
( ) Step
that
4. Start test by pressing
order.
RESET and RUN Switches in
The test takes several minutes to run.
When the test is done, a print routine
will print a map that corresponds to
the memory IC layout of the 8KRA board;
that is, four rows of sixteen.
( ) Step 5 . Analyze the map to determine which bits are defec ­
tive. An example follows:
IC1_ Page No. 7654321001234567 y —
~ Bit 0 XGGGGGGGGGGGGGGG *- Bit 4
Bit 1 — GGGGGGGGGGGGGGGG Bit 5
Bit 2 - GGGGGGGGGGGGGGGG - Bit 6
IC49
Bit 3 XGGGGGGGGGGGGGGGBit 7 IC64
AVI -4