Tektronix DC 501 Instruction Manual page 8

19B 27A25B
24B
19A, 20A, 20B, 21B
J100
I
INPUT iATTEM-
16A>-
SIGNAL-SHAPING
0115
CIRCUIT
0160 U135
0122 U150A U1606
0128 U150B 0170
TRIGGER
LEVEL
I'
DISPLAY
TIME.
I
DISPLAY TIME
|
CONTROL
0230 0238
0240
1-MHz
CLOCK
Y200
U200A U200C
U200B U200D
OPTIONAL
1-MHz
CLOCK
Y201
U201
I
J
I
J
REGULATED
SUPPLIES
+20
V >-
-20
vV
1
U300
1
>
1
1
1
1
s
1
U320 4-f
^
1
.
1
*
1
1
0330
'
1
0340
+
15
V|
REG
GATE GENERATOR
U220A U222A
U220B
U222B
CONTROL
SIGNALS
U230A
U230B
U230C
U230D
U246D
GATE
LATCH
CLEAR
CLEAR
RESET
DECADE
DIVIDER
UNITS
U209
U210
U211
U212
U213
U214
U215
.01
SEC
.1
SEC
1
SEC
10
SEC
MEAS
INTER
SWITCH
S200
•
+5
V REG
—
5.2
V REG
-10
V REG
.1
S-
-
1
S
—
IDS
—
-
MSD
—
OPTIONAL
AUTO-GATE
&
READOUT
SCALING
CIRCUIT
10" DCU STORAGE
U165A
REGISTER
U1656 U250
U167 U251
U169 U252
U253
10'
DCU
U254
U235
U255
U256
10'
DCU
U236
10^
DCU
U237
10"
DCU
U238
10' DCU
U239
10"
DCU
U240
OVERFLOW]
I
REGISTER
U241A
U241B
0242
OVERFLOW
RESET
,U18
U181
U183
U185
U190
U19^
To
Gate
'
Generator
.
To
Display
Circuits
LEADING-ZERO
SUPPRESSION
&
I
DECIMAL
POINT
LOCATION
U245B
U246A
U246B
U260C
U263B
INVERTERS
U246C U267D
U267A U267E
U267B U267F
U267C
ANODE
VOLTAGE
ENABLE
0280
0283
0281 0284
0282 0285
0286
Fig. 2-1.
DC
501 Block
Diagram.
Theory
of
Operation—
DC
501