ARTERY AT32F425 Series Manuals

Manuals and User Guides for ARTERY AT32F425 Series. We have 2 ARTERY AT32F425 Series manuals available for free PDF download: Reference Manual, Manual

ARTERY AT32F425 Series Reference Manual (429 pages)

ARM-based 32-bit Cortex-M4F MCU with 32 to 64 KB Flash, sLib, CAN, OTGFS, 13 timers, ADC, 12 communication interfaces

Brand: ARTERY | Category: Computer Hardware | Size: 6 MB

Table of Contents
2
System Architecture
30
Figure 1-1 AT32F425 Series Microcontrollers System Architecture
31
System Overview
32
ARM Cortex
32
TM -M4 Processor
32
Bit Band
32
Figure 1-2 Internal Block Diagram of Cortex ® -M4
32
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
32
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
33
Table 1-1 Bit-Band Address Mapping in SRAM
33
Interrupt and Exception Vectors
34
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
34
Table 1-3 AT32F425 Series Vector Table
34
System Tick (Systick)
36
Reset
36
Figure 1-5 Reset Process
36
Figure 1-6 Example of MSP and PC Initialization
37
List of Abbreviations for Registers
38
Device Characteristics Information
38
Flash Memory Size Register
38
Device Electronic Signature
38
Table 1-3 List of Abbreviations for Registers
38
Table 1-4 List of Abbreviations for Registers
38
Memory Resources
39
Internal Memory Address Map
39
Figure 2-1AT32F425 Address Mapping
39
Flash Memory
40
SRAM Memory
40
Table 2-1 Flash Memory Organization (64 KB)
40
Table 2-2 Flash Memory Organization (64 KB)
40
Peripheral Address Map
41
Table 2-3 Peripheral Boundary Address
41
Power Control (PWC)
43
Introduction
43
Main Features
43
Figure 3-1 Block Diagram of each Power Supply
43
Por/Lvr
44
Power Voltage Monitor (PVM)
44
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
44
Figure 3-3 PVM Threshold and Output
44
Power Domain
45
Power Saving Modes
45
PWC Registers
46
Table 3-1 PW Register Map and Reset Values
46
Power Control Register (PWC_CTRL)
47
Power Control/Status Register (PWC_CTRLSTS)
47
Power Control Register2 (PWC_CTRL2)
48
Clock and Reset Manage (CRM)
49
Clock
49
Clock Sources
49
Figure 4-1 AT32F425 Clock Tree
49
System Clock
50
Peripheral Clock
50
Clock Fail Detector
51
Clock Output
51
Interrupts
51
Reset
51
System Reset
51
Battery Powered Domain Reset
52
CRM Registers
52
Figure 4-2 System Reset Circuit
52
Table 4-1 CRM Register Map and Reset Values
52
Clock Control Register (CRM_CTRL)
53
Clock Configuration Register (CRM_CFG)
54
Clock Interrupt Register (CRM_CLKINT)
55
APB2 Peripheral Reset Register (CRM_APB2RST)
57
APB1 Peripheral Reset Register1 (CRM_APB1RST)
57
APB Peripheral Clock Enable Register (CRM_AHBEN)
58
APB2 Peripheral Clock Enable Register (CRM_AHB2EN)
59
APB1 Peripheral Clock Enable Register (CRM_AHB1EN)
60
Battery Powered Domain Control Register (CRM_BPDC)
61
Control/Status Register (CRM_CTRLSTS)
61
APB Peripheral Reset Register (CRM_APBRST)
62
PLL Configuration Register (CRM_PLL)
62
Additional Register1 (CRM_MISC1)
63
Additional Register2 (CRM_MISC2)
64
Flash Memory Controller (FLASH)
65
FLASH Introduction
65
Table 5-1 Flash Memory Architecture(64 K)
65
Table 5-2 Flash Memory Architecture(32 K)
65
Table 5-3 User System Data Area
65
Flash Memory Operation
67
Unlock/Lock
67
Erase Operation
67
Figure 5-1 Flash Memory Page Erase Process
68
Programming Operation
69
Figure 5-2 Flash Memory Mass Erase Process
69
Read Operation
70
Main Flash Memory Extension Area
70
User System Data Area Operation
70
Unlock/Lock
70
Figure 5-3 Flash Memory Programming Process
70
Erase Operation
71
Programming Operation
72
Figure 5-4 System Data Area Erase Process
72
Read Operation
73
Flash Memory Protection
73
Access Protection
73
Figure 5-5 System Data Area Programming Process
73
Erase/Program Protection
74
Table 5-4 Flash Memory Access Limit
74
Special Functions
75
Security Library Settings
75
Bootloader Code Area Used as Flash Memory Extension
76
CRC Verify
76
Flash Memory Registers
76
Table 5-5 Flash Memory Interface-Register Map and Reset Value
76
Flash Performance Select Register (FLASH_PSR)
77
Flash Unlock Register (FLASH_UNLOCK)
77
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
78
Flash Status Register (FLASH_STS)
78
Flash Control Register (FLASH_CTRL)
78
Flash Address Register (FLASH_ADDR)
79
User System Data Register (FLASH_USD)
79
Erase/Program Protection Status Register (FLASH_EPPS)
80
Flash Security Library Status Register0 (SLIB_STS0)
80
Flash Security Library Status Register1 (SLIB_STS1)
80
Security Library Password Cle Ar Register (SLIB_PWD_CLR)
81
Security Library Additional Status Register (SLIB_MISC_STS)
81
Flash CRC Address Register (FLASH_CRC_ARR)
81
Flash CRC Control Register (FLASH_CRC_CTRL)
81
Flash CRC Check Result Register (FLASH_CRC_CHKR)
82
Security Library Password Setting Register (SLIB_SET_PWD)
82
Security Library Address Setting Register (SLIB_SET_RANGE)
82
Boot Mode Setting Register (BTM_MODE_SET)
83
Security Library Unlock Register (FLASH_UNLOCK)
83
Gpios and IOMUX
84
Introduction
84
Function Overview
84
GPIO Structure
84
Figure 6-1 GPIO Basic Structure
84
GPIO Reset Status
85
General-Purpose Input Configuration
85
Analog Input/Output Configuration
85
General-Purpose Output Configuration
85
GPIO Port Protection
86
IOMUX Structure
86
Multiplexed Function Pull-Up/Down Configuration
86
Figure 6-2 IOMUX Structure
86
IOMUX Input/Output
87
Table 6-1 Port a Multiplexed Function Configuration with GPIOA_MUX* Register
87
Table 6-2 Port B Multiplexed Function Configuration with GPIOB_MUX* Register
88
Table 6-3 Port C Multiplexed Function Configuration with GPIOC_MUX* Register
89
Table 6-4 Port D Multiplexed Function Configuration with GPIOD_MUX* Register
89
Table 6-5 Port E Multiplexed Function Configuration with GPIOE_MUX* Register
89
Peripheral MUX Function Configuration
90
IOMUX Mapping Priority
90
External Interrupt/Wake-Up Lines
90
GPIO Registers
90
Table 6-6 Pins Owned by Hardware
90
Table 6-7 GPIO Register Map and Reset Values
90
GPIO Configuration Register (Gpiox_Cfgr) (X=A/B/C/D/F)
91
GPIO Output Mode Register (Gpiox_Omoder) (X=A/B/C/D/F)
91
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A/B/C/D/F)
91
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A/B/C/D/F)
91
GPIO Input Register (Gpiox_Idh) (X=A/B/C/D/F)
92
GPIO Output Register (Gpiox_Idh) (X= A/B/C/D/F)
92
GPIO Set/Clear Register (Gpiox_Scr) (X=A/B/C/D/F)
92
GPIO Write Protection Register (Gpiox_Wpr) (X=A/B/C/D/F)
92
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X= A/B/C/D/F)
93
GPIO Port Bit Clear Register (Gpiox_Clr) (X=A/B/C/D/F)
93
GPIO Huge Current Control Register (Gpiox_Hdrv) (X= A/B/C/D/F)
93
System Configuration Controller (SCFG)
94
Introduction
94
SCFG Registers
94
SCFG Configuration Register1 (SCFG_CFG1)
94
Table 7-1 SCFG Register Map and Reset Values
94
SCFG External Interrupt Configuration Register1 (SCFG_ EXINTC1)
95
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)
96
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)
97
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)
97
SCFG Configuration Register2 (SCFG_CFG2)
98
External Interrupt/Event Controller (EXINT)
99
EXINT Introduction
99
Function Overview and Configuration Procedure
99
Figure 8-1 External Interrupt/Event Controller Block Diagram
99
EXINT Registers
100
Interrupt Enable Register (EXINT_INTEN)
100
Event Enable Register (EXINT_EVTEN)
100
Polarity Configuration Register1 (EXINT_ POLCFG1)
100
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
100
Polarity Configuration Register2 (EXINT_ POLCFG2)
101
Software Trigger Register (EXINT_ SWTRG)
101
Interrupt Status Register (EXINT_ INTSTS)
101
DMA Controller (DMA)
102
Introduction
102
Main Features
102
Function Overview
102
DMA Configuration
102
Figure 9-1 DMA Block Diagram
102
Handshake Mechanism
103
Arbiter
103
Programmable Data Transfer Width
103
Figure 9-2 Re-Arbitrae after Request/Acknowledge
103
Errors
104
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
104
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
104
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
104
Table 9-1 DMA Error Event
104
Interrupts
105
Flexible DMA Request Mapping
105
Table 9-2 DMA Interrupt Requests
105
Table 9-3 DMA Flexible Request Sources
105
DMA Registers
106
Table 9-4 DMA Register Map and Reset Value
106
DMA Interrupt Status Register (DMA_STS)
107
DMA Interrupt Flag Clear Register (DMA_CLR)
108
DMA Channel-X Configuration Register (Dma_Cxctrl ) (X = 1
110
DMA Channel-X Number of Data Register (Dma_Cxdtcnt)
111
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr)
111
DMA Channel-X Memory Address Register (Dma_Cxmaddr)
111
DMA Channel Source Register (DMA_SRC_SEL0)
112
DMA Channel Source Register1 (DMA_SRC_SEL1)
112
CRC Calculation Unit (CRC)
113
CRC Introduction
113
CRC Registers
113
Data Register (CRC_DT)
113
Common Data Register (CRC_CDT)
113
Table 10-1 CRC Register Map and Reset Value
113
Control Register (CRC_CTRL)
114
Initialization Register (CRC_IDT)
114
C Interface
115
I 2 C Introduction
115
I 2 C Main Features
115
I 2 C Function Overview
115
Figure 11-1 I C Bus Protocol
115
I 2 C Interface
116
Figure 11-2 I2C Function Block Diagram
116
C Timing Control
118
Figure 11-3 Setup and Hold Time
118
Data Transfer Management
119
Table 11-1 I C Timing Specifications
119
C Master Communication Flow
120
Table 11-2 I 2 C Configuration Table
120
Figure 11-4 I 2 C Master Transmission Flow
122
Figure 11-5 Transfer Sequence of I
123
Figure 11-6 I 2 C Master Receive Flow
123
Figure 11-7 Transfer Sequence of I
124
Figure 11-8 10-Bit Address Read Access When READH10=1
124
Figure 11-9 10-Bit Address Read Access When READH10=0
124
C Slave Communication Flow
125
Figure 11-10 I 2 C Slave Transmission Flow
127
Figure 11-11 I 2 C Slave Transmission Timing
127
Figure 11-12 I 2 C Slave Receive Flow
128
Figure 11-13 I 2 C Slave Receive Timing
128
Smbus
129
Table 11-3 Smbus Timeout Specification
130
Table 11-4 Smbus Timeout Detection Configuration
130
Smbus Master Communication Flow
131
Table 11-5 Smbus Mode Configuration
131
Figure 11-14 Smbus Master Transmission Flow
133
Figure 11-15 Smbus Master Transmission Timing
134
Figure 11-16 Smbus Master Receive Flow
134
Smbus Slave Communication Flow
135
Figure 11-17 Smbus Master Receive Timing
135
Figure 11-18 Smbus Slave Transmission Flow
137
Figure 11-19 Smbus Slave Transmission Timing
137
Figure 11-20 Smbus Slave Receive Flow
138
Figure 11-21 Smbus Slave Receive Timing
138
Data Transfer Using DMA
139
Error Management
139
Table 11-6 I 2 C Error Events
139
I 2 C Interrupt Requests
141
I 2 C Debug Mode
141
I 2 C Registers
141
Table 11-7 I 2 C Interrupt Requests
141
Table 11-8 I 2 C Register Map and Reset Values
141
Control Register1 (I2C_CTRL1)
142
Control Register2 (I2C_CTRL2)
143
Own Address Register1 (I2C_OADDR1)
143
Own Address Register2 (I2C_OADDR2)
144
Timing Register (I2C_CLKCTRL)
144
Timeout Register (I2C_TIMEOUT)
144
Status Register (I2C_STS)
145
Status Clear Register (I2C_CLR)
146
PEC Register (I2C_PEC)
146
Receive Data Register (I2C_RXDT)
146
Transmit Data Register (I2C_TXDT)
146
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
147
USART Introduction
147
Figure 12-1 USART Block Diagram
147
Full-Duplex/Half-Duplex Selector
149
Mode Selector
149
Introduction
149
Configuration Procedure
149
USART Frame Format and Configuration
150
DMA Transfer Introduction
150
Transmission Using DMA
150
Reception Using DMA
150
Baud Rate Generation
151
Introduction
151
Configuration
151
Table 12-1 Error Calculation for Programmed Baud Rate
151
Transmitter
152
Transmitter Introduction
152
Transmitter Configuration
152
Receiver
152
Receiver Introduction
152
Receiver Configuration
153
Start Bit and Noise Detection
154
Tx/Rx Swap
154
Table 12-2 Data Sampling over Start Bit and Noise Detection
154
Table 12-3 Data Sampling over Valid Data and Noise Detection
154
Interrupt Requests
155
Figure 12-2 Tx/Rx Swap
155
Figure 12-3 USART Interrupt Map Diagram
155
Table 12-4 USART Interrupt Request
155
I/O Pin Control
156
USART Registers
156
Status Register (USART_STS)
156
Table 12-5 USART Register Map and Reset Value
156
Data Register (USART_DT)
157
Baud Rate Register (USART_BAUDR)
157
Control Register1 (USART_CTRL1)
157
Control Register2 (USART_CTRL2)
159
Control Register3 (USART_CTRL3)
160
Guard Time and Divider Register (USART_GDIV)
161
Serial Peripheral Interface (SPI)
162
SPI Introduction
162
Function Overview
162
SPI Description
162
Figure 13-1 SPI Block Diagram
162
Full-Duplex/Half-Duplex Selector
163
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
163
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
164
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
164
Chip Select Controller
165
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
165
SPI_SCK Controller
166
Crc
166
DMA Transfer
167
TI Mode
167
Transmitter
168
Receiver
168
Motorola Mode
169
Figure 13-6 Master Full-Duplex Communications
169
Figure 13-7 Slave Full-Duplex Communications
170
Figure 13-8 Master Half-Duplex Transmit
170
Figure 13-9 Slave Half-Duplex Receive
170
TI Mode
171
Figure 13-10 Slave Half-Duplex Transmit
171
Figure 13-11 Master Half-Duplex Receive
171
Figure 13-12 TI Mode Continous Transfer
171
Interrupts
172
IO Pin Control
172
Figure 13-13 TI Mode Continous Transfer with Dummy CLK
172
Figure 13-14 TI Mode Continous Transfer with Dummy CLK
172
Figure 13-15 SPI Interrupts
172
Precautions
173
I 2 S Functional Description
173
S Introduction
173
Figure 13-16 I 2 S Block Diagram
173
S Full-Duplex
174
Operating Mode Selector
174
Figure 13-17 I 2 S Full-Duplex Structure
174
Figure 13-18 I 2 S Slave Device Transmission
175
Figure 13-19 I 2 S Slave Device Reception
175
Figure 13-20 I 2 S Master Device Transmission
175
Audio Protocol Selector
176
Figure 13-21 I S Master Device Reception
176
I2S_CLK Controller
177
Figure 13-22 CK & MCK Source in Master Mode
177
DMA Transfer
178
Table 13-1 Audio Frequency Precision Using System Clock
178
Transmitter/Receiver
179
I2S Communication Timings
179
Interrupts
180
IO Pin Control
180
Figure 13-23 Audio Standard Timings
180
Figure 13-24 I 2 S Interrupts
180
SPI Registers
181
SPI Control Register1 (SPI_CTRL1)
181
Mode
181
Table 13-2 SPI Register Map and Reset Value
181
SPI Control Register2 (SPI_CTRL2)
182
SPI Status Register (SPI_STS)
183
SPI Data Register (SPI_DT)
184
SPICRC Register (SPI_CPOLY)
184
Mode)
184
Spirxcrc Register (SPI_RCRC) (Not Used in I S Mode)
184
Spitxcrc Register (SPI_TCRC)
184
SPI_I2S Register (SPI_I2SCTRL)
184
SPI_I2S Prescaler Register (SPI_I2SCLKP)
185
Timer
186
Table 14-1 TMR Functional Comparison
186
Basic Timer (TMR6 and TMR7)
187
TMR6 and TMR7 Introduction
187
TMR6 and TMR7 Main Features
187
TMR6 and TMR7 Function Overview
187
Count Clock
187
Counting Mode
187
Figure 14-1 Basic Timer Block Diagram
187
Figure 14-2 Control Circuit with CK_INT Divided by 1
187
Debug Mode
188
TMR6 and TMR7 Registers
188
TMR6 and TMR7 Control Register1 (Tmrx_Ctrl1)
188
Figure 14-3 Overflow Event When PRBEN=0
188
Figure 14-4 Overflow Event When PRBEN=1
188
Figure 14-5 Counting Timing Diagram When the Prescaler Division Is 4
188
Table 14-2 TMR6 and TMR7- Register Table and Reset Value
188
TMR6 and TMR7 Control Register2 (Tmrx_Ctrl2)
189
TMR6 and TMR7 Dma/Interrupt Enable Register (Tmrx_Iden)
189
TMR6 and TMR7 Interrupt Status Register (Tmrx_Ists)
189
TMR6 and TMR7 Software Event Register (Tmrx_Swevt)
190
TMR6 and TMR7 Counter Value (Tmrx_Cval)
190
TMR6 and TMR7 Division (Tmrx_Div)
190
TMR6 and TMR7 Period Register (Tmrx_Pr)
190
General-Purpose Timer (TMR2 and TMR3)
190
TMR2 and TMR3 Introduction
190
TMR2 and TMR3 Main Features
190
TMR2 and TMR3 Functional Overview
191
Count Clock
191
Figure 14-6 General-Purpose Timer Block Diagram
191
Figure 14-7 Control Circuit with CK_INT Divided by 1
191
Figure 14-8 Block Diagram of External Clock Mode a
191
Figure 14-9 Counting in External Clock Mode a
192
Figure 14-10 Block Diagram of External Clock Mode B
192
Figure 14-11 Counting in External Clock Mode B
192
Counting Mode
193
Figure 14-12 Counter Timing with Prescaler Value Changing from 1 to 4
193
Figure 14-13 Overflow Event When PRBEN=0
193
Table 14-3 Tmrx Internal Trigger Connection
193
Figure 14-14 Overflow Event When PRBEN=1
194
Figure 14-15 Counter Timing Diagram with Internal Clock Divided by 4
194
Figure 14-16 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
194
TMR Input Function
195
Figure 14-17 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
195
Figure 14-18 Input/Output Channel 1 Main Circuit
195
Figure 14-19 Channel 1 Input Stage
195
Table 14-4 Counting Direction Versus Encoder Signals
195
TMR Output Function
196
Figure 14-20 Capture/Compare Channel Output Stage (Channel 1 to 4)
196
Figure 14-21 C1ORAW Toggles When Counter Value Matches the C1DT Value
197
Figure 14-22 Upcounting Mode and PWM Mode a
197
TMR Synchronization
198
Figure 14-23 Up/Down Counting Mode and PWM Mode a
198
Figure 14-24 One-Pulse Mode
198
Figure 14-25 Clearing Cxoraw(PWM Mode A) by EXT Input
198
Figure 14-26 Example of Reset Mode
199
Figure 14-27 Example of Suspend Mode
199
Figure 14-28 Example of Trigger Mode
199
Figure 14-29 Master/Slave Timer Connection
200
Figure 14-30 Using Master Timer to Start Slave Timer
200
Debug Mode
201
TMR2 and TMR3 Registers
201
Figure 14-31 Starting Master and Slave Timers Synchronously by an External Trigger
201
Table 14-5 TMR2 and TMR3 Register Map and Reset Value
201
TMR2 and TMR3 Control Register1 (Tmrx_Ctrl1)
202
TMR2 and TMR3 Control Register2 (Tmrx_Ctrl2)
203
TMR2 and TMR3 Slave Timer Control Register (Tmrx_Stctrl)
203
TMR2 and TMR3 Dma/Interrupt Enable Register (Tmrx_Iden)
204
TMR2 and TMR3 Interrupt Status Register (Tmrx_Ists)
205
TMR2 and TMR3 Software Event Register (Tmrx_Sw EVT)
206
TMR2 and TMR3 Channel Mode Register1 (Tmrx_Cm1)
206
TMR2 and TMR3 Channel Mode Register2 (Tmrx_Cm2)
208
TMR2 and TMR3 Channel Control Register (Tmrx_Cctrl)
209
TMR2 and TMR3 Counter Value (Tmrx_Cval)
209
Table 14-6 Standard Cxout Channel Output Control Bit
209
TMR2 and TMR3 Division Value (Tmrx_Div)
210
TMR2 and TMR3 Period Register (Tmrx_Pr)
210
TMR2 and TMR3 Channel 1 Data Register (Tmrx_C1Dt)
210
TMR2 and TMR3 Channel 2 Data Register (Tmrx_C2Dt)
210
TMR2 and TMR3 Channel 3 Data Register (Tmrx_C3Dt)
210
TMR2 and TMR3 Channel 4 Data Register (Tmrx_C4Dt)
211
TMR2 and TMR3 DMA Control Register (Tmrx_Dmactrl)
211
TMR2 and TMR3 DMA Data Register (Tmrx_Dmadt)
211
General-Purpose Timer (TMR9 to TMR14)
211
TMR13 and TMR14 Introduction
211
TMR13 and TMR14 Main Features
211
TMR13 and TMR14 Functional Overview
212
Count Clock
212
Counting Mode
212
Figure 14-32 Block Diagram of General-Purpose TMR13/14
212
Figure 14-33 Control Circuit with CK_INT Divided by 1
212
Figure 14-34 Overflow Event When PRBEN=0
212
TMR Input Function
213
Figure 14-35 Overflow Event When PRBEN=1
213
Figure 14-36 Input/Output Channel 1 Main Circuit
213
Figure 14-37 Channel 1 Input Stage
213
TMR Output Function
214
Figure 14-38 Capture/Compare Channel Output Stage (Channel 1)
214
Debug Mode
215
TMR13 and TMR14 Registers
215
Figure 14-39 C1ORAW Toggles When Counter Value Matches the C1DT Value
215
Figure 14-40 Upcounting Mode and PWM Mode a
215
Figure 14-41 One-Pulse Mode
215
TMR13 and TMR14 Control Register1 (Tmrx_Ctrl1)
216
TMR13 and TMR14 Dma/Interrupt Enable Register (Tmrx_Iden)
216
Table 14-7 TMR13 and TMR14 Register Map and Reset Value
216
TMR13 and TMR14 Interrupt Status Register (Tmrx_Ists)
217
TMR13 and TMR14 Software Event Register (Tmrx_Swevt)
217
TMR13 and TMR14 Channel Mode Register1 (Tmrx_Cm1)
217
TMR13 and TMR14 Channel Control Register (Tmrx_Cctrl)
219
TMR13 and TMR14 Counter Value (Tmrx_Cval)
219
TMR13 and TMR14 Division Value (Tmrx_Div)
219
TMR13 and TMR14 Period Register (Tmrx_Pr)
219
Table 14-8 Standard Cxout Channel Output Control Bit
219
TMR13 and TMR14 Channel 1 Data Register (Tmrx_C1Dt)
220
TMR14 Channel Input Remap Register (TMR14_RMP)
220
General-Purpose Timer (TMR15)
220
TMR15 Introduction
220
TMR15 Main Features
220
TMR15 Functional Overview
221
Count Clock
221
Figure 14-42 TMR15 Block Diagram
221
Figure 14-43 Control Circuit with CK_INT Divided by 1
221
Figure 14-44 Block Diagram of External Clock Mode a
221
Counting Mode
222
Figure 14-45 Counting in External Clock Mode a
222
Figure 14-46 Counter Timing with Prescaler Value Changing from 1 to 4
222
Table 14-9 Tmrx Internal Trigger Connection
222
TMR Input Function
223
Figure 14-47 Overflow Event When PRBEN=0
223
Figure 14-48 Overflow Event When PRBEN=1
223
Figure 14-49 OVFIF When RPR=2
223
TMR Output Function
224
Figure 14-50 Input/Output Channel 1 Main Circuit
224
Figure 14-51 Channel 1 Input Stage
224
Figure 14-52 Channel 1 Output Stage
224
Figure 14-53 Channel 2 Output Stage
225
Figure 14-54 C1ORAW Toggles When Counter Value Matches the C1DT Value
226
Figure 14-55 Upcounting Mode and PWM Mode a
226
Figure 14-56 One-Pulse Mode
226
TMR Break Function
227
Figure 14-57 Complementary Output with Dead-Time Insertion
227
TMR Synchronization
228
Figure 14-58 Example of TMR Break Function
228
Figure 14-59 Example of Reset Mode
228
Debug Mode
229
TMR15 Registers
229
Figure 14-60 Example of Suspend Mode
229
Figure 14-61 Example of Trigger Mode
229
Table 14-10 TMR1 and TMR8 Register Map and Reset Value
229
TMR15 Control Register1 (TMR15_CTRL1)
230
TMR15 Control Register2 (TMR15_CTRL2)
230
TMR15 Slave Timer Control Register (TMR15_STCTRL)
231
TMR15 Dma/Interrupt Enable Register (TMR15_IDEN)
231
TMR15 Interrupt Status Register (TMR15_ISTS)
232
TMR15 Software Event Register (TMR15_SWEVT)
233
TMR15 Channel Mode Register1 (TMR15_CM1)
233
TMR15 Channel Control Register (TMR15_CCTRL)
235
Table 14-11 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
236
TMR15 Counter Value (TMR15_CVAL)
237
TMR15 Division Value (TMR15_DIV)
237
TMR15 Period Register (TMR15_PR)
237
TMR15 Repetition Period Register (TMR15_RPR)
237
TMR15 Channel 1 Data Register (TMR15_C1DT)
237
TMR15 Channel 2 Data Register (TMR15_C2DT)
237
TMR15 Break Register (TMR15_BRK)
238
TMR15 DMA Control Register (TMR15_DMACTRL)
239
TMR15 DMA Data Register (TMR15_DMADT)
239
General-Purpose Timers (TMR16 and TMR17)
239
TMR16 and TMR17 Introduction
239
TMR16 and TMR17 Main Features
240
TMR16 and TMR17 Functional Overview
240
Count Clock
240
Counting Mode
240
Figure 14-62 Block Diagram of TMR16 and TMR17 Timer
240
Figure 14-63 Control Circuit with CK_INT Divided by 1
240
TMR Input Function
241
Figure 14-64 Overflow Event When PRBEN=0
241
Figure 14-65 Overflow Event When PRBEN=1
241
Figure 14-66 OVFIF When RPR=2
241
Figure 14-67 Input/Output Channel 1 Main Circuit
241
TMR Output Function
242
Figure 14-68 Channel 1 Input Stage
242
Figure 14-69 Channel Output Stage
242
Figure 14-70 C1ORAW Toggles When Counter Value Matches the C1DT Value
243
Figure 14-71 Upcounting Mode and PWM Mode a
243
TMR Break Function
244
Figure 14-72 One-Pulse Mode
244
Figure 14-73 Complementary Output with Dead-Time Insertion
244
Debug Mode
245
TMR16 and TM17 Registers
245
Figure 14-74 Example of TMR Break Function
245
Table 14-12 TMR16 and TMR17 Register Map and Reset Value
245
TMR16 and TMR17 Control Register1 (Tmrx_Ctrl1)
246
TMR16 and TMR17 Control Register2 (Tmrx_Ctrl2)
246
TMR16 and TMR17 Dma/Interrupt Enable Register (Tmrx_Iden)
247
TMR16 and TMR17 Interrupt Status Register (Tmrx_Ists)
247
TMR16 and TMR17 Software Event Register (Tmrx_Swevt)
248
TMR16 and TMR17 Channel Mode Register1 (Tmrx_Cm1)
248
TMR16 and TMR17 Channel Control Register (Tmrx_Cctrl)
250
Table 14-13 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
250
TMR16 and TMR17 Counter Value (Tmrx_Cval)
251
TMR16 and TMR17 Division Value (Tmrx_Div)
251
TMR16 and TMR17 Period Register (Tmrx_Pr)
251
TMR16 and TMR17 Repetition Period Register (Tmrx_Rpr)
251
TMR16 and TMR17 Channel 1 Data Register (Tmrx_C1Dt)
251
TMR16 and TMR17 Break Register (Tmrx_Brk)
252
TMR16 and TMR17 DMA Control Register (Tmrx_Dmactrl)
253
TMR16 and TMR17 DMA Data Register (Tmrx_Dmadt)
253
Advanced-Control Timers (TMR1)
253
TMR1 Introduction
253
TMR1 Main Features
254
TMR1 Functional Overview
254
Count Clock
254
Figure 14-75 Block Diagram of Advanced-Control Timer
254
Figure 14-76 Control Circuit with CK_INT Divided by 1
254
Figure 14-77 Block Diagram of External Clock Mode a
255
Figure 14-78 Counting in External Clock Mode a
255
Figure 14-79 Block Diagram of External Clock Mode B
255
Counting Mode
256
Figure 14-80 Counting in External Clock Mode B
256
Figure 14-81 Counter Timing with Prescaler Value Changing from 1 to 4
256
Table 14-14 Tmrx Internal Trigger Connection
256
Figure 14-82 Overflow Event When PRBEN=0
257
Figure 14-83 Overflow Event When PRBEN=1
257
Figure 14-84 Counter Timing Diagram with Internal Clock Divided by 4
257
Figure 14-85 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
258
Figure 14-86 OVFIF When RPR=2
258
Figure 14-87 Example of Encoder Interface Mode C
258
Table 14-15 Counting Direction Versus Encoder Signals
258
TMR Input Function
259
Figure 14-88 Input/Output Channel 1 Main Circuit
259
Figure 14-89 Channel 1 Input Stage
259
TMR Output Function
260
Figure 14-90 Channel Output Stage (Channel 1 to 3)
260
Figure 14-91 Channel 4 Output Stage
260
Figure 14-92 C1ORAW Toggles When Counter Value Matches the C1DT Value
261
Figure 14-93 Upcounting Mode and PWM Mode a
261
Figure 14-94 Up/Down Counting Mode and PWM Mode
261
Figure 14-95 One-Pulse Mode
262
Figure 14-96 Clearing Cxoraw(PWM Mode A) by EXT Input
262
Figure 14-97 Complementary Output with Dead-Time Insertion
262
TMR Break Function
263
TMR Synchronization
263
Figure 14-98 Example of TMR Break Function
263
Debug Mode
264
Figure 14-99 Example of Reset Mode
264
Figure 14-100 Example of Suspend Mode
264
Figure 14-101 Example of Trigger Mode
264
TMR1 Registers
265
TMR1 Control Register1 (TMR1_CTRL1)
265
Table 14-16 TMR1 Register Map and Reset Value
265
TMR1 Control Register2 (TMR1_CTRL2)
266
TMR1 Slave Timer Control Register (TMR1_STCTRL)
267
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)
268
TMR1 Interrupt Status Register (TMR1_ISTS)
269
TMR1 Software Event Register (TMR1_SWEVT)
270
TMR1 Channel Mode Register1 (TMR1_CM1)
270
TMR1 Channel Mode Register2 (TMR1_CM2)
272
TMR1 Channel Control Register (TMR1_CCTRL)
273
Table 14-17 Complementary Output Channel Cxout and Cxcout Control Bits with Break Function
274
TMR1 Counter Value (TMR1_CVAL)
275
TMR1 Division Value (TMR1_DIV)
275
TMR1 Period Register (TMR1_PR)
275
TMR1 Repetition Period Register (TMR1_RPR)
275
TMR1 Channel 1 Data Register (TMR1_C1DT)
275
TMR1 Channel 2 Data Register (TMR1_C2DT)
275
TMR1 Channel 3 Data Register (TMR1_C3DT)
276
TMR1 Channel 4 Data Register (Tmrx_C4Dt)
276
TMR1 Break Register (TMR1_BRK)
276
TMR1 DMA Control Register (TMR1_DMACTRL)
277
TMR1 DMA Data Register (TMR1_DMADT)
278
TMR1 Channel Mode Register3 (TMR1_ CM3)
278
TMR1 Channel 5 Data Register (TMR1_C5DT)
278
Window Watchdog Timer (WWDT)
279
WWDT Introduction
279
WWDT Main Features
279
WWDT Functional Overview
279
Figure 15-1 Window Watchdog Block Diagram
279
Debug Mode
280
WWDT Registers
280
Control Register (WWDT_CTRL)
280
Configuration Register (WWDT_CFG)
280
Figure 15-2 Window Watchdog Timing Diagram
280
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
280
Table 15-2 WWDT Register Map and Reset Value
280
Status Register (WWDT_STS)
281
Watchdog Timer (WDT)
282
WDT Introduction
282
WDT Main Features
282
WDT Functional Overview
282
Debug Mode
283
WDT Registers
283
Figure 16-1 WDT Block Diagram
283
Table 16-1 WDT Timeout Period (Lick=40Khz)
283
Table 16-2 WDT Register and Reset Value
283
Command Register (WDT_CMD)
284
Divider Register (WDT_DIV)
284
Reload Register (WDT_RLD)
284
Status Register (WDT_STS)
284
Window Register (WDT_WIN)
284
Enhanced Real-Time Clock (ERTC)
285
ERTC Introduction
285
ERTC Main Features
285
ERTC Function Overview
285
ERTC Clock
285
Figure 17-1 ERTC Block Diagram
285
ERTC Initialization
286
Table 17-1 RTC Register Map and Reset Values
286
Periodic Automatic Wakeup
288
ERTC Calibration
288
Time Stamp Function
289
Tamper Detection
289
Multiplexed Function Output
290
ERTC Wakeup
290
Table 17-2 ERTC Low-Power Mode Wakeup
290
Table 17-3 Interrupt Control Bits
290
ERTC Registers
291
ERTC Time Register (ERTC_TIME)
291
ERTC Date Register (ERTC_DATE)
291
Table 17-4 ERTC Register Map and Reset Values
291
ERTC Control Register (ERTC_CTRL)
292
ERTC Initialization and Status Register (ERTC_STS)
293
ERTC Divider Register (ERTC_DIV)
294
ERTC Wakeup Timer Register (ERTC_WAT)
295
ERTC Alarm Clock a Register (ERTC_ALA)
295
ERTC Write Protection Register (ERTC_WP)
295
ERTC Subsecond Register (ERTC_SBS)
295
ERTC Time Adjustment Register (ERTC_TADJ)
295
ERTC Time Stamp Time Register (ERTC_TSTM)
296
ERTC Time Stamp Date Register (ERTC_TSDT)
296
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)
296
ERTC Smooth Calibration Register (ERTC_SCAL)
296
ERTC Tamper Configuration Register (ERTC_TAMP)
297
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)
298
ERTC Battery Powered Domain Data Register (Ertc_Bprx)
298
Analog-To-Digital Converter (ADC)
299
ADC Introduction
299
ADC Main Features
299
ADC Structure
299
ADC Functional Overview
300
Channel Management
300
Figure 18-1 ADC1 Block Diagram
300
Internal Reference Voltage
301
ADC Operation Process
301
Power-On and Calibration
301
Figure 18-2 ADC Basic Operation Process
301
Trigger
302
Sampling and Conversion Sequence
302
Figure 18-3 ADC Power-On and Calibration
302
Table 18-1 Trigger Sources for ADC
302
Conversion Sequence Management
303
Sequence Mode
303
Automatic Preempted Group Conversion Mode
303
Figure 18-4 Sequence Mode
303
Figure 18-5 Preempted Group Auto Conversion Mode
303
Repetition Mode
304
Partition Mode
304
Oversampling
304
Figure 18-6 Repetition Mode
304
Figure 18-7 Partition Mode
304
Oversampling of Ordinary Group of Channels
305
Table 18-2 Correlation between Maximum Cumulative Data, Oversampling Multiple and Shift Digits
305
Oversampling of Preempted Group of Channels
306
Figure 18-8 Ordinary Oversampling Restart Mode Selection
306
Figure 18-9 Ordinary Oversampling Trigger Mode
306
Data Management
307
Data Alignment
307
Data Read
307
Voltage Monitoring
307
Figure 18-10 Oversampling of Preempted Group of Channels
307
Figure 18-11 Data Alignment
307
Status Flag and Interrupts
308
ADC Registers
308
ADC Status Register (ADC_STS)
308
Table 18-3 ADC Register Map and Reset Values
308
ADC Control Register1 (ADC_CTRL1)
309
ADC Control Register2 (ADC_CTRL2)
310
ADC Sampling Time Register 1 (ADC_SPT1)
312
ADC Sampling Time Register 2 (ADC_SPT2)
313
ADC Preempted Channel Data Offset Register
315
(ADC_ Pcdtox) (X=1
315
ADC Voltage Monitor High Threshold Register (ADC_VWHB)
315
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)
315
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)
315
ADC Ordinary Sequence Register 2 (ADC_ OSQ2)
316
ADC Ordinary Sequence Register 3 (ADC_ OSQ3)
316
ADC Preempted Sequence Register (ADC_ PSQ)
316
ADC Preempted Data Register X (ADC_ Pdtx) (X=1
317
ADC Ordinary Data Register (ADC_ ODT)
317
ADC Oversampling Register (ADC_ OVSP)
318
Controller Area Network (CAN)
319
CAN Introduction
319
CAN Main Features
319
Baud Rate
319
Figure 19-1 Bit Timing
319
Figure 19-2 Transmit Interrupt Generation
321
Interrupt Management
322
Design Tips
322
Figure 19-3 Transmit Interrupt Generation
322
Figure 19-4 Receive Interrupt 0 Generation
322
Figure 19-5 Receive Interrupt 1 Generation
322
Figure 19-6 Status Error Interrupt Generation
322
Functional Overview
323
General Description
323
Operating Modes
323
Figure 19-7 CAN Block Diagram
323
Test Modes
324
Message Filtering
324
Figure 19-8 32-Bit Identifier Mask Mode
325
Figure 19-9 32-Bit Identifier List Mode
325
Figure 19-10 16-Bit Identifier Mask Mode
325
Figure 19-11 16-Bit Identifier List Mode
325
Message Transmission
327
Figure 19-12 Transmit Mailbox Status
327
Message Reception
328
Figure 19-13 Receive FIFO Status
328
Error Management
329
CAN Registers
329
Table 19-1 CAN Register Map and Reset Values
329
CAN Control and Status Registers
330
CAN Master Control Register (CAN_MCTRL)
330
CAN Master Status Register (CAN_MSTS)
331
CAN Transmit Status Register (CAN_TSTS)
333
CAN Receive FIFO 0 Register (CAN_RF0)
335
CAN Receive FIFO 1 Register (CAN_RF1)
336
CAN Interrupt Enable Register (CAN_INTEN)
336
CAN Error Status Register (CAN_ESTS)
338
CAN Bit Timing Register (CAN_BTMG)
338
CAN Mailbox Registers
339
Transmit Mailbox Identifier Register (Can_Tmix) (X=0
339
Figure 19-14 Transmit and Receive Mailboxes
339
Transmit Mailbox Data Length and Time Stamp Register
340
(Can_Tmcx) (X=0
340
Transmit Mailbox Data Low Register (Can_Tmdtlx) (X=0
340
Transmit Mailbox Data High Register (Can_Tmdthx) (X=0
340
Receive FIFO Mailbox Identifier Register (Can_Rfix) (X=0
340
Receive FIFO Mailbox Data Length and Time Stamp Register
341
(Can_Rfcx) (X=0
341
Receive FIFO Mailbox Data Low Register
341
(Can_Rfdtlx) (X=0
341
Receive FIFO Mailbox Data High Register (Can_Rfdthx) (X=0
341
CAN Filter Registers
341
CAN Filter Control Register (CAN_FCTRL)
341
CAN Filter Mode Configuration Register (CAN_FMCFG)
341
CAN Filter Bit Width Configuration Register (CAN_ FBWCFG)
342
CAN Filter FIFO Association Register (CAN_ FRF)
342
CAN Filter Activation Control Register (CAN_ FACFG)
342
CAN Filter Bank I Filter Bit Register (CAN_ Fifbx
342
Universal Serial Bus Full-Seed Device Interface (OTGFS)
343
USBFS Structure
343
OTGFS Functional Description
343
Figure 20-1 Block Diagram of OTGFS Structure
343
OTGFS Clock and Pin Configuration
344
OTGFS Clock Configuration
344
OTGFS Pin Configuration
344
Table 20-1 OTGFS Input/Output Pins
344
OTGFS Interrupts
345
OTGFS Functional Description
345
OTGFS Initialization
345
Figure 20-2 OTGFS Interrupt Hierarchy
345
OTGFS FIFO Configuration
346
Device Mode
346
Table 20-2 OTGFS Transmit FIFO SRAM Allocation
346
Host Mode
347
Table 20-3 OTGFS Internal Register Storage Space Allocation
347

ARTERY AT32F425 Series Manual (26 pages)

Brand: ARTERY | Category: Computer Hardware | Size: 1 MB

Table of Contents
2
Development Resources
5
Set up AT32 Development Environment
5
Debug Tools and Evaluation Board
5
Programming Tools and Software Resources
5
Figure 1. AT_START_F425 and AT-Link-EZ
5
Figure 2. AT-START-F425 Evaluation Board Package from ARTERY Official Website
5
AT32 Development Environment
6
Figure 3. ICP/ISP/AT-Link-Family Package on ARTERY Official Website
6
Figure 4. BSP Resources on ARTERY Official Website
6
Figure 5. Keil_V5 Templates Template
7
Figure 6. Pack Resources on ARTERY Official Website
8
Figure 7. Install Arterytek.at32F425_Dfp
8
Figure 8. Install Keil4_At32Mcu_Addon
8
Figure 9. Click "Pack Installer" in Keil
9
Figure 10. Install Iar_At32Mcu_Addon
9
Figure 11. Keil Debug Option
10
Figure 12. Settings Option in Keil Debug
10
Figure 13. Keil Utilities Option
11
Figure 14. IAR Debug Option
11
How to Quickly Replace AT32F415 with AT32F425
12
AT32F425 Functionality Configuration
12
Instruction Prefetch Buffer
12
Figure 15. IAR CMSIS-DAP Option
12
PLL Clock Configuration
13
Figure 16. Wait State Bit in FLASH_PSR Register
13
Figure 17. System_Clock_Config Function
13
Figure 18. AT32F425 94Mhz Output Clock
13
Encryption
14
Figure 19. Use ICP Tool to Enable/Disable Access Protection
14
Figure 20. Use ISP to Enable Access Protection
15
Figure 21. Use ISP to Disable Access Protection
15
Figure 22. Use ICP Tool to Enable Erase/Program Protection
16
Set System Memory as Main Memory Extension
17
Figure 23. Use ICP Tool to Disable Erase/Program Protection
17
Figure 24. Use ICP Tool to Set Boot Memory AP Mode
18
Figure 25. Boot Memory AP Mode Operating Progress
18
Figure 26. Use ICP Tool to Set Offline Boot Mode AP Mode
19
Figure 27. Use ICP Tool to Set Offline Project Programming
20
Figure 28. ICP Tool to Monitor Offline Download Status
20
How to Distinguish AT32 MCU from Other Mcus
21
Figure 29. Read Cortex ID
21
Figure 30. Read PID and UID
21
Faqs about Download and Compiling
22
Program Enters Hard Fault Handler
22
Jlink Unable to Recognize IC in Keil Project
22
Errors During Download
22
Flash Download Failed-"Cortex-M4
22
Figure 31. Error: Flash Download Failed-"Cortex- M4
22
No Debug Unit Device Found
23

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ARTERY AT32F425 Series Manual (26 pages)

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