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Advantech ASMB-H90 Startup Manual page 2

Lga 4094 hygon eatx server board with 16 x ddr4, 4 x pcie x16, 2 x pcie x8, 10 x sata3, 2 x m.2, 4 x usb3.2 gen1, dual gbe, ipmi

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Jumpers and Connectors
The board has a number of jumpers that allow you to con-
figure your system to suit your application. The table below
lists the function of each of the jumpers and connectors.
Connectors
Label
ATXPWR1
ATX12V1, ATX12V2
SPI_CN1
SPI_CN2
VGA_HDR1
SYSFAN1, SYSFAN2
SYSFAN3, SYSFAN4
CPUFAN1, CPUFA2
DIMMA0, DIMMB0,
DIMMC0, DIMMD0,
DIMME0, DIMMF0,
DIMMG0, DIMMH0
SLIMSAS1,
SLIMSAS2
FRHDD_BP1
CN2
JFP1, JFP1+JFP2,
JFP3
SLOT12V1
LAN1, LAN2
SPI_IPMI
M2_CN1
M2_CN2
PMBUS1
SATA1~SATA10
JFP4
SGPIO0, SGPIO1
PCIEX16_SLOT1
PCIEX8_SLOT2
PCIEX16_SLOT3
PCIEX8_SLOT4
PCIEX16_SLOT5
PCIEX16_SLOT6
USB_FRONT1
CN4
2 H90 Startup Manual
Function
ATX 24-pin main power connector
Processor power connector
Primary BIOS SPI ROM
Secondary BIOS SPI ROM
Front VGA header
SYSTEM FAN connector
CPU FAN connector
DDR4 slot (CPU0/CPU1)
Slimline SAS x8 connector
Front BP I2C connector
HDT header (Debug)
Front panel header
For PCIe slot 12V input only
RJ-45 GbE LAN connector
TPM SPI connector
M.2 connector (PCIe x2)
M.2 connector (PCIe x2)
PMBUS connector to communi-
cate with power supply
SATA 1~10 connector
Front panel header (for 3rd party
Chassis)
SATA SGPIO header
PCIE x16 slot (x16 link) (CPU)
PCIE x8 slot (x8 link) (CPU)
PCIE x16 slot (x16 link) (CPU)
PCIE x8 slot (x8 link) (CPU)
PCIE x16 slot (x16 link) (CPU)
PCIE x16 slot (x16 link) (CPU)
Front panel USB connector
Custom Flash (Reserved)
Jumpers and Connectors (Cont.)
CN5
IPMB1
CN1
FPGA_JTAG
LAN1/LAN2
LAN1_USB3
VGA1, COM1
Jumper list
Label
CASE_CN1
JP1
JP2
JP3
JP4
JP1: CMOS clear function
Closed pins
1-2
2-3
*: Default
Keep CMOS data
Declaration of Conformity
This device complies with the requirements in Part 15 of
the FCC rules. Operation is subject to the following two
conditions:
1. This device may not cause harmful interference.
2. This device must accept any interference received,
including interference that may cause undesired opera-
tion.
BMC programming header
IPMB header
UART debug port
CPLD programming header
10G RJ45 (Option)
USB 3.2 port 1, 2 (Type A); IPMI
LAN (RJ45)
VGA & COM connector
Function
Chassis case open alarm
CMOS clear
BMC debug port
SGPIO debug port
PSU_ON
Result
Keep CMOS data
Clear CMOS data
Clear CMOS data

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