Full-Duplex Data Interface (Tx And Rx Port) Timing Specifications; Explanation Of Test Levels - Analog Devices AD9865 Manual

AD9865

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 7.
Parameter
Tx PATH INTERFACE (See Figure 53)
Input Nibble Rate (2× Interpolation)
Input Nibble Rate (4× Interpolation)
Tx Data Setup Time (t )
DS
Tx Data Hold Time (t )
DH
1
Rx PATH INTERFACE (See Figure 54)
Output Nibble Rate
Rx Data Valid Time (t )
DV
Rx Data Hold Time (t )
DH
1
C =5 pF for digital data outputs.
LOAD

EXPLANATION OF TEST LEVELS

I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Temp Test Level
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Rev. A | Page 8 of 48
Min Typ Max
20 160
10 100
2.5
1.5
10 160
3
0
Unit
MSPS
MSPS
ns
ns
MSPS
ns
ns