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SERIAL PORT
Table 10. SPI Register Mapping
Bit
Address
Break-
(Hex)
1
down
Description
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
(7)
4-Wire SPI
(6)
LSB First
(5)
S/W Reset
POWER CONTROL REGISTERS (via PWR_DWN pin)
0x01
(7)
Clock Syn.
(6)
TxDAC/IAMP
(5)
Tx Digital
(4)
REF
(3)
ADC CML
(2)
ADC
(1)
PGA Bias
(0)
RxPGA
0x02
(7)
CLK Syn.
(6)
TxDAC/IAMP
(5)
Tx Digital
(4)
REF
(3)
ADC CML
(2)
ADC
(1)
PGA Bias
(0)
RxPGA
HALF-DUPLEX POWER CONTROL
0x03
(7:3)
Tx OFF Delay
(2)
Rx _TXEN
(1)
Tx PWRDN
(0)
Rx PWRDN
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
(5)
Duty Cycle Enable
(4)
f
from PLL
ADC
(3:2)
PLL Divide-N
(1:0)
PLL Multiplier-M
0x05
(2)
OSCIN to RXCLK
(1)
Invert RXCLK
(0)
Disabled RXCLK
0x06
(7:6)
CLKOUT2 Divide
(5)
CLKOUT2 Invert
(4)
CLKOUT2 Disable
(3:2)
CLKOUT1 Divide
(1)
CLKOUT1 Invert
(0)
CLKOUT1 Disable
Rx PATH CONTROL
0x07
(5)
Initiate Offset Cal.
(4)
Rx Low Power
(0)
Rx Filter ON
Power-Up Default Value
MODE = 0 (Half-Duplex)
Width
CONFIG = 0
CONFIG = 1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
1
0xFF
0xFF
1
1
1
0
0
1
0
0
2
00
00
2
01
10*
1
0
0
1
0
0
1
0
0
2
01
01
1
0
0
1
0
0
2
01
01
1
0
0
1
0
0
1
0
0
1
0
1*
1
1
1
Rev. A | Page 19 of 48
MODE = 1 (Full-Duplex)
Comments
CONFIG = 0
CONFIG = 1
0
0
Default SPI configuration is
3-wire, MSB first.
0
0
0
0
0
0
PWR_DWN = 0.
Default setting is for all
0
0
blocks powered on.
0
0
0
0
0
0
0
0
0
0
0
0
0
1*
PWR_DWN = 1.
Default setting* is for all
1
1
functional blocks powered
1
1
down except PLL.
1
1
*MODE = CONFIG = 1.
1
1
Setting has PLL powered
1
1
down with OSCIN input
routed to RXCLK output.
1
1
1
1
Default setting is for TXEN
input to control power
on/off of Tx/Rx path.
N/A
N/A
Tx driver delayed by 31
1/f
DATA
0
0
Default setting is Duty Cycle
Restore disabled, ADC CLK
0
0
from OSCIN input, and PLL
00
00
multiplier × 2 setting.
01
01
*PLL multiplier × 4 setting.
0
1*
Full-duplex RXCLK normally
at nibble rate.
0
0
*Exception on power-up.
0
0
01
01
Default setting is CLKOUT2
and CLKOUT1 enabled with
0
0
divide-by-2.
0
1*
*CLKOUT1 and CLKOUT2
01
01
disabled.
0
0
0
1*
0
0
Default setting has LPF ON
and Rx path at nominal
0
1*
power bias setting.
1
1
*Rx path to low power.
AD9865
clock cycles.
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