AD9865
Parameter
POWER CONSUMPTION (Half-Duplex Operation with f
Tx Mode
I
+ I
AVDD
CLKVDD
I
+ I
DVDD
DRVDD
Rx Mode
I
+ I
AVDD
CLKVDD
I
+ I
DVDD
DRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
1
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP's current consumption, which is application dependent.
2
Default power-up settings for MODE = LOW and CONFIG = LOW.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
Table 4.
Parameter
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
CMOS LOGIC OUTPUTS (C
= 5 pF)
LOAD
High Level Output Voltage (I
OH
Low Level Output Voltage (I
OH
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
Output Rise/Fall Time (High Strength Mode and C
Output Rise/Fall Time (Low Strength Mode and C
RESET
Minimum Low Pulse Width (Relative to f
= 50 MSPS)
DATA
1
(I
+ I
AVDD
CLKVDD
= 1 mA)
= 1 mA)
= 15 pF)
LOAD
= 15 pF)
LOAD
= 5 pF)
LOAD
= 5 pF)
LOAD
)
ADC
Rev. A | Page 6 of 48
Temp
Test Level
2
25°C
IV
25°C
IV
25°C
IV
25°C
IV
)
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
Full
IV
Full
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
25°C
III
= 2 kΩ, unless otherwise noted.
SET
Temp
Test Level
Min
Full
VI
DRVDD – 0.7
Full
VI
Full
VI
Full
VI
DRVDD – 0.7
Full
VI
Full
VI
Full
VI
Full
VI
Full
VI
1
Min
Typ
Max
Unit
112
130
mA
46
49.5
mA
225
253
mA
36.5
39
mA
87
mA
108
mA
38
mA
10
120
mA
170
mA
107
mA
1.66
W
13
mA
440
ns
12
ns
20
ns
20
ns
27
ns
7.8
µs
88
ns
13
µs
20
ns
20
µs
Typ
Max
Unit
V
0.4
V
12
µA
3
pF
V
0.4
V
1.5/2.3
ns
1.9/2.7
ns
0.7/0.7
ns
1.0/1.0
ns
Clock
cycles
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