Pin Configuration And Function Descriptions - Analog Devices AD9865 Manual

AD9865

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RXEN/RXSYNC
TXEN/TXSYNC
TXCLK/TXQUIET
Table 9. Pin Function Descriptions
Pin No.
1
2 to 5
6
7
8, 9
10
11
12
13
14
64 63 62 61 60
ADIO9/Tx[5]
1
ADIO8/Tx[4]
2
PIN 1
ADIO7/Tx[3]
3
IDENTIFIER
ADIO6/Tx[2] 4
ADIO5/Tx[1] 5
ADIO4/Tx[0] 6
ADIO3/Rx[5]
7
ADIO2/Rx[4] 8
ADIO1/Rx[3] 9
ADIO0/Rx[2]
10
NC/Rx[1] 11
NC/Rx[0]
12
13
14
15
RXCLK
16
17 18 19 20 21
Figure 2. Pin Configuration
1
Mnemonic Mode
ADIO9 HD
Tx[5] FD
ADIO8 to 5 HD
Tx[4 to 1] FD
ADIO4 HD
Tx[0] FD
ADIO3 HD
Rx[5] FD
ADIO2, 1 HD
Rx[4, 3] FD
ADIO0 HD
Rx[2] FD
NC HD
Rx[1] FD
NC HD
Rx[0] FD
RXEN HD
RXSYNC FD
TXEN HD
TXSYNC FD
Rev. A | Page 10 of 48
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AD9865
TOP VIEW
(Not to Scale)
22 23 24 25 26 27 28 30 31 32
29
Description
MSB of ADIO Buffer
MSB of Tx Nibble Input
Bits 8 to 5 of ADIO Buffer
Bits 4 to 1 of Tx Nibble Input
Bit 4 of ADIO Buffer
LSB of Tx Nibble Input
Bit 3 of ADIO Buffer
MSB of Rx Nibble Output
Bits 2 to 1 of ADIO Buffer
Bits 4 to 3 of Rx Nibble Output
LSB of ADIO Buffer
Bit 2 of Rx Nibble Output
No Connect
Bit 1 of Rx Nibble Output
No Connect
LSB of Rx Nibble Output
ADIO Buffer Control Input
Rx Data Synchronization Output
Tx Path Enable Input
Tx Data Synchronization Input
AVSS
48
AVSS
47
IOUT_N–
46
45 IOUT_G–
44 AVSS
43 AVDD
REFIO
42
41 REFADJ
40 AVDD
AVSS
39
38 RX+
RX–
37
AVSS
36
AVDD
35
34 AVSS
REFT
33