Iamp Voltage-Mode Operation - Analog Devices AD9865 Manual

outputs left open for optimum linearity performance. The
1
transformer should be specified to handle the dc standing
current, I , drawn by the IAMP. Also, because I
BIAS
signal independent, a series resistor (not shown) can be inserted
between AVDD and the transformer's center-tap to reduce the
IAMP's common-mode voltage, V
dissipation on the IC. The V
CM
the power dissipated in the IAMP alone is as follows:
P = 2 × (N + G) × I × V
IAMP
0.1µF
R
SET
IAMP
TxDAC
0 TO –7.5dB 0 TO –12dB
Figure 64. Current-Mode Operation
1
A step-down transformer with a turn ratio, T, can be used to
increase the output power, P_OUT, delivered to the load. This
causes the output load, R , to be reflected back to the IAMP's
L
2
differential output by T , resulting in a larger differential voltage
swing seen at the IAMP's output. For example, the IAMP can
deliver 24 dBm of peak power to a 50 Ω load, if a 1.41:1 step-
down transformer is used. This results in 5 V p-p voltage swings
appearing at IOUTN+ and IOUTN− pins. Figure 42 shows how
the third order intercept point, OIP3, of the IAMP varies as a
function of common-mode voltage over a 2.5 MHz to 20.0 MHz
span with a 2-tone signal having a peak power of approximately
24 dBm with IOUT = 50 mA.
PK
For applications requiring an IOUT
secondary's path to deliver the additional current to the load.
IOUTG+ and IOUTN+ should be shorted as well as IOUTG−
and IOUTN−. If IOUT represents the peak current to be
PK
delivered to the load, then the current gain in the secondary
path, G, can be set by the following equation:
G = IOUT /12.5 − 4
PK
The linearity performance becomes limited by the secondary
mirror path's distortion.
1
The B6080 and BX6090 transformers from Pulse Engineering are worthy of
consideration for current and voltage modes.
remains
BIAS
, and reduce the power
CM
bias should not exceed 5.0 V and
(2)
CM
AVDD
= 2 × (N+G) × 1
0.1µF
I
BIAS
IOUTN+
IOUTG+
T:1
R
L
IOUT
PK
IOUTN–
IOUTG–
= (N+G) × 1
IOUT
PK
× T × R
2 2
P_OUT = (IOUT )
PK PK L
exceeding 50 mA, set the
PK
(3)
Rev. A | Page 31 of 48

IAMP VOLTAGE-MODE OPERATION

The voltage-mode configuration is shown in Figure 65. This
configuration is suited for applications having a poorly defined
load that can vary over a considerable range. A low impedance
voltage driver can be realized with the addition of two external
RF bipolar npn transistors (Phillips PBR951) and resistors. In
this configuration, the current mirrors in the primary path
(IOUTN outputs) feed into scaling resistors, R, generating a
differential voltage into the bases of the npn transistors. These
transistors are configured as source followers with the secon-
dary path current mirrors appearing at IOUTG+ and IOUTG−
providing a signal-dependent bias current. Note that the
IOUTP outputs must remain open for proper operation.
0.1µF
R
SET
IOUTN+
IOUTG+
TxDAC IAMP
0 TO –7.5dB 0 TO –12dB
IOUTN–
IOUTG–
Figure 65. Voltage-Mode Operation
The peak differential voltage signal developed across the npn's
bases is as follows:
VOUT = R × (N × I)
PK
where:
N is the gain setting of the primary mirror.
I is the standing current of the TxDAC defined in Equation 1.
The common-mode bias voltage seen at IOUTN+ and IOUTN−
is approximately AVDD − VOUT
voltage seen at IOUTG+ and IOUTG− is approximately the
npn's V drop below this level (AVDD − VOUT
BE
the voltage-mode configuration, the total power dissipated
within the IAMP is as follows :
P = 2 × I × {(AVDD − VOUT
IAMP
+ (AVDD − VOUT − 0.65) × G}
PK
The emitters of the npn transistors are ac-coupled to the trans-
1
former via a 0.1 µF blocking capacitor and series resistor of 1 Ω
to 2 Ω. Note that protection diodes are not shown for clarity
purposes, but should be considered if interfacing to a power or
phone line.
The amount of standing and signal-dependent current used to
bias the npn transistors depends on the peak current, IOUT
required by the load. If the load is variable, determine the worst
case, IOUT , and add 3 mA of margin to ensure that the npn
PK
transistors remain in the active region during peak load
AD9865
AVDD
DUAL NPN
R
R
PHILLIPS PBR951
R
0.1µF
S
IOUT
PK
TO LOAD
AVDD
R
0.1µF
S
(4)
, while the common-mode
PK
− 0.65). In
PK
) × N
PK
(5)
,
PK