Analog Devices AD9865 Manual page 38

AD9865
at OSCIN (or RXCLK) can be determined upon power up. Also,
this clock has near 50% duty cycle, because it is derived from
the VCO. As a result, CLKOUT1 should be selected before
CLKOUT2 as the primary source for system clock distribution.
CLKOUT2 is a divided version of the reference frequency, f
and can be set to be a submultiple integer of f
where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is
a delayed version of the signal appearing at OSCIN, exhibiting
the same duty cycle characteristics. With L set to 1 or 2, the
output of CLKOUT2 is a divided version of the OSCIN signal,
exhibiting a near 50% duty cycle, but without having a determi-
nistic phase relationship relative to CLKOUT1 (or RXCLK).
Table 22. SPI Registers for CLK Synthesizer
Address (Hex)
0x04
,
OSCIN
0x06
L
(f /2 ,
OSCIN OSCIN
Rev. A | Page 38 of 48
Bit Description
(4) ADC CLK from PLL
(3:2) PLL divide factor (P)
(1:0) PLL multiplication factor (M)
(7:6) CLKOUT2 divide number
(5) CLKOUT2 invert
(4) CLKOUT2 disable
(3:2) CLKOUT1 divide number
(1) CLKOUT1 invert
(0) CLKOUT1 disable