GigaDevice Semiconductor GD32F150 Series Manuals

Manuals and User Guides for GigaDevice Semiconductor GD32F150 Series. We have 3 GigaDevice Semiconductor GD32F150 Series manuals available for free PDF download: User Manual

GigaDevice Semiconductor GD32F150 Series User Manual

GigaDevice Semiconductor GD32F150 Series User Manual (702 pages)

ARM Cortex-M3 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 9 MB

Table of Contents

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GigaDevice Semiconductor GD32F150 Series User Manual

GigaDevice Semiconductor GD32F150 Series User Manual (577 pages)

Arm Cortex-M3 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 7 MB

Table of Contents

Table of Contents
2
List of Figures
15
List of Tables
21
System and Memory Architecture
23
ARM Cortex-M3 Processor
23
System Architecture
24
Figure 1-1. the Structure of the Cortex ® -M3 Processor
24
Memory Map
25
Figure 1-2. Series System Architecture of Gd32F130Xx and Gd32F150Xx Devices
25
Table 1-1. Memory Map of Gd32F130Xx and Gd32F150Xx Devices
26
Bit-Banding
28
On-Chip SRAM Memory
28
On-Chip Flash Memory
29
Boot Configuration
29
Table 1-2. Flash Module Organization
29
Table 1-3. Boot Modes
29
System Configuration Registers (SYSCFG)
31
System Configuration Register 0 (SYSCFG_CFG0)
31
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
32
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
33
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
34
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
36
System Configuration Register 2 (SYSCFG_CFG2)
37
Device Electronic Signature
38
Memory Density Information
38
Unique Device ID (96 Bits)
39
Flash Memory Controller (FMC)
41
Overview
41
Characteristics
41
Function Overview
41
Flash Memory Architecture
41
Table 2-1. Base Address and Size for Flash Memory
41
Read Operations
42
Unlock the FMC_CTL Register
42
Page Erase
42
Mass Erase
43
Figure 2-1. Process of Page Erase Operation
43
Figure 2-2. Process of the Mass Erase Operation
44
Main Flash Programming
45
Option Bytes Erase
46
Figure 2-3. Process of the Word Programming Operation
46
Option Bytes Programming
47
Option Bytes Description
47
Table 2-2. Option Bytes
47
Page Erase/Program Protection
48
Security Protection
49
Table 2-3. OB_WP Bit for Pages Protected
49
Register Definition
50
Wait State Register (FMC_WS)
50
Unlock Key Register (FMC_KEY)
50
Option Bytes Unlock Key Register (FMC_OBKEY)
51
Status Register (FMC_STAT)
51
Control Register (FMC_CTL)
52
Address Register (FMC_ADDR)
53
Option Bytes Status Register (FMC_OBSTAT)
54
Write Protection Register (FMC_WP)
54
Wait State Enable Register (FMC_WSEN)
55
Product ID Register (FMC_PID)
55
Power Management Unit (PMU)
57
Overview
57
Characteristics
57
Function Overview
57
Figure 3-1. Power Supply Overview
57
Backup Domain
59
Dda
59
VDD Domain
60
Figure 3-2. Waveform of the POR/PDR
60
1.2V Power Domain
61
Figure 3-3. Waveform of LVD Threshold
61
Power Saving Modes
62
Table 3-1. Power Saving Mode Summary
63
Register Definition
64
Control Register (PMU_CTL)
64
Power Control/Status Register (PMU_CS)
65
Reset and Clock Unit (RCU)
67
Reset Control Unit (RCTL)
67
Overview
67
Function Overview
67
Clock Control Unit (CCTL)
68
Overview
68
Figure 4-1. the System Reset Circuit
68
Figure 4-2. Clock Tree
69
Characteristics
70
Function Overview
70
Figure 4-3. HXTAL Clock Source
70
Table 4-1. Clock Source Select
73
Table 4-2. Core Domain Voltage Selected in Deep-Sleep Mode
73
Register Definition
74
Control Register 0 (RCU_CTL0)
74
Configuration Register 0 (RCU_CFG0)
75
Interrupt Register (RCU_INT)
79
APB2 Reset Register (RCU_APB2RST)
82
APB1 Reset Register (RCU_APB1RST)
83
AHB Enable Register (RCU_AHBEN)
85
APB2 Enable Register (RCU_APB2EN)
87
APB1 Enable Register (RCU_APB1EN)
88
Backup Domain Control Register (RCU_BDCTL)
90
Reset Source /Clock Register (RCU_RSTSCK)
92
AHB Reset Register (RCU_AHBRST)
93
Configuration Register 1 (RCU_CFG1)
94
Configuration Register 2 (RCU_CFG2)
95
Control Register 1 (RCU_CTL1)
96
APB1 Additional Enable Register (RCU_ADDAPB1EN)
97
APB1 Additional Reset Register (RCU_ADDAPB1RST)
97
Voltage Key Register (RCU_VKEY)
98
Deep-Sleep Mode Voltage Register (RCU_DSV)
98
Power down Voltage Select Register (RCU_PDVSEL)
99
Interrupt / Event Controller (EXTI)
100
Overview
100
Characteristics
100
Interrupts Function Overview
100
Table 5-2. NVIC Exception Types in Cotrex
101
Table 5-3. Interrupt Vector Table
101
External Interrupt and Event Block Diagram
103
External Interrupt and Event Function Overview
103
Figure 5-1. Block Diagram of EXTI
103
Table 5-4. EXTI Source
104
Register Definition
106
Interrupt Enable Register (EXTI_INTEN)
106
Event Enable Register (EXTI_EVEN)
106
Rising Edge Trigger Enable Register (EXTI_RTEN)
107
Falling Edge Trigger Enable Register (EXTI_FTEN)
107
Software Interrupt Event Register (EXTI_SWIEV)
108
Pending Register (EXTI_PD)
109
General-Purpose I/Os (GPIO)
110
Overview
110
Characiteristics
110
Function Overview
110
Table 6-1. GPIO Configuration Table
110
GPIO Pin Configuration
111
Figure 6-1. Basic Structure of a General-Pupose I/O
111
Alternate Functions (AF)
112
Additional Functions
112
Input Configuration
112
Figure 6-2. Basic Structure of Input Configuration
112
Output Configuration
113
Analog Configuration
113
Figure 6-3. Basic Structure of Output Configuration
113
Alternate Function (AF) Configuration
114
Figure 6-4. Basic Structure of Analog Configuration
114
Figure 6-5. Basic Structure of Alternate Function Configuration
114
GPIO Locking Function
115
GPIO Single Cycle Toggle Function
115
Register Definition
116
Port Control Register (Gpiox_Ctl, X=A
116
Port Output Mode Register (Gpiox_Omode, X=A
117
Port Output Speed Register (Gpiox_Ospd, X=A
119
Port Pull-Up/Down Register (Gpiox_Pud, X=A
121
Port Input Status Register (Gpiox_Istat, X=A
122
Port Output Control Register (Gpiox_Octl, X=A
123
Port Bit Operate Register (Gpiox_Bop, X=A
123
Port Configuration Lock Register (Gpiox_Lock, X=A, B)
124
Alternate Function Selected Register0 (Gpiox_Afsel0, X=A, B, C)
125
Alternate Function Selected Register1 (Gpiox_Afsel1, X=A,B,C)
126
Bit Clear Register (Gpiox_Bc, X=A
127
Cyclic Redundancy Checks Management Unit (CRC)
128
Overview
128
Characteristics
128
Function Overview
129
Figure 7-1. Block Diagram of CRC Management Unit
129
Register Definition
131
Data Register (CRC_DATA)
131
Free Data Register (CRC_FDATA)
131
Control Register (CRC_CTL)
132
Initialization Data Register (CRC_IDATA)
132
Direct Memory Access Controller (DMA)
134
Overview
134
Characteristics
134
Block Diagram
135
Function Overview
135
DMA Operation
135
Figure 8-1. Block Diagram of DMA
135
Table 8-1. DMA Transfer Operation
136
Peripheral Handshake
137
Arbitration
137
Figure 8-2. Handshake Mechanism
137
Address Generation
138
Circular Mode
138
Memory to Memory Mode
138
Channel Configuration
138
Interrupt
139
Figure 8-3. DMA Interrupt Logic
139
Table 8-2. Interrupt Events
139
DMA Request Mapping
140
Table 8-3. DMA Requests for each Channel
140
Figure 8-4. DMA Request Mapping
141
Register Definition
143
Interrupt Flag Register (DMA_INTF)
143
Interrupt Flag Clear Register (DMA_INTC)
143
Channel X Control Register (Dma_Chxctl)
144
Channel X Counter Register (Dma_Chxcnt)
146
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
147
Channel X Memory Base Address Register (Dma_Chxmaddr)
147
Debug (DBG)
149
Overview
149
Serial Wire Debug Port Overview
149
Pin Assignment
149
JEDEC-106 ID Code
149
Debug Hold Function Overview
150
Debug Support for Power Saving Mode
150
Debug Support for TIMER, I2C, RTC, WWDGT and FWDGT
150
DBG Registers
151
ID Code Register (DBG_ID)
151
Control Register 0(DBG_CTL0)
151
Control Register 1 (DBG_CTL1)
153
Analog to Digital Converter (ADC)
155
Overview
155
Characteristics
155
Pins and Internal Signals
156
Figure 10-1. ADC Module Block Diagram
156
Table 10-1. ADC Internal Input Signals
156
Table 10-2. ADC Input Pins Definition
156
Function Overview
157
Foreground Calibration Function
157
Dual Clock Domain Architecture
158
ADCON Enable
158
Routine Sequence
158
Operation Modes
158
Figure 10-2. Single Operation Mode
158
Figure 10-3. Continuous Operation Mode
159
Figure 10-4. Scan Operation Mode, Continuous Disable
160
Figure 10-5. Scan Operation Mode, Continuous Enable
160
Conversion Result Threshold Monitor Function
161
Data Storage Mode
161
Figure 10-6. Discontinuous Operation Mode
161
Sample Time Configuration
162
Figure 10-7. Data Storage Mode of 12-Bit Resolution
162
Figure 10-8. Data Storage Mode of 10-Bit Resolution
162
Figure 10-9. Data Storage Mode of 8-Bit Resolution
162
Figure 10-10. Data Storage Mode of 6-Bit Resolution
162
External Trigger Configuration
163
DMA Request
163
ADC Internal Channels
163
Table 10-3. External Trigger Source for ADC Routine Sequence
163
Battery Voltage Monitoring
164
ADC Interrupts
164
Register Definition
165
Status Register (ADC_STAT)
165
Control Register 0 (ADC_CTL0)
165
Control Register 1 (ADC_CTL1)
167
Sampling Time Register 0 (ADC_SAMPT0)
168
Sampling Time Register 1 (ADC_SAMPT1)
169
Watchdog High Threshold Register (ADC_WDHT)
170
Watchdog Low Threshold Register (ADC_WDLT)
171
Routine Sequence Register 0 (ADC_RSQ0)
171
Routine Sequence Register 1 (ADC_RSQ1)
172
Routine Sequence Register 2 (ADC_RSQ2)
172
Routine Data Register (ADC_RDATA)
173
Digital-To-Analog Converter (DAC)
173
Overview
173
Characteristic
174
Figure 11-1. DAC Block Diagram
174
Table 11-1. DAC I/O Description
174
Function Overview
175
DAC Enable
175
DAC Output Buffer
175
DAC Data Configuration
175
DAC Trigger
175
Table 11-2. External Triggers of DAC
175
DAC Workflow
176
DAC Output Calculate
176
DMA Function
176
Register Definition
177
Control Register (DAC_CTL)
177
Software Trigger Register (DAC_SWT)
178
DAC0 12-Bit Right-Aligned Data Holding Register (DAC0_R12DH)
178
DAC0 12-Bit Left-Aligned Data Holding Register (DAC0_L12DH)
179
DAC0 8-Bit Right-Aligned Data Holding Register (DAC0_R8DH)
179
DAC0 Data Output Register (DAC0_DO)
180
Status Register (DAC_STAT)
180
Comparator (CMP)
182
Overview
182
Characteristics
182
Function Overview
182
CMP Clock and Reset
183
CMP I/O Configure
183
Figure 12-1. CMP Block Diagram
183
CMP Operating Mode
184
CMP Hysteresis
184
CMP Register Write Protection
184
Figure 12-2. CMP Hysteresis
184
Register Definition
185
Control/Status Register (CMP_CS)
185
Watchdog Timer (WDGT)
189
Free Watchdog Timer (FWDGT)
189
Overview
189
Characteristics
189
Function Overview
189
Figure 13-1. Free Watchdog Timer Block Diagram
190
Table 13-1. Min / Max FWDGT Timeout Period at 40 Khz (IRC40K)
191
Register Definition
192
Window Watchdog Timer (WWDGT)
196
Overview
196
Characteristics
196
Function Overview
196
Figure 13-2. Window Watchdog Timer Block Diagram
197
Figure 13-3. Window Watchdog Timer Timing Diagram
198
Table 13-2. Min-Max Timeout Value at 36 Mhz (Fpclk1)
198
Register Definition
199
Real-Time Clock(RTC)
201
Overview
201
Characteristics
201
Function Overview
202
Block Diagram
202
Clock Source and Prescalers
202
Figure 14-1. Block Diagram of RTC
202
Shadow Registers Introduction
203
Configurable and Field Maskable Alarm
203
RTC Initialization and Configuration
204
Calendar Reading
205
Resetting the RTC
206
RTC Shift Function
206
RTC Reference Clock Detection
207
RTC Smooth Digital Calibration
208
Time-Stamp Function
210
Tamper Detection
210
Calibration Clock Output
211
Alarm Output
211
RTC Power Saving Mode Management
212
RTC Interrupts
212
Table 14-1. RTC Power Saving Mode Management
212
Table 14-2. RTC Interrupts Control
212
Register Definition
213
Time Register (RTC_TIME)
213
Date Register (RTC_DATE)
213
Control Register (RTC_CTL)
214
Status Register (RTC_STAT)
216
Prescaler Register (RTC_PSC)
218
Alarm 0 Time and Date Register (RTC_ALRM0TD)
219
Write Protection Key Register (RTC_WPK)
220
Sub Second Register (RTC_SS)
220
Shift Function Control Register (RTC_SHIFTCTL)
221
Time of Time Stamp Register (RTC_TTS)
221
Date of Time Stamp Register (RTC_DTS)
222
Sub Second of Time Stamp Register (RTC_SSTS)
223
High Resolution Frequency Compensation Register (RTC_HRFC)
223
Tamper Register (RTC_TAMP)
224
Alarm 0 Sub Second Register (RTC_ALRM0SS)
226
Backup Registers (Rtc_Bkpx) (X=0
227
Timer (Timerx)
229
Table 15-1. Timers (Timerx) Are Devided into Six Sorts
229
Advanced Timer (Timerx,X=0)
230
Overview
230
Characteristics
230
Block Diagram
231
Function Overview
231
Figure 15-1. Advanced Timer Block Diagram
231
Figure 15-2. Timing Chart of Internal Clock Divided by 1
232
Figure 15-3. Timing Chart of PSC Value Change from 0 to 2
233
Figure 15-4. Timing Chart of up Counting Mode, PSC=0/2
234
Figure 15-5. Timing Chart of up Counting Mode , Change Timerx_Car on the Go
234
Figure 15-6. Timing Chart of down Counting Mode, PSC=0/2
235
Figure 15-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
236
Figure 15-8. Center-Aligned Counter Timechart
236
Figure 15-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
238
Figure 15-10. Repetition Counter Timing Chart of up Counting Mode
238
Figure 15-11. Repetition Counter Timing Chart of down Counting Mode
239
Figure 15-12. Channel Input Capture Principle
240
Figure 15-13. Channel Output Compare Principle (with Complementary Output, X=0, 1, 2)
241
Figure 15-14. Channel Output Compare Principle (CH3_O)
241
Figure 15-15. Output-Compare under Three Modes
242
Figure 15-16. EAPWM Timechart
243
Figure 15-17. CAPWM Timechart
243
Table 15-2. Complementary Outputs Controlled by Parameters
246
Figure 15-18. Channel Output Complementary PWM with Dead-Time Insertion
247
Figure 15-19. Output Behavior in Response to a Break(the Break High Active)
248
Figure 15-20. Example of Counter Operation in Quadrature Decoder Interface Mode
249
Figure 15-21. Example of Quadrature Decoder Interface Mode with CI0FE0 Polarity Inverted
249
Table 15-3. Counting Direction Versus Quadrature Decode Signals
249
Figure 15-22. Hall Sensor I S Used to BLDC Motor
250
Figure 15-23. Hall Sensor Timing between Two Timers
251
Table 15-4. Slave Mode Example Table
251
Figure 15-24. Restart Mode
252
Figure 15-25. Pause Mode
252
Figure 15-26. Event Mode
253
Figure 15-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
254
Figure 15-28. TIMER0 Master/Slave Mode Timer Example
254
Table 15-5. Input Trigger of Timer0
255
Figure 15-29. Triggering TIMER0 with Enable of TIMER2
256
Figure 15-30. Triggering TIMER0 and TIMER2 with Timer2'S CI0 Input
257
Timerx Registers(X=0)
258
General Level0 Timer (Timerx, X=1, 2)
285
Overview
285
Characteristics
285
Block Diagram
285
Figure 15-31. General Level 0 Timer Block Diagram
285
Function Overview
286
Figure 15-32. Timing Chart of Internal Clock Divided by 1
287

GigaDevice Semiconductor GD32F150 Series User Manual

GigaDevice Semiconductor GD32F150 Series User Manual (685 pages)

ARM Cortex-M3 32-bit MCU

Brand: GigaDevice Semiconductor | Category: Microcontrollers | Size: 26 MB

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