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Chipset Overview
The Grand Champion SL
"Champion" chipset technology. The chipset for the X5DE8-GG/X5DEI-GG/
X5DEE-M is comprised of a North Bridge (CMIC-SL) and a South Bridge
(CSB6).
The North Bridge interfaces directly to the processors via a 100 MHz Host
bus and integrates the functions of the main memory subsystem and the
IMB bus interface unit. The memory subsystem consists of a 4-DIMM con-
figuration accessed over a 266 MHz memory bus at a peak bandwidth of
1.6 GB/sec.
The South Bridge provides various integrated functions, including the PCI
bridge and support for UDMA100, security (passwords and system protec-
tion), Plug & Play, USBs, power management, interrupt controllers and the
LPC Bus.
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Special Features
ATI Graphics Controller
The X5DE8-GG/X5DEI-GG/X5DEE-M has an integrated ATI video controller
based on the Rage XL graphics chip. The Rage XL fully supports sideband
addressing and AGP texturing. This onboard graphics package can provide
a bandwidth of up to 512 MB/sec over a 32-bit graphics memory bus.
BIOS Recovery
The BIOS Recovery function allows you to recover your BIOS image file if
the BIOS flashing procedure fails (see Section 3-3).
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond
when AC power is lost and then restored to the system. You can choose
for the system to remain powered off (in which case you must hit the
power switch to turn it back on) or for it to automatically return to a power-
TM
is a fourth-generation product of ServerWorks
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Chapter 1: Introduction
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