Related Manuals for Supermicro X5DL8-GG
Summary of Contents for Supermicro X5DL8-GG
- Page 1 ® UPER SUPER X5DL8-GG SUPER X5DLR-8G2+ SUPER X5DLR-8G2 USER’S MANUAL Revision 1.0c...
- Page 2 The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product. Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not copy any part of this document.
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Page 3: Manual Organization
CMOS. For quick reference, a general FAQ (Frequently Asked Ques- tions) section is provided. Instructions are also included for contacting technical support. In addition, you can visit our web site at www.supermicro.com/ techsupport.htm for more detailed information. Chapter 4 includes an introduction to BIOS and provides detailed information on running the CMOS Setup utility. -
Page 4: Table Of Contents
Contacting Supermicro ... 1-2 Super X5DL8-GG Image ... 1-4 Super X5DLR-8G2 Image ... 1-5 Super X5DL8-GG Layout ... 1-6 Super X5DL8-GG Quick Reference ... 1-7 Super X5DLR-8G2 Layout ... 1-8 Super X5DLR-8G2/X5DLR-8G2+ Quick Reference ... 1-9 Motherboard Features ... 1-10 ServerWorks GC - LE Chipset System Block Diagram ... - Page 5 Fan Detection Select ... 2-17 Chassis/Overheat Fan Select ... 2-17 Watch Dog ... 2-17 GLAN1 Enable/Disable ... 2-18 GLAN2 Enable/Disable ... 2-18 SCSI Enable/Disable ... 2-18 SCSI Termination Enable/Disable ... 2-18 PCI-X Bus Speed Setting (X5DL8-GG) ... 2-19 Table of Contents...
- Page 6 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PCI-X Bus Speed Setting (X5DLR-8G2/X5DLR-8G2+) ... 2-19 33 MHz PCI Enable/Disable ... 2-19 Front Side Bus Speed ... 2-20 Spread Spectrum ... 2-20 PCI 3.3V Standby Enable/Disable ... 2-20 VGA Enable/Disable ... 2-20 Main Power Override ... 2-21 Parallel Port, Floppy/Hard Disk Drive and SCSI Connections ...
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Page 7: Chapter 1: Introduction
One (1) I/O backpanel shield Two (2) fan/heatsink assemblies (Fan-042 - retail only) Two (2) sets of heatsink retention clips (SKT-095-604, 4 total) One (1) Supermicro CD or diskettes containing drivers and utilities One (1) User's/BIOS Manual SCSI Accessories One (1) 68-pin LVD SCSI cable (retail only) -
Page 8: Contacting Supermicro
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Contacting Supermicro Headquarters Address: SuperMicro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Web Site: www.supermicro.com Europe Address: SuperMicro Computer B.V. - Page 9 Chapter 1: Introduction Notes...
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Page 10: Super X5Dl8-Gg Image
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-1. SUPER X5DL8-GG Image... -
Page 11: Super X5Dlr-8G2 Image
Chapter 1: Introduction Figure 1-2. SUPER X5DLR-8G2 Image Note: the X5DLR-8G2+ has the same layout but has 1) no parallel (printer) port and 2) a standard PCI-X slot. -
Page 12: Super X5Dl8-Gg Layout
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-3. SUPER X5DL8-GG Layout Keyboard/Mouse Bank 1A USB0/1 Bank 1B Bank 2A Bank 2B COM1 Bank 3A Parallel Bank 3B Port Bank 4A Bank 4B GLAN1 Rage XL BATTERY GLAN2 D1-D4 D5-D8 COM2 JBT1 PCI-X #6... - Page 13 X5DL8-GG Quick Reference Jumper Description 33 MHz PCI Enable/Disable Spread Spectrum SCSI Enable/Disable JBT1 CMOS Clear PCI 3.3V Standby En/Dis Watch Dog GLAN2 Enable/Disable Main Power Override JP12 System Bus Speed JP48 Chassis/Overheat Fan Select JP54 GLAN1 Enable/Disable JP56 VGA Enable/Disable...
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Page 14: Super X5Dlr-8G2 Layout
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 1-4. SUPER X5DLR-8G2 Layout* Keyboard/Mouse Bank 2B USB0/1 Bank 2A Bank 1B Bank 1A COM1 Bank 0B Parallel Bank 0A Port GLAN1 CIOB-E GLAN2 D1-D4 D5-D8 Rage XL BATTERY JP56 AIC-7902 JPA1 USB2/3 Note: the X5DLR-8G2+ has the same layout but has 1) no parallel (printer) port and 2) a standard PCI-X slot. - Page 15 X5DLR-8G2+/X5DLR-8G2 Quick Reference Jumper Description Spread Spectrum SCSI Enable/Disable JBT1 CMOS Clear Speaker Enable/Disable Watch Dog JP12 System Bus Speed JP48 Chassis/Overheat Fan Select JP56 VGA Enable/Disable JP58 Fan Detection Select JPA1/A2 SCSI Channel A/B Termination Open (Terminated) PCI-X Speed Settings Connector Description ATX POWER...
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Page 16: Motherboard Features
Note: Please refer to the motherboard specifications pages on our web site for updates on supported processors (http://www.supermicro.com/Product_page/product-m.htm). Memory • X5DL8-GG: Eight 184-pin DIMM sockets supporting up to 16 GB of registered ECC DDR-266/200 (PC2100/1600) SDRAM • X5DLR-8G2+/X5DLR-8G2: Six 184-pin DIMM sockets supporting up to 12 GB of registered ECC DDR-266/200 (PC2100/1600) SDRAM Note: Memory is 2-way interleaved meaning DIMM modules must be installed two at a time. - Page 17 • Adaptec 2015S SCSI RAID support (X5DLR-8G2+/X5DLR-8G2) • Integrated ATI Rage XL Graphics Controller • Intel 82540EM Gb Ethernet controller (X5DL8-GG - LAN1) • Broadcom BCM5703 Gb Ethernet controller (X5DL8-GG - LAN2) • Broadcom BCM5704 dual Gb Ethernet controller (X5DLR-8G2+/X5DLR- 8G2) •...
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Page 18: System Block Diagram
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual ATI XL PCI Bus VG A Processor 1 LAN1 ATA 100 Ports CSB5 ( South USB Ports Bri dge) SM Bus LPC Bus Seri al Port SI O Paral l el Port Fl oppy Port Figure 1-5 . -
Page 19: Chipset Overview
SMBus. The CIOBX2 is an integrated IO bridge that provides high-performance data flow between the IMB interface and the dual peer PCI-X bus interfaces. The X5DL8-GG has two CIOBX2 bridges (four buses). Special Features ATI Graphics Controller The X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 has an integrated ATI video con- troller based on the Rage XL graphics chip. -
Page 20: Pc Health Monitoring
Always On. PC Health Monitoring This section describes the PC health monitoring features of the SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2. It has an onboard System Hardware Monitor chip that supports PC health monitoring. Onboard Voltage Monitors for the CPU Cores, Chipset Voltage, +5V, +12V and 5V Standby An onboard voltage monitor will scan these voltages continuously. -
Page 21: 1-5 Acpi Features
The system BIOS is protected by hardware that prevents viruses from infecting the BIOS area. through the flash utility provided by Supermicro. This feature can prevent viruses from infecting the BIOS area and destroying valuable data. Auto-Switching Voltage Regulator for the CPU Core The auto-switching voltage regulator for the CPU core can support up to 20A current and auto-sense voltage IDs ranging from 1.4V to 3.5V. - Page 22 LAN traffic is kept to a minimum and users are not interrupted. The motherboards have a 3-pin header (WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability. Note that Wake- On-LAN can only be used with an ATX 2.01 (or above) compliant power...
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Page 23: Power Supply
As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates. The SUPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 accommodates ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. - Page 24 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual complete modem control capability and a processor interrupt system. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor inter- rupt system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K,...
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Page 25: Chapter 2: Installation
Static-Sensitive Devices Electric-Static-Discharge (ESD) can damage electronic components. To pre- vent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD. Precautions • Use a grounded wrist strap designed to prevent static discharge. •... -
Page 26: Pga Processor And Heatsink Installation
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PGA Processor and Heatsink Installation When handling the processor package, avoid placing direct pressure on the label area of the fan. Also, do not place the motherboard on a conductive surface, which can damage the BIOS battery and prevent the system from booting up. - Page 27 4. Secure the other retention bracket into position by repeating Step 3. 5. Lift the lever on the CPU socket: lift the the lever completely or you will damage the CPU socket when power is applied. (Install CPU1 first.) 6. Install the CPU in the socket. Make sure that pin 1 of the CPU is seated on pin 1 of the socket (both corners are marked with a triangle).
- Page 28 Triangle Mounting the Motherboard in the Chassis All motherboards have standard mounting holes to fit different types of chassis. Make sure the location of all the mounting holes for both the motherboard and the chassis match. Although a chassis may have both plastic and metal mounting fasteners, metal ones are highly recommended because they ground the motherboard to the chassis.
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Page 29: Installing Dimms
DIMM Installation (See Figure 2-2) 1. Insert an even number of memory modules. Interleaved memory requires you to install two modules at a time. With the X5DL8-GG, begin from the two slots of the last bank and working your way toward the two slots of Bank 1. -
Page 30: Ioports/Control Panel Connectors
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Figure 2-2. To Install: Insert the module vertically a n d p r e s s d o w n u n t i l i t snaps into place. Pay atten- tion to the notch on the bot- tom of the module. -
Page 31: Front Control Panel
Front Control Panel JF1 contains header pins for various front control panel connectors. These connectors are designed for use with Supermicro server chassis. Figure 2-4 for the pin locations of the various front control panel buttons and LED indicators. Refer to the following section for descriptions and pin definitions. -
Page 32: Connecting Cables
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Connecting Cables ATX Power Connector power supply meets the SSI (Superset ATX) 24- pin specification, however it also supports a 20-pin power supply connector. Make sure that the ori- entation of the PS connector is correct. -
Page 33: Hdd Led
HDD LED The HDD LED (for IDE and SCSI disk drives) connection is located on pins 13 and 14 of JF1. Attach the IDE hard drive LED cable to these pins to display disk activity. Refer to the table on the right for pin definitions. -
Page 34: Power Fail Led
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Power Fail LED The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table on the right for pin definitions. Reset The Reset connection is located on pins 3 and 4 of JF1. Attach it to the hardware reset switch on the computer case. -
Page 35: Serial Ports
Serial Ports The COM1 serial port is located under the parallel port (see Figure 2-3). See the table on the right for definitions. motherboard layout diagrams for the location of the COM2 connec- tor, which is a header. PS/2 Keyboard and Mouse Ports The ATX PS/2 keyboard and the PS/2 mouse are located on J11. -
Page 36: Hd Led Indicator
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual HD LED Indicator (JF2) The HD LED connector located at JF2 is used to indicate activity on any hard drive (IDE, SCSI or CD- ROM). Power LED (JF2) The Power LED connection located at JF2 is used to inform you that power is being supplied to the motherboard. -
Page 37: Wake-On-Lan
Wake-On-LAN (X5DL8-GG) The Wake-On-LAN header is des- ignated as WOL. See the table on the right for pin definitions. must have a LAN card with a Wake-on-LAN connector and cable to use this feature. Chassis Intrusion A Chassis Intrusion header is lo- cated at JP57. -
Page 38: Onboard Indicators
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Onboard Indicators GLAN1/GLAN2 LEDs Each of the Ethernet ports (located beside the VGA port) has a yellow and a green LED. See the tables below for the functions associated with these LEDs. On each Gb LAN port, the yellow LED indicates activity while the other LED may be green, orange or off to indicate the speed of the connec- tion (as specified in the tables below). -
Page 39: Cr5 Led
CR5 LED CR5 is an onboard LED that serves as a power indicator. table on the right for the meaning of each of the three colors dis- played by CR5. DIP Switch Settings DIP Switch 4: Processor Speed The red "DIP" switch labeled SW4 has four individual switches, which are used to set the speed of the processor. -
Page 40: Jumper Settings
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Jumper Settings Explanation of Jumpers To modify the operation of the motherboard, jumpers can be used choose optional settings. create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board. -
Page 41: Fan Detection Select
SpeakerEnable/Disable (X5DLR-8G2+, X5DLR-8G2) To disable the onboard speaker, remove the jumper from JP2 (see the table on the right). Fan Detection Select JP58 allows you to select which fan speed to have displayed in the Hardware Monitors section of BIOS (the CPU1/2 fans or the CPU1/CPU2 Chassis fans). -
Page 42: Glan1 Enable/Disable
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual GLAN1 Enable/Disable (X5DL8-GG) Change the setting of jumper JP54 to enable or disable the onboard LAN1 port on the motherboard. See the table on the right for jumper settings. The default set- ting is pins 1-2. -
Page 43: Pci-X Bus Speed Setting (X5Dl8-Gg)
PCI-X Bus Speed Setting (X5DL8-GG) Jumpers P1, P2, S1 and S2 are used to change the speeds for the four PCI-X buses. See the table on the right for jumper settings. PCI-X Buses: S1: Bus for PCI-X slot #1 and SCSI... -
Page 44: Front Side Bus Speed
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Front Side Bus Speed JP12 is used to set the system (front side) bus speed for the pro- cessors. It is best to keep this jumper set to Auto. See the table on the right for jumper settings. -
Page 45: Main Power Override
Main Power Override (X5DL8-GG) Instead of using the chassis power on switch, you may close jumper JP7 to apply power to the system. This effectively disables the power button from turning off the system. See the table on the right for jumper settings. The de- fault setting is Open (normal). -
Page 46: Floppy Connector
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Floppy Connector The floppy connector is located on J12. See the table below for pin definitions. IDE Connectors There are no jumpers to configure the onboard IDE#1 and #2 connectors (J18 and J19, respectively). See the table on the right for pin definitions. -
Page 47: Ultra320 Scsi Connector
Ultra320 SCSI Connector Refer to the table below for the pin definitions of the Ul- tra320 SCSI connectors lo- cated at JA1 and JA2. 68-pin Ultra320 SCSI Connectors (JA1 and JA2) Connector Contact Number Signal Names GROUN D DIFFSENS TERMPW R TERMPW R RESERVED GROUN D... -
Page 48: 2-10 Installing Software Drivers
2-10 Installing Software Drivers After all the hardware has been installed you must install the software drivers. The necessary drivers are all included on the Supermicro CD that came packaged with your motherboard. CDROM drive, the display shown in Figure 2-5 should appear. (If this dis- play does not appear, click on the My Computer icon and then on the icon representing your CDROM drive. -
Page 49: Chapter 3: Troubleshooting
Troubleshooting Procedures Use the following procedures to troubleshoot your system. followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Note: Always disconnect the power cord before adding, changing or installing any hardware components. -
Page 50: Memory Errors
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual If you are a system integrator, VAR or OEM, a POST diagnos- tics card is recommended. For I/O port 80h codes, refer to Memory Errors 1. Make sure the DIMM modules are properly and fully installed. -
Page 51: Frequently Asked Questions
4. Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at support@supermicro.com, by fax at (408) 503- 8019 or by phone at (408) 503-8000, option 2. - Page 52 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual find the readme.txt (flash instructions), the flash.bat (BIOS flash utility) and the BIOS image (xxxxxx.rom) files. Copy these files onto a bootable floppy and reboot your system. It is not necessary to set BIOS boot block protec- tion jumpers on the motherboard.
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Page 53: Returning Merchandise For Service
Chapter 3: Troubleshooting BIOS is not in control such as during memory count (the first screen that appears when the system is turned on), the momentary on/off switch must be held for more than four seconds to shut down the system. This feature is required to implement the ACPI features on the motherboard. - Page 54 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...
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Page 55: Chapter 4: Amibios
Introduction This chapter describes the AMIBIOS for the X5DL8-GG/X5DLR-8G2+/X5DLR- 8G2. The AMI ROM BIOS is stored in a Flash EEPROM and can be easily upgraded using a floppy disk-based program. Note: Due to periodic changes to BIOS, some settings may have been added or deleted and might not yet be recorded in this manual. -
Page 56: Bios Features
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual BIOS Features • Supports Plug and Play V1.0A and DMI 2.3 • Supports Intel PCI (Peripheral Component Interconnect) (PME) local bus specification 2.2 • Supports Advanced Power Management (APM) specification v 1.1 • Supports ACPI •... - Page 57 The Main BIOS Setup Menu Press the <Delete> key during the POST (Power On Self Test) to enter the Main Menu of the BIOS Setup Utility. All Main Setup options are described in this section. The Main BIOS Setup screeen is displayed below. Main Advanced Chipset PCIPnP AMIBIOS Version:...
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Page 58: Advanced Bios Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Advanced BIOS Setup Choose Advanced BIOS Setup from the AMIBIOS Setup Utility main menu with the Left/Right arrow keys. You should see the following display. Select one of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub screen for that item. -
Page 59: Super Io Configuration
Super IO Configuration Advanced Configure Winbond627F Serial Port(s) and Parallel P Serial Port1 Address Serial Port1 IRQ Serial Port2 Address Serial Port2 IRQ Serial Port2 Mode Parallel Port Address Parallel Port IRQ Parallel Port Mode ECP Mode DMA Channel V07.00 (C)Copyright 1985-2001, American Megatrends, Inc. The Super IO Configuration includes the following items: Serial Port 1 Address This option specifies the base I/O port address of serial port 1. -
Page 60: Ide Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Serial Port 2 Mode Use this option to choose the Serial Port 2 Mode. The settings are Normal, Sharp-IR, SIR and consumer. Parallel Port Address This option specifies the I/O address used by the parallel port. The settings for this item include Disabled, 378, 278 and 3BC. - Page 61 Primary IDE Master When entering "Setup", BIOS automatically detects the presence of IDE devices. This displays the auto detection status of the IDE de- vices. You can also manually configure the IDE drives by providing the following information: This option allows the user to configure the IDE devices. When the desired item is highlighted (selected), press "Enter"...
- Page 62 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual PIO Mode IDE PIO (Programmable I/O) mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode in- creases, the cycle time decreases. The settings are: Auto, 0, 1, 2, 3 and 4.
- Page 63 Chapter 4: AMIBIOS Primary IDE Slave When the system enters "Setup", BIOS automatically detects the presence of IDE devices. This option displays the auto detection status of IDE de- vices. The settings for "Primary IDE Slave" are the same as those for the "Primary IDE Master".
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Page 64: Floppy Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Floppy Configuration Floppy A Use this option to specify which of floppy drive you have installed in the A drive. The settings are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3 1/ 2", 1.44 MB 3 1/2"... - Page 65 Chapter 4: AMIBIOS allows the computer to force a third party BIOS to display during system boot. Keep Current has the system display AMIBIOS information on bootup. BootUp Num Lock This option is used to select the status of the Number Lock function on your keyboard on bootup.
- Page 66 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Wait for F1 if Error This settings for this option are Enabled and Disabled. Disabled: This prevents the AMIBIOS to wait on an error for user intervention. This setting should be used if there is a known reason for a BIOS error to appear. An example would be a system administrator must remote boot the system.
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Page 67: Event Log Configuration
Chapter 4: AMIBIOS Event Log Configuration Event Logging This option Enables or Disables the logging of events. You can use this screen to select options for the Event Log Configuration Settings. You can access sub screens to view the event log and mark all events as read. Use the up and down arrow keys to select an item, and the plus (+) and minus (-) keys to change the option setting. -
Page 68: Peripheral Device Configuration
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Peripheral Device Configuration Power Lost Control This option determines how the system will respond when power is reap- plied after a power loss condition. start up the system when power is reapplied. Always Off means you must push the main power button to restart the system after power is restored. -
Page 69: Chipset Setup
Chipset Setup Choose Chipset Setup from the AMIBIOS Setup Utility main menu. The screen is shown below. All Chipset Setup options are described following the screen. Main Advanced Chipset Memory Timing Control SDRAM CAS Latency MPS 1.4 Support Hyper-threading Auto DQS Setting Support DQS Selection Watch Dog Timer V07.00 (C)Copyright 1985-2002, American Megatrends, Inc. -
Page 70: Pci Pnp Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Hyper-threading Enables hyper-threading if supported by the operating system. threading is a method of creating an additional "virtual" processor by using parallelism to process mulitple instructions simultaneously. The settings for this option are Enabled and Disabled. - Page 71 Chapter 4: AMIBIOS Plug & Play OS This option specifies how Plug and Play devices will be configured. settins are Yes and No. No lets BIOS configure all devices in the system. Yes lets the operating system (if supported) configure PnP devices not required for bootup.
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Page 72: Power Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Power Setup Choose Power Setup from the AMIBIOS Setup main menu. All Power Setup options are described in this section. below. Main Advanced Chipset ACPI Aware O/S Power Management V02.03 (C)Copyright 1985-2002, American Megatrends, Inc. The Power Setup screen is shown... - Page 73 ACPI Aware O/S This option allows the system to utilize Intel's ACPI (Advanced Configuration and Power Interface) specification. Windows 3.x®, and Windows NT® are examples of non-ACPI aware oper- ating systems. Windows 95®, Windows 98®, Windows ME® and Windows 2000® are examples of ACPI aware operating systems. Power Management When enabled, this option displays the following four options relating to power management.
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Page 74: Boot Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Boot Setup Choose Boot Setup from the AMIBIOS Setup main menu. options are described in this section. below. Main Advanced Chipset > Boot Device Priority > Hard Disk Drives > Removable Devices > ATAPI CDROM Drives V02.03 (C)Copyright 1985-2000, American Megatrends, Inc. - Page 75 3rd Boot Device The settings for the 3rd Boot Device are Removable Device, ATAPI CDROM, Hard Drive, Onboard LAN2 Option-ROM and IBA 4.0.1.9 Slot 0102. 4th Boot Device The settings for the 4th Boot Device are Removable Device, ATAPI CDROM, Hard Drive, Onboard LAN2 Option-ROM and IBA 4.0.1.9 Slot 0102.
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Page 76: Security Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Security Setup Choose Security Setup from the AMIBIOS Setup main menu. All Security Setup options are described in this section. The Security Setup screen is shown below. Main Advanced Chipset Supervisor Password User Password > Change Supervisor Password >... - Page 77 Change Supervisor Password This option allows you to change a supervisor password that was entered previously. Change User Password This option allows you to change a user password that was entered previ- ously. Clear User Password Use this option to clear the user password so that it is not required to be entered when the system boots up.
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Page 78: 4-10 Exit Setup
UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual 4-10 Exit Setup Choose Exit Setup from the AMIBIOS Setup main menu. All Exit Setup op- tions are described in this section. The Exit Setup screen is shown below. Main Advanced Chipset > Exit Saving Changes >... - Page 79 Chapter 4: AMIBIOS Load Optimal Defaults Highlighting this setting and then pressing <Enter> provides the optimum performance settings for all devices and system features. Load Failsafe Defaults Highlighting this setting and then pressing <Enter> provides the safest set of parameters for the system. Use them if the system is behaving errati- cally.
- Page 80 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes 4-26...
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Page 81: Appendix Abios Error Beep Codes
BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. The error messages normally appear on the screen. - Page 82 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...
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Page 83: Appendix Bbios Post Checkpoint Codes
BIOS POST Checkpoint Codes When AMIBIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, diagnostic equipment can be attached to the computer to read I/O port 0080h. Uncompressed Initialization Codes The uncompressed initialization checkpoint codes are listed in order of execution: Checkpoint... - Page 84 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in order of execution: Checkpoint Code Description The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test. Initializing the interrupt vector table next.
- Page 85 initialization before the keyboard BAT command is issued. The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard controller. The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.
- Page 86 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Checkpoint Code Description Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on. Any initialization before setting video mode will be done next. Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next.
- Page 87 Checkpoint Code Description Patterns written in base memory. Determining the amount of memory below 1 MB next. The amount of memory below 1 MB has been found and verified. Determining the amount of memory above 1 MB memory next. The amount of memory above 1 MB has been found and verified. Checking for a soft reset and clearing the memory below 1 MB for the soft reset next.
- Page 88 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Checkpoint Code Description The DMA page register test passed. Performing the DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
- Page 89 Checkpoint Code Description Initializing the bus option ROMs from C800 next. See the last page of this chapter for additional information. Initializing before passing control to the adaptor ROM at C800. Initialization before the C800 adaptor ROM gains control has com- pleted.
- Page 90 UPER X5DL8-GG/X5DLR-8G2+/X5DLR-8G2 User’s Manual Notes...