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Supermicro SUPER X5DPL-8GM User Manual

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UPER
SUPER X5DPL-8GM
SUPER X5DPL-iGM
USER'S MANUAL
Revision 1.1

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  • Page 1 ® UPER SUPER X5DPL-8GM SUPER X5DPL-iGM USER’S MANUAL Revision 1.1...
  • Page 2 The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product. Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not copy any part of this document.

  • Page 3: Preface

    Preface About This Manual This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the SUPER X5DPL-8GM/X5DPL-iGM mainboard. The SUPER X5DPL-8GM/ ® X5DPL-iGM supports single or dual Intel...

  • Page 4: Table Of Contents

    Checklist ....................1-1 Contacting Supermicro ................1-2 Super X5DPL-8GM/X5DPL-iGM Image ........... 1-4 Super X5DPL-8GM/X5DPL-iGM Layout ..........1-5 Super X5DPL-8GM/X5DPL-iGM Quick Reference ....... 1-6 Motherboard Features ................1-7 Intel E7501 Chipset: System Block Diagram ........1-9 Chipset Overview ..................1-10 Special Features ................... 1-10 ATI Graphics Controller ................
  • Page 5 Table of Contents Overheat LED ................... 2-9 Power Fail Button ..................2-9 Reset Button ................... 2-10 Power Button ..................2-10 Chassis Intrusion ................... 2-10 Universal Serial Bus (USB0/1) ............2-10 Extra Universal Serial Bus Headers ........... 2-11 Serial Ports ..................... 2-11 LAN (Ethernet) Ports ................
  • Page 6 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Chapter 3: Troubleshooting Troubleshooting Procedures ................ 3-1 Before Power On ..................3-1 No Power ....................3-1 No Video ....................3-1 Memory Errors ..................3-2 Losing the System’s Setup Configuration ........... 3-2 Technical Support Procedures ..............3-2 Frequently Asked Questions ................

  • Page 7: Chapter 1: Introduction

    One (1) USB ribbon cable (retail only) One (1)COM Port w/Cable (retail only) One (1) I/O backpanel shield One (1) Supermicro CD containing drivers and utilities One (1) User's/BIOS Manual Two (2) Pentium 4 Xeon active heatsinks (FAN-042-CF, retail only)

  • Page 8: Contacting Supermicro

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Contacting Supermicro Headquarters Address: SuperMicro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A. Tel: +1 (408) 503-8000 Fax: +1 (408) 503-8008 Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support) Web Site: www.supermicro.com Europe Address: SuperMicro Computer B.V.
  • Page 9 Chapter 1: Introduction Notes...
  • Page 10 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Figure 1-1. SUPER X5DPL-8GM/X5DPL-iGM...

  • Page 11: Super X5Dpl-8Gm/X5Dpl-Igm Layout

    Chapter 1: Introduction Figure 1-2. SUPER X5DPL-8GM/X5DPL-iGM Layout* (not drawn to scale) Keyboard ATX PWR CONN JP40 Mouse Chassis Fan3 CPU/Ch Fan DIMM #1A USB0/1 BANK 1 JP36 DIMM #1B CPU 1 DIMM #2A COM1 BANK 2 DIMM #2B DIMM #3A...
  • Page 12 UPER X5DPL-8GM/X5DPL-iGM User’s Manual X5DPL-8GM/X5DPL-iGM Quick Reference Jumper Description Default Setting JBT1 CMOS Clear See Section 2-6 JP3/JD3 Mb/Gb LAN Enable/Disable Pins 1-2 (Enabled) VGA Enable/Disable Pins 1-2 (Enabled) JP22* SCSI Enable/Disable Pins 1-2 (Enabled) JP37 Watch Dog Open (Disabled) JP39 CPU Clock Pins 1-2 (Auto)

  • Page 13: Motherboard Features

    533/400 MHz front side (system) bus speed. Note: Please refer to the support section of our web site for a complete listing of supported processors (http://www.supermicro.com/TechSupport.htm). M e m o r y • Six 184-pin DDR DIMM sockets supporting up to 12 GB of registered ECC DDR-266/200 (PC2100/1600) SDRAM Note: Interleaved memory;...
  • Page 14 UPER X5DPL-8GM/X5DPL-iGM User’s Manual ACPI/PC 98 Features (optional) • Microsoft OnNow • Slow blinking LED for suspend state indicator • Main switch override mechanism • External modem ring-on Onboard I/O • AIC-7902 for dual channel Ultra320 SCSI (X5DPL-8GM only) • Adaptec SCSI RAID 2010S supported (X5DPL-8GM only) •...

  • Page 15: Intel E7501 Chipset: System Block Diagram

    Chapter 1: Introduction Figure 1-3. Intel E7501 Chipset: System Block Diagram Processor Processor PCI-X Slot #4 PCI-X Slot 533/400 MHz Host Bus 66 MHz SCSI PCI Bus P64H2 DDR266/200 266/200 MHz Memory Bus 100 MHz PCI-X Bus PCI-X Slot #6 UDMA/100 Gbit LAN 33 MHz PCI Bus...

  • Page 16: Chipset Overview

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Chipset Overview The Intel E7501 (Plumas) chipset is a high-performance chipset with a per- formance and feature-set designed for mid-range, dual processor servers. The E7501 chipset consists of four major components: the Memory Control- ler Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0 (P64H2) and the 82808AA Host Channel Adapter (VxB).

  • Page 17: Recovery From Ac Power Loss

    Chapter 1: Introduction Recovery from AC Power Loss BIOS provides a setting for you to determine how the system will respond when AC power is lost and then restored to the system. You can choose for the system to remain powered off (in which case you must hit the power switch to turn it back on) or for it to automatically return to a power- on state.

  • Page 18: Acpi Features

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual CPU Fan Auto-Off in Sleep Mode The CPU fan activates when the power is turned on. It continues to operate when the system enters Standby mode. When in sleep mode, the CPU will not run at full power, thereby generating less heat. CPU Overheat LED JOH1 is a header used to connect to a CPU overheat LED.
  • Page 19 Chapter 1: Introduction In addition to enabling operating system-directed power management, ACPI provides a generic system event mechanism for Plug and Play and an oper- ating system-independent interface for configuration control. ACPI lever- ages the Plug and Play BIOS data structures while providing a processor architecture-independent implementation that is compatible with both Win- dows 2000 and Windows NT 5.0.

  • Page 20: Power Supply

    It is even more important for processors that have high CPU clock rates. The SUPER X5DPL-8GM/X5DPL-iGM accommodates ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate. You should use one that will supply at least...

  • Page 21: Super I/O

    Chapter 1: Introduction Super I/O The disk drive adapter functions of the Super I/O chip include a floppy disk drive controller that is compatible with industry standard 82077/765, a data separator, write pre-compensation circuitry, decode logic, data rate selec- tion, a clock generator, drive interface control logic and interrupt and DMA logic.
  • Page 22 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Notes 1-16...

  • Page 23: Chapter 2: Installation

    Chapter 2: Installation Chapter 2 Installation Static-Sensitive Devices Electric-Static-Discharge (ESD) can damage electronic components. To pre- vent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD.

  • Page 24: Pga Processor And Heatsink Installation

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual PGA Processor and Heatsink Installation When handling the processor package, avoid placing direct pressure on the label area of the fan. Also, do not place the motherboard on a conductive surface, which can damage the BIOS battery and prevent the system from booting up. IMPORTANT: Always connect the power cord last and always remove it before adding, removing or changing any hardware components.
  • Page 25 Chapter 2: Installation 4. Secure the other retention bracket into position by repeating Step 3. 5. Lift the lever on the CPU socket: lift the lever completely or you will Socket lever damage the CPU socket when power is applied. (Install CPU1 first.) 6.
  • Page 26 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Figure 2-1. PGA604 Socket: Empty and with Processor Installed Lever Pin 1 Warning! Make sure you lift the lever completely when installing the CPU. If the lever is only partly raised, damage to the socket or CPU may result.

  • Page 27: Installing Dimms

    Chapter 2: Installation Installing DIMMs Note: Check the Supermicro web site for recommended memory modules: http://www.supermicro.com/TECHSUPPORT/FAQs/Memory_vendors.htm CAUTION Exercise extreme care when installing or removing DIMM modules to prevent any possible damage. Also note that the memory is interleaved to improve performance (see step 1).

  • Page 28: I/Oports/Control Panel Connectors

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual To Remove: Use your thumbs to gently push near the edge of both ends of the module. This should release it from the slot. I/OPorts/Control Panel Connectors The I/O ports are color coded in conformance with the PC 99 specification. See Figure 2-3 below for the colors and locations of the various I/O ports.
  • Page 29 JF2 contains header pins for various buttons and indicators that are nor- mally located on a control panel at the front of the chassis. These connec- tors are designed especially for use with Supermicro server chassis. See Figure 2-4 for the descriptions of the various control panel buttons and LED indicators.

  • Page 30: Connecting Cables

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Connecting Cables ATX Power Connector ATX Power Supply 24-pin Connector Pin Definitions Pin Number Definition Pin Number Definition The main power supply connector +3.3V +3.3V meets the SSI (Superset ATX) 24- +3.3V -12V pin specification, however it also PS_ON# supports a 20-pin power supply connector.

  • Page 31: Hdd Led

    Chapter 2: Installation HDD LED H DD LED Pin Definitions (JF2) The HDD LED (for IDE Hard Disk Number Definition Drives) connection is located on pins 13 and 14 of JF2. Attach the HD Active IDE hard drive LED cable to these pins to display disk activity.

  • Page 32: Reset Button

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Reset Button Reset Pin Definitions (JF 2) The Reset Button connection is lo- Number Definition cated on pins 3 and 4 of JF2. At- Reset tach it to the hardware reset Ground switch on the computer case. Refer to the table on the right for pin definitions.

  • Page 33: Extra Universal Serial Bus Headers

    Chapter 2: Installation Extra Universal Serial Bus Headers USB2 Pin Definitions (J27) Three USB headers:FPUSB0/ 1(JD2) and USB2(J27) are in- Number Definition Power cluded motherboard. FPUSB0/1 were designed to pro- Ground vide front side USB access. will need a USB cable (not in- cluded) for these headers.

  • Page 34: Fan Headers

    R eset (from MB) passed through the PWR_LED pin on JF2 to indicate of a power fail- Note: This feature is only available when using ure on the chassis. See the table redundant Supermicro power supplies. on the right for pin definitions. 2-12...

  • Page 35: Keylock

    Chapter 2: Installation Keylock The keyboard lock connection is designated on JL1. Utilizing this header allows you to inhibit any actions made on the keyboard, ef- fectively "locking" it. Wake-On-LAN The Wake-On-LAN header is des- W ake-On-LAN Pin Definitions (W OL) ignated WOL.

  • Page 36: Jumper Settings

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Jumper Settings Explanation of Jumpers Connector Pins To modify the operation of the motherboard, jumpers can be used choose between Jumper optional settings. Jumpers create shorts between two pins to change the function of the Setting connector.

  • Page 37: Gb Lan Enable/Disable

    Open Disabled Closed Enabled This feature assumes that Supermicro redundant power sup- ply units are installed in the chas- sis. If you only have a single 3rd Party PW Fail Alarm power supply installed, you should Reset Jumper Settings (JP36)

  • Page 38: Scsi Termination Enable/Disable

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual SCSI Termination Enable/ SCSI Channel T ermination Disable (X5DPL-8GM) Enable/Disable Jumper Settings (JPA1, JPA2) Jumpers JPA1 and JPA2 allow you Jumper Position Definition to enable or disable termination for Open Enabled the individual SCSI channels. Closed Disabled Jumper JPA1 controls SCSI channel A and JPA2 controls SCSI channel...

  • Page 39: Onboard Indicators

    Chapter 2: Installation Onboard Indicators Gb LAN Right LED Gb/Mb LAN LEDs Indicator Color Definition The LAN (Ethernet) ports have No Connection Green 100 MHz two LEDs. On the Gb LAN port, Orange 1 GHz the yellow (left) LED indicates ac- tivity while the other (right) LED may be green, orange or off to in- Gb LAN Left LED...

  • Page 40: Floppy Connector

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Floppy Connector The floppy connector is located on JP7. See the table below for pin definitions. Floppy Connector Pin Definitions (JP7) Pin Number Function Pin Number Function FDHDIN Reserved FDEDIN Index- M otor Enable D rive Select B- D rive Select A- M otor Enable DIR-...

  • Page 41: Ultra320 Scsi Connectors

    Chapter 2: Installation Ultra320 SCSI Connector (X5DPL-8GM) Refer to the table below for the pin definitions of the Ultra320 SCSI connectors located at JA1 and JA2. 68-pin Ultra320 SCSI C onnectors (JA1 and JA2) Connector Connector Contact Contact Number Signal Names Number Signal Names +D B(12)

  • Page 42: Installing Software Drivers

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Installing Software Drivers After all the hardware has been installed you must install the software drivers. The necessary drivers are all included on the Supermicro CD that came packaged with your motherboard. After inserting this CD into your CDROM drive, the display shown in Figure 2-5 should appear.

  • Page 43: Chapter 3: Troubleshooting

    Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.

  • Page 44: Memory Errors

    Technical Support Procedures Before contacting Technical Support, please take the following steps. Also, note that as a motherboard manufacturer, SuperMicro does not sell directly to end-users, so it is best to first check with your distributor or reseller for troubleshooting services.

  • Page 45: Frequently Asked Questions

    4. Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at support@supermicro.com or by fax at: (408) 503-8000, option 2. Frequently Asked Questions...
  • Page 46 To recover BIOS: a recovery flash requires an update key over the COM port as follows: hardwire Pin4 to Pin8, hardwire Pin9 and Pin7 to Pin6, and hardwire Pin3 to Pin2. Use the Supermicro CD to make a “Phoenix BIOS Crisis Disk for Supermicro Mainboard”. This disk includes a BIOS file named “bios.rom”.

  • Page 47: Returning Merchandise For Service

    Chapter 3: Troubleshooting Question: Why can't I turn off the power using the momentary power on/off switch? Answer: The instant power off function is controlled in BIOS by the Power Button Mode setting. When the On/Off feature is enabled, the motherboard will have instant off capabilities as long as the BIOS has control of the system.
  • Page 48 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Notes...

  • Page 49: Chapter 4: Bios

    Please refer Manual Download area Supermicro site <http://www.supermicro.com> for any changes to BIOS that may not be reflected in this manual. System BIOS ® ® The BIOS is the Basic Input Output System used in all IBM PC, XT™, AT...

  • Page 50: Running Setup

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Running Setup *Default settings are in bold text unless otherwise noted. The BIOS setup options described in this section are selected by choos- ing the appropriate text from the main BIOS Setup screen. All displayed text is described in this section, although the screen display is often all you need to understand how to set the options (see on next page).

  • Page 51: Main Setup

    Chapter 4: BIOS Main BIOS Setup Menu Phoenix BIOS Setup Utility Main Advanced Security Power Boot Exit Item Specific Help System Time [16:19:20] System Date [02/02/02] Legacy Diskette A: [1.44/1.25 MB] Legacy Diskette B: [Not Installed] ! Primary Master [120 GB] ! Primary Slave [None] ! Secondary Master...

  • Page 52: Legacy Diskette B

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Legacy Diskette B This setting allows the user to set the type of floppy disk drive installed as diskette B. The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB, 3.5 in and 2.88MB 3.5 in. ! ! ! ! ! Primary Master/Primary Slave/Secondary Master/Secondary Slave These settings allow the user to set the parameters of the IDE Primary...
  • Page 53 Chapter 4: BIOS Multi-Sector Transfers Select the number of transfer sectors. Options are 2, 4, 6, 8 and 16 Sectors. LBA Mode Control This item determines whether Phoenix BIOS will access the IDE Primary Master Device via LBA mode. The options are Enabled and Disabled. 32-bit I/O Selects 32-bit I/O operation.

  • Page 54: Advanced Setup

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual Advanced Setup Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. The items with a triangle beside them have sub menus that can be accessed by highlighting the item and pressing <Enter>.
  • Page 55 Chapter 4: BIOS ! ! ! ! ! PCI/PnP Configuration Access the submenu for this item to make changes to the PCI/PnP configuration, as listed below. Onboard LAN1 OPROM Configure Enabling this setting allows you to boot your system from LAN 1. Options are Enabled and Disabled.
  • Page 56 UPER X5DPL-8GM/X5DPL-iGM User’s Manual ! ! ! ! ! PCI Slot Configuration PCI/PCIX Frequency (Slot 4-5) This setting controls the bus speed of PCI-X slots # 4 and 5. Options are 33 MHz, 66 MHz, 100 MHz, 133 MHz and Auto. PCI/PCIX Frequency (Slot 6) This setting controls the bus speed of PCI-X slots # 4 and 5.
  • Page 57 Chapter 4: BIOS Latency Timer This setting (included in the submenu for the above six settings) sets the minimum guaranteed time allotted to the bus master in units of PCI bus clocks. Options are Default, 0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h and 00E0h. Large Disk Access Mode This setting determines how large hard drives are to be accessed.
  • Page 58 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Serial Port A This setting allows you to assign control of serial port A. The options are Enabled (user defined), Disabled, Auto (BIOS controlled) and OS Controlled. Base I/O Address Select the base I/O address for serial port A. The options are 3F8, 2F8, 3E8 and 2E8.
  • Page 59 Chapter 4: BIOS Base I/O Address Select the base I/O address for the parallel port. The options are 378, 278 and 3BC. Interrupt Select the IRQ (interrupt request) for the parallel port. Options are IRQ5 and IRQ7. Mode Specify the parallel port mode. Options are Output Only, Bi-directional, EPP and ECP.
  • Page 60 UPER X5DPL-8GM/X5DPL-iGM User’s Manual S.M.A.R.T Monitoring This setting lets you enable or disable the function of IDE Failure Prediction. The options are Enabled and Disabled. ! ! ! ! ! Advanced Processor Options Access the submenu to make changes to the following settings. CPU Speed This is a display that indicates the speed of the installed processor.
  • Page 61 Chapter 4: BIOS Event Log Capacity This is a display, not a setting, informing you of the event log capacity. View DMI Event Log Highlight this item and press <Enter> to view the contents of the event log. Event Logging This setting allows you to Enable or Disable DMI event logging.
  • Page 62 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Console Type Choose from the available options to select the console type for console redirection. The settings are VT100, VT100, 8bit, PC ANSI, 7 bit, PC ANSI, VT100+, VT-UTF8. Flow Control Choose from the available options to select the flow control for console redirection.
  • Page 63 Chapter 4: BIOS Security Choose Security from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. Security setting options are displayed by highlighting the setting using the arrow keys and pressing <Enter>. All Security BIOS settings are described in this section.
  • Page 64 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Supervisor Password Is This displays whether a supervisor password has been entered for the system. Clear means such a password has not been used and Set means a supervisor password has been entered for the system. User Password Is This displays whether a user password has been entered for the system.
  • Page 65 Chapter 4: BIOS Power Choose Power from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. Power setting options are displayed by highlighting the setting using the arrow keys and pressing <Enter>. All Power BIOS settings are described in this section.
  • Page 66 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Resume on Time Select either Off or On, which will wake the system up at the time specified in the next setting. Resume Time Use this setting to specify the time you want the system to wake up (the above setting must be set to (On).
  • Page 67 Chapter 4: BIOS +Removable Devices Highlight and press <Enter> to expand the field. See details on how to change the order and specs of removable devices in the Item Specific Help w i n d o w . CD-ROM Drive See details on how to change the order and specs of removable devices in the Item Specific Help window.
  • Page 68 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Choose PIR from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. The items with a triangle beside them have sub menus that can be accessed by highlighting the item and pressing <Enter>. PIR stands for "Processor Info ROM", which allows BIOS to read certain information from the processors.
  • Page 69 Chapter 4: BIOS ! ! ! ! ! Processor Info ROM Data Highlight this and hit <Enter> to see PIR data on the following items: Header Info Processor Data Processor Core Data Package Data Part Number Data Thermal Reference Data Feature Data Other Data OEM Data...

  • Page 70: Exit

    UPER X5DPL-8GM/X5DPL-iGM User’s Manual 3.3V Standby (V) 3.3V Vcc (V) 5V Vcc (V) 12V Vcc (V) 1.8V Vcc (V) -12V Vcc (V) Exit Choose Exit from the Phoenix BIOS Setup Utility main menu with the arrow keys. You should see the following display. All Exit BIOS settings are described in this section.
  • Page 71 Chapter 4: BIOS Exit Saving Changes Highlight this item and hit <Enter> to save any changes you made and to exit the BIOS Setup utility. Exit Discarding Changes Highlight this item and hit <Enter> to exit the BIOS Setup utility without saving any changes you may have made.
  • Page 72 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Notes 4-24...

  • Page 73: Appendix Abios Post Messages

    Appendix A: BIOS POST Messages Appendix A BIOS POST Messages During the Power-On Self-Test (POST), the BIOS will check for problems. If a problem is found, the BIOS will activate an alarm or display a message. The following is a list of such BIOS messages.
  • Page 74 UPER X5DPL-8GM/X5DPL-iGM User’s Manual System CMOS checksum bad - Default configuration used System CMOS has been corrupted or modified incorrectly, perhaps by an application program that changes data stored in CMOS. The BIOS installed Default Setup Values. If you do not want these values, enter Setup and enter your own values.
  • Page 75 Appendix A: BIOS POST Messages System cache error - Cache disabled RAM cache failed and BIOS disabled the cache. On older boards, check the cache jumpers. You may have to replace the cache. See your dealer. A disabled cache slows system performance considerably. CPU ID: CPU socket number for Multi-Processor error.
  • Page 76 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Fixed Disk n Fixed disk n (0-3) identified. Invalid System Configuration Data Problem with NVRAM (CMOS) data. I/O device IRQ conflict I/O device IRQ conflict error. PS/2 Mouse Boot Summary Screen: PS/2 Mouse installed. nnnn kB Extended RAM Passed Where nnnn is the amount of RAM in kilobytes successfully tested.
  • Page 77 Appendix A: BIOS POST Messages Parity Check 2 nnnn Parity error found in the I/O bus. BIOS attempts to locate the address and display it on the screen. If it cannot locate the address, it displays ????. Press <F1> to resume, <F2> to Setup, <F3> for previous Displayed after any recoverable error message.
  • Page 78 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Notes...

  • Page 79: Appendix Bbios Post Codes

    Appendix B: BIOS POST Codes Appendix B BIOS POST Codes This section lists the POST (Power On Self Test) codes for the PhoenixBIOS. POST codes are divided into two categories: recoverable and terminal. Recoverable POST Errors When a recoverable type of error occurs during POST, the BIOS will display an POST code that describes the problem.
  • Page 80 UPER X5DPL-8GM/X5DPL-iGM User’s Manual POST Code Description 8254 timer initialization 8237 DMA controller initialization Reset Programmable Interrupt Controller 1-3-1-1 Test DRAM refresh 1-3-1-3 Test 8742 Keyboard Controller Set ES segment register to 4 GB Auto size DRAM Initialize POST Memory Manager Clear 512 kB base RAM 1-3-4-1 RAM failure on address line xxxx* 1-3-4-3 RAM failure on data bits xxxx* of low byte of...
  • Page 81 Appendix B: BIOS POST Codes POST Code Description Test RAM between 512 and 640 kB Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers Initialize Multi Processor APIC Enable external and CPU caches Setup System Management Mode (SMM) area Display external L2 cache size Load custom defaults (optional) Display shadow-area message...
  • Page 82 UPER X5DPL-8GM/X5DPL-iGM User’s Manual POST Code Description Check for SMART Drive (optional) Shadow option ROMs Set up Power Management Initialize security engine (optional) Enable hardware interrupts Determine number of ATA and SCSI drives Set time of day Check key lock Initialize typematic rate Erase F2 prompt Scan for F2 key stroke...
  • Page 83 Appendix B: BIOS POST Codes POST Code Description Re-map I/O and memory for PCMCIA Initialize digitizer and display message Unknown interrupt The following are for boot block in Flash ROM POST Code Description Initialize the chipset Initialize the bridge Initialize the CPU Initialize system timer Initialize system I/O Check force recovery boot...
  • Page 84 UPER X5DPL-8GM/X5DPL-iGM User’s Manual Notes...

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