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® UPER SUPER X5SS8-GM SUPER X5SSE-GM SUPER X5SSE-GMII USER’S MANUAL Revision 1.0b...
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The State of California, County of Santa Clara shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product. Unless you request and receive written permission from SUPER MICRO COMPUTER, you may not copy any part of this document.
This manual is written for system integrators, PC technicians and knowledgeable PC users. It provides information for the installation and use of the SUPER X5SS8-GM/X5SSE-GM/X5SSE-GMII motherboard. The SUPER X5SS8-GM/X5SSE-GM/X5SSE-GMII supports single 604-pin Intel - 3.20 GHz processors with a 512K L2 cache at a 533/400 MHz front side bus - refer to the motherboard specifications pages on our web site (http:/ /www.supermicro.com/Product_page/product-m.htm) for updates on sup-...
Contacting Supermicro ... 1-2 Super X5SS8-GM Image ... 1-4 Super X5SSE-GM/X5SSE-GMII Image ... 1-5 Super X5SS8-GM Layout ... 1-6 Super X5SS8-GM Quick Reference ... 1-7 Super X5SSE-GM/X5SSE-GMII Layout ... 1-8 Super X5SSE-GM/X5SSE-GMII Quick Reference ... 1-9 Motherboard Features ... 1-10 ServerWorks GC-SL: Chipset System Block Diagram ...
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L2 LED ... 2-9 L1 LED ... 2-9 Overheat LED ... 2-9 Power Fail LED ... 2-9 Reset ... 2-9 PWR_ON ... 2-10 Universal Serial Bus (USB0/1) ... 2-10 Extra Universal Serial Bus Connection (USB2/3) ... 2-10 Serial Ports ... 2-11 PS/2 Keyboard and Mouse Ports ...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual 2-10 Installing Software Drivers ... 2-21 Chapter 3: Troubleshooting Troubleshooting Procedures ... 3-1 Before Power On ... 3-1 No Power ... 3-1 No Video ... 3-1 Memory Errors ... 3-2 Losing the System’s Setup Configuration ... 3-2 Technical Support Procedures ...
One (1) USB cable One (1) COM port cable One (1) I/O backpanel shield One (1) Supermicro CD or diskettes containing drivers and utilities One (1) User's/BIOS Manual One (1) fan/heatsink assembly (FAN-042CF) One (1) heatsink retention clip assembly (SKT-095E-604)
Chapter 1: Introduction Figure 1-2. SUPER X5SSE-GM/X5SSE-GMII Image * *Notes: 1. The X5SSE-GM motherboard shares the same layout but has both a Mb and a Gb Ethernet port. 2. The X5SSE-GM supports CPUs up to 3.06 MHz, and the X5SSE-GMII supports CPUs up to 3.20 MHz.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Figure 1-3. SUPER X5SS8-GM Layout Keyboard/ ATX POWER Mouse Processor Power USB0/1 COM1 JP19 Parallel Port JP11 (WOL) Mb LAN Port Gb LAN Port CHS Fan JP10 Broadcom Controller JP27 32-bit/33 MHz PCI #4 Rage XL...
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X5SS8-GM Quick Reference Jumper Description SCSI Enable/Disable JBT1 CMOS Clear JPA1/A2 SCSI Channel A/B Termination Off (Terminated) VGA Enable/Disable JP10 Mb LAN Enable/Disable JP15 Fan Status Select JP19 Watch Dog Enable/Disable JP20 Main Power Override JP22 System Bus Speed Select...
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Figure 1-4. SUPER X5SSE-GM/X5SSE-GMII Layout Keyboard/ ATX POWER Mouse Processor Power USB0/1 COM1 JP19 Parallel Port JP11 (WOL) Mb LAN Port Gb LAN Port CHS Fan JP10 Broadcom Controller JP27 32-bit/33 MHz PCI #4 Rage XL...
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X5SSE-GM/X5SSE-GMII Quick Reference* Jumper Description JBT1 CMOS Clear VGA Enable/Disable JP10* Mb LAN Enable/Disable JP15 Fan Status Select JP19 Watch Dog Enable/Disable JP20 Main Power Override JP22 System Bus Speed Select JP27* Gb LAN Enable/Disable Switch DIP Switch 1 Connector COM1/COM2 CPU/CHS/OH FAN DDR1-DDR4...
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Motherboard Features • Single 604-pin Intel GHz at a front side (system) bus speed of 533/400 MHz. Note: Please refer to the support section of our web site for a complete listing of supported processors (http://www.supermicro.com/TechSupport.htm).
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• Integrated ATI Rage XL Graphics Controller • Adaptec ZCR card support (X5SS8-GM only) • One Broadcom BCM5702 Gb fast Ethernet controller • One Intel 82551 10/100 Mb fast Ethernet controller (X5SS8-GM, X5SSE- GM/X5SSE-GMII) • 2 EIDE Ultra DMA/100 bus master interfaces •...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Floppy Parallel Port Port ATA 100 Ports CSB6 (South Ports Bridge) SMBus ATI XL Mb LAN Figure 1-5. ServerWorks Grand Champion SL Chipset: Note: This is a general block diagram. Please see the previous Motherboard Features Section for details on the features of each motherboard.
Chipset Overview The Grand Champion SL "Champion" chipset technology. the X5SS8-GM/X5SSE-GM/X5SSE-GMII is comprised of a North Bridge (CMIC- SL) and a South Bridge (CSB6). The North Bridge interfaces directly to the processors via a 533/400 MHz Host bus and integrates the functions of the main memory subsystem and the IMB bus interface unit.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual PC Health Monitoring This section describes the PC health monitoring features of the SUPER X5SS8-GM/X5SSE-GM/X5SSE-GMII. Both have an onboard System Hard- ware Monitor chip that supports PC health monitoring. Onboard Voltage Monitors for the CPU Core, Chipset Voltage, +5V, +12V, -12V, +3.3V and +2.5V...
The system BIOS is protected by hardware that prevents viruses from infecting the BIOS area. through the flash utility provided by Supermicro. This feature can prevent viruses from infecting the BIOS area and destroying valuable data. Auto-Switching Voltage Regulator for the CPU Core The auto-switching voltage regulator for the CPU core can support up to 20A current and auto-sense voltage IDs ranging from 1.4V to 3.5V.
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LAN traffic is kept to a minimum and users are not interrupted. The motherboards have a 3-pin header (WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has WOL capability.
As with all computer products, a stable power source is necessary for proper and reliable operation. It is even more important for processors that have high CPU clock rates. The SUPER X5SS8-GM/X5SSE-GM/X5SSE-GMII accommodates ATX power supplies. Although most power supplies generally meet the specifications required by the CPU, some are inadequate.
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability and a processor inter- rupt system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.
Static-Sensitive Devices Electric-Static-Discharge (ESD) can damage electronic components. To pre- vent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from ESD. Precautions • Use a grounded wrist strap designed to prevent static discharge. •...
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual PGA Processor and Heatsink Installation When handling the processor package, avoid placing direct pressure on the label area of the fan. Also, do not place the motherboard on a conductive surface, which can damage the BIOS battery and prevent the system from booting up.
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4. Secure the other retention bracket into position by repeating Step 3. 5. Lift the lever on the CPU socket: lift the the lever completely or you will damage the CPU socket when power is applied. 6. Install the CPU in the socket. Make sure that pin 1 of the CPU is seated on pin 1 of the socket (both corners are marked with a triangle).
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CPU may result. Mounting the Motherboard in the Chassis All motherboards have standard mounting holes to fit different types of chassis. Make sure the location of all the mounting holes for both the motherboard and the chassis match. Although a chassis may have both plastic and metal mounting fasteners, metal ones are highly recommended because they ground the motherboard to the chassis.
3. Gently press down on the DIMM module until it snaps into place in the slot. Repeat for more modules as desired. Support The X5SS8-GM/X5SSE-GM/X5SSE-GMII supports up to 4 GB of ECC regis- tered DDR-266/200 (PC2100/1600) SDRAM memory. You must be running 533 MHz FSB processor(s) to use DDR-266 SDRAM.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual IOPorts/Control Panel Connectors The IO ports are color coded in conformance with the PC 99 specification. See Figure 2-3 below for the colors and locations of the various IO ports. Figure 2-3. Mouse (Green) Keyboard USB Ports (Purple) Note: COM2 is a header located on the motherboard behind the VGA port.
Front Control Panel JF1 and JF2 contain header pins for various front control panel connectors. These connectors are designed for use with Supermicro server chassis. See Figure 2-4 for the pin locations of the various front control panel but- tons and LED indicators. Refer to the following section for descriptions and pin definitions.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Connecting Cables ATX Power Connection The power supply connector (at J35) meets the SSI (Superset ATX) 24-pin specification, how- ever it also supports a 20-pin power supply connector. Make sure that the orientation of the connector is correct.
L2 LED The L2 (LAN2 - Gb LAN) LED con- nection is located on pins 9 and 10 of JF1. Attach an LED cable to display network activity. the table on the right for pin defini- tions. L1 LED The L1 (LAN1 - Mb LAN) LED con- nection is located on pins 11 and 12 of JF1.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual PWR_ON The PWR_ON connection is lo- cated on pins 1 and 2 of JF1. Mo- mentarily contacting both pins will power on/off the system. button can also be configured to function as a suspend button (see the Power Button Mode setting in BIOS).
RJ45 type cables. See the next section for a description of the LEDs on the LAN ports. Note: The X5SS8-GM/X5SSE-GM/ X5SSE-GMII has one 10/100 Mb and one Gb LAN port. viewed from the rear, the Mb port is on the left (see Figure 2-3).
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual HD LED Indicator A HD LED connector is located on JF2 (see Figure 2-4). indicates activity on any hard drive (IDE, SCSI or CD-ROM). Chassis Intrusion A Chassis Intrusion header is lo- cated at JF2 and another on JP16.
External Speaker Header Connect a cable from an external speaker to the JP28 header on the motherboard if you wish to use external speakers instead of the onboard speaker. Onboard Indicators LAN Port LEDs Each of the Ethernet ports (located beside the VGA port) has a yellow and a green LED.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual DIP Switch Settings DIP Switch 1: Processor Speed The red "DIP" switch labeled SW1 has four individual switches, which are used to set the speed of the processor. The table on the right shows you the switch settings for the various speeds your processor may be able to run at.
Jumper Settings Explanation of Jumpers To modify the operation of the motherboard, jumpers can be used choose between settings. Jumpers create shorts between two pins to change the function of the connector. Pin 1 is identified with a square solder pad on the printed circuit board.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual VGA Enable/Disable JP9 allows you to enable or dis- able the VGA port. position is on pins 1 and 2 to en- able VGA. See the table on the right for jumper settings. Fan Status Select...
The default setting is pins 1-2. SCSI Termination Enable/ Disable (X5SS8-GM only) Jumpers JPA1 and JPA2 allow you to enable or disable termination for the SCSI connectors. Jumper JPA1 controls SCSI channel A and JPA2 is for SCSI channel B.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Parallel Port, Floppy/Hard Disk Drive and SCSI Connections Note the following when connecting the floppy and hard disk drive cables: • The floppy disk drive cable has seven twisted wires. • A red mark on a wire typically designates the location of pin 1.
Floppy Connector The floppy connector is located on J28. See the table below for pin definitions. IDE Connectors There are no jumpers to configure onboard IDE#1, #2 and #3 connec- tors (J39, J40 and J41, re- spectively). See the table on the right for pin defini- tions.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Ultra320 SCSI (X5SS8-GM) Connector Refer to the table below for the pin definitions of the Ultra320 SCSI connectors located at JA2 and JA3. Connector Contact Number 68-pin Ultra320 SCSI Connectors (JA2, JA3) Connector Contact Signal Names...
Chapter 2: Installation 2-10 Installing Software Drivers After all the hardware has been installed you must install the software drivers. The necessary drivers are all included on the Supermicro CD that came packaged with your motherboard. After inserting this CD into your CDROM drive, the display shown in Figure 2-5 should appear.
Troubleshooting Procedures Use the following procedures to troubleshoot your system. followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter. Note: Always disconnect the power cord before adding, changing or installing any hardware components.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual If you are a system integrator, VAR or OEM, a POST diagnos- tics card is recommended. For I/O port 80h codes, refer to Memory Errors 1. Make sure the DIMM modules are properly and fully installed.
4. Distributors: For immediate assistance, please have your account number ready when placing a call to our technical support department. We can be reached by e-mail at support@supermicro.com, by fax at (408) 503- 8019 or by phone at (408) 503-8000, option 2.
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual the BIOS image (xxxxxx.rom) files. Copy these files onto a bootable floppy and reboot your system. It is not necessary to set BIOS boot block protec- tion jumpers on the motherboard. At the DOS prompt, enter the command "flash."...
Chapter 3: Troubleshooting system is turned on), the momentary on/off switch must be held for more than four seconds to shut down the system. This feature is required to implement the ACPI features on the motherboard. Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered.
Introduction This chapter describes the AMIBIOS for the X5SS8-GM/X5SSE-GM/X5SSE- GMII. The AMI ROM BIOS is stored in a Flash EEPROM and can be easily upgraded using a floppy disk-based program. Note: Due to periodic changes to BIOS, some settings may have been added or deleted and might not yet be recorded in this manual.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual BIOS Features • Supports Plug and Play V1.0A and DMI 2.3 • Supports Intel PCI (Peripheral Component Interconnect) (PME) local bus specification 2.2 • Supports Advanced Power Management (APM) specification v 1.1 • Supports ACPI •...
The Main BIOS Setup Menu Press the <Delete> key during the POST (Power On Self Test) to enter the Main Menu of the BIOS Setup Utility. All Main Setup options are described in this section. The Main BIOS Setup screeen is displayed below. Main Advanced Chipset PCIPnP AMIBIOS Version:...
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Advanced BIOS Setup Choose Advanced BIOS Setup from the AMIBIOS Setup Utility main menu with the Left/Right arrow keys. You should see the following display. Select one of the items in the left frame of the screen, such as SuperIO Configuration, to go to the sub screen for that item.
Super IO Configuration Advanced Configure Winbond627F Serial Port(s) and Parallel P Serial Port1 Address Serial Port1 IRQ Serial Port2 Address Serial Port2 IRQ Serial Port2 Mode Parallel Port Address Parallel Port IRQ Parallel Port Mode ECP Mode DMA Channel V07.00 (C)Copyright 1985-2001, American Megatrends, Inc. The Super IO Configuration includes the following items: Serial Port 1 Address This option specifies the base I/O port address of serial port 1.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Serial Port 2 Mode Use this option to choose the Serial Port 2 Mode. The settings are Normal, Sharp-IR, SIR and consumer. Parallel Port Address This option specifies the I/O address used by the parallel port. The settings for this item include Disabled, 378, 278 and 3BC.
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Primary IDE Master When entering "Setup", BIOS automatically detects the presence of IDE devices. This displays the auto detection status of the IDE de- vices. You can also manually configure the IDE drives by providing the following information: This option allows the user to configure the IDE devices. When the desired item is highlighted (selected), press "Enter"...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual PIO Mode IDE PIO (Programmable I/O) mode programs timing cycles between the IDE drive and the programmable IDE controller. As the PIO mode in- creases, the cycle time decreases. The settings are: Auto, 0, 1, 2, 3 and 4.
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Chapter 4: BIOS Primary IDE Slave When the system enters "Setup", BIOS automatically detects the presence of IDE devices. This option displays the auto detection status of IDE de- vices. The settings for "Primary IDE Slave" are the same as those for the "Primary IDE Master".
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Floppy Configuration Floppy A Use this option to specify which of floppy drive you have installed in the A drive. The settings are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3 1/ 2", 1.44 MB 3 1/2"...
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Chapter 4: BIOS BootUp Num Lock This option is used to select the status of the Number Lock function on your keyboard on bootup. The settings are On and Off. BootUp CPU Speed This option is used set the CPU speed to either High or Low. PS/2 Mouse Support This option specifies whether a PS/2 Mouse will be supported.
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Wait for F1 if Error This settings for this option are Enabled and Disabled. Disabled: This prevents the AMIBIOS to wait on an error for user intervention. This setting should be used if there is a known reason for a BIOS error to appear. An example would be a system administrator must remote boot the system.
Chapter 4: BIOS Event Log Configuration Event Logging This option Enables or Disables the logging of events. You can use this screen to select options for the Event Log Configuration Settings. You can access sub screens to view the event log and mark all events as read. Use the up and down arrow keys to select an item, and the plus (+) and minus (-) keys to change the option setting.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Peripheral Device Configuration Power Lost Control This option determines how the system will respond when power is reap- plied after a power loss condition. start up the system when power is reapplied after an AC power loss.
Chipset Setup Choose Chipset Setup from the AMIBIOS Setup Utility main menu. The screen is shown below. All Chipset Setup options are described following the screen. Main Advanced Chipset Memory Timing Control Act to Deact Act to Read/Write RAS Precharge Time RA Cycle Time SDRAM CAS Latency RAS Time Recycle after Refresh [10 Clks]...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual RAS Cycle Time This determines the cycle time of a Row Address Strobe. The settings are 6 Clks, 7 Clks, 8 Clks and 9 Clks. SDRAM CAS Latency This sets the CAS latency for system memory. The default setting is CAS Latency 2.5.
Memory Enhance Mapping The settings for this option are Enabled and Disabled. PCI PnP Setup Choose PCI/PnP Setup from the AMIBIOS Setup main menu. All PCI/PnP options are described in this section. The PCI/PnP Setup screen is shown below. Main Advanced Chipset PCIPnP Plug &...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Allocate IRQ to PCI VGA This option lets you allocate an interrupt request (IRQ) to the PCI VGA adapter card (if used). The settings are Yes and No. PCI IDE BusMaster The settings for this option are Disabled and Enabled. Enable to specify that the IDE controller on the PCI bus has bus mastering capabilities.
Power Setup Choose Power from the AMIBIOS Setup main menu. All Power options are described in this section. Main Advanced Chipset ACPI Aware O/S Power Management Power Button Mode Suspend Timeout (Minutes) V07.00 (C)Copyright 1985-2001, American Megatrends, Inc. ACPI Aware O/S Yes allows the system to utilize Intel's ACPI specification.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Boot Setup Choose Boot Setup from the AMIBIOS Setup main menu. options are described in this section. below. Main Advanced Chipset > Boot Device Priority > Hard Disk Drives > Removable Devices > ATAPI CDROM Drives V02.03 (C)Copyright 1985-2000, American Megatrends, Inc.
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3rd Boot Device The settings for the 3rd Boot Device are Removable Device, ATAPI CDROM, Hard Drive and Intel UNDI PXE-2.0 (build 082). 4th Boot Device The settings for the 4th Boot Device are Removable Device, ATAPI CDROM, Hard Drive and Intel UNDI PXE-2.0 (build 082). Hard Disk Drives Use this screen to view the boot sequency of hard drives that have been auto-detected or entered manually on your system.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Security Setup Choose Security Setup from the AMIBIOS Setup main menu. All Security Setup options are described in this section. The Security Setup screen is shown below. Main Advanced Chipset Supervisor Password User Password > Change Supervisor Password >...
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Change Supervisor Password This option allows you to change a supervisor password that was entered previously. Change User Password This option allows you to change a user password that was entered previ- ously. Clear User Password Use this option to clear the user password so that it is not required to be entered when the system boots up.
UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual 4-10 Exit Setup Choose Exit Setup from the AMIBIOS Setup main menu. All Exit Setup op- tions are described in this section. The Exit Setup screen is shown below. Main Advanced Chipset > Exit Saving Changes >...
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Chapter 4: BIOS Load Optimal Defaults Highlighting this setting and then pressing <Enter> provides the optimum performance settings for all devices and system features. Load Failsafe Defaults Highlighting this setting and then pressing <Enter> provides the safest set of parameters for the system. Use them if the system is behaving errati- cally.
BIOS Error Beep Codes During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. The error messages normally appear on the screen.
When BIOS performs the Power On Self Test, it writes checkpoint codes to I/O port 0080h. If the computer cannot complete the boot process, diagnostic equipment can be attached to the computer to read I/O port 0080h. Uncompressed Initialization Codes The uncompressed initialization checkpoint codes are listed in order of execution: Checkpoint Code Description...
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Bootblock Recovery Codes The bootblock recovery checkpoint codes are listed in order of execution: Checkpoint Code Description The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test. Initializing the interrupt vector table next.
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initialization before the keyboard BAT command is issued. The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard controller. The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Checkpoint Code Description Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on. Any initialization before setting video mode will be done next. Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next.
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Checkpoint Code Description Patterns written in base memory. Determining the amount of memory below 1 MB next. The amount of memory below 1 MB has been found and verified. Determining the amount of memory above 1 MB memory next. The amount of memory above 1 MB has been found and verified. Checking for a soft reset and clearing the memory below 1 MB for the soft reset next.
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UPER X5SS8-GM/X5SSE-GM/X5SSE-GMII User’s Manual Checkpoint Code Description The DMA page register test passed. Performing the DMA Controller 1 base register test next. The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next. The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.
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Checkpoint Code Description Initializing the bus option ROMs from C800 next. See the last page of this chapter for additional information. Initializing before passing control to the adaptor ROM at C800. Initialization before the C800 adaptor ROM gains control has com- pleted.
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