Supermicro 7044H-82 User Manual page 96

S S
UPER ERVER 7044H-82R/7044H-X8R/7044H-82 User's Manual
POST Code
18h
1Ah
1Ch
20h
22h
24h
28h
29h
2Ah
2Ch
2Eh
2Fh
32h
33h
36h
38h
3Ah
3Ch
3Dh
41h
42h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Eh
4Fh
50h
51h
52h
54h
55h
58h
59h
5Ah
5Bh
Description
8254 timer initialization
8237 DMA controller initialization
Reset Programmable Interrupt Controller
1-3-1-1 Test DRAM refresh
1-3-1-3 Test 8742 Keyboard Controller
Set ES segment register to 4 GB
Auto size DRAM
Initialize POST Memory Manager
Clear 512 kB base RAM
1-3-4-1 RAM failure on address line xxxx*
1-3-4-3 RAM failure on data bits xxxx* of low byte of
memory bus
Enable cache before system BIOS shadow
Test CPU bus-clock frequency
Initialize Phoenix Dispatch Manager
Warm start shut down
Shadow system BIOS ROM
Auto size cache
Advanced configuration of chipset registers
Load alternate registers with CMOS values
Initialize extended memory for RomPilot
Initialize interrupt vectors
POST device initialization
2-1-2-3 Check ROM copyright notice
Initialize I20 support
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Initialize MultiBoot
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Enable USB devices
2-2-3-1 Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
A-2