Table Of Contents - Texas Instruments LMK04816 Operating Instructions Manual

Low-noise clock jitter cleaner with dual loop plls evaluation board
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L M K 0 4 8 1 6

Table of Contents

TABLE OF CONTENTS .............................................................................................................................................. 2
GENERAL DESCRIPTION .......................................................................................................................................... 4
QUICK START ......................................................................................................................................................... 5
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04816 ............................................................................. 7
.......................................................................................................................................................... 7
PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11
...................................................................................................................................................... 11
122.88 MHz VCXO PLL ........................................................................................................................................ 11
....................................................................................................................................................... 12
EVALUATION BOARD INPUTS AND OUTPUTS ....................................................................................................... 13
RECOMMENDED TEST EQUIPMENT...................................................................................................................... 21
PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 22
.................................................................................................................................................................. 22
Programming Steps ............................................................................................................................................ 22
Details ................................................................................................................................................................ 22
Programming Steps ............................................................................................................................................ 24
Details ................................................................................................................................................................ 24
APPENDIX A: CODELOADER USAGE ...................................................................................................................... 26
......................................................................................................................................................... 26
................................................................................................................................................... 27
................................................................................................................................................................... 29
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency ....................................................................... 30
................................................................................................................................................................... 31
............................................................................................................................................................ 32
............................................................................................................................................................ 37
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ................................................................................. 38
PLL1 ......................................................................................................................................................................... 38
122.88 MHz VCXO Phase Noise .......................................................................................................................... 38
Clock Output Measurement Technique .............................................................................................................. 39
Buffered Phase Noise ......................................................................................................................................... 39
) ........................................................................................................................................... 40
E V A L U A T I O N
.................................................................................................................................. 4
.................................................................................................................... 4
........................................................................................................................... 4
.............................................................................................................................. 7
............................................................................................................................................. 8
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.................................................................................................................. 9
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........................................................................................................................... 22
......................................................................................................................... 24
B O A R D
O P E R A T I N G
.................................................................................................... 6
2
I N S T R U C T I O N S
SNLU107

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