Texas Instruments LMK04906 Series User Manual
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Texas Instruments LMK04906 Series User Manual

Texas Instruments LMK04906 Series User Manual

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LMK04906 Evaluation Board
User's Guide
January 2012
Literature Number SNAU126A
Revised – December 2013

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Summary of Contents for Texas Instruments LMK04906 Series

  • Page 1 LMK04906 Evaluation Board User's Guide January 2012 Literature Number SNAU126A Revised – December 2013...
  • Page 2 LMK04906 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs Evaluation Board Instructions SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS ....................35 PLL1 ................................ 35 25 MHz VCXO Phase Noise ....................... 35 Clock Output Measurement Technique ....................36 Clock Outputs (CLKout).......................... 37 Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 4 Confirm PLL2 operation/locking ..................... 58 APPENDIX I: EVM SOFTWARE AND COMMUNICATION ......................59 OPTION 1 ..............................59 OPTION 2 ..............................59 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 5: General Description

    Table 2: LMK04906B Devices Buffered/ Programmable Reference Divided LVDS/LVPECL/ Device VCO Frequency Inputs OSCin LVCMOS Outputs Outputs LMK04906B 2370 to 2600 MHz Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 6: Quick Start

    5. Measurements may be made on an active output clock port via its SMA connector. 125 MHz (Default) Figure 1: Quick Start Diagram SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 7: Default Codeloader Modes For Evaluation Boards

    The next section outlines step-by-step procedures for using the evaluation board with the LMK04906B. For boards with another part number, make sure to select the corresponding part number under the “Device” menu. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 8: Example: Using Codeloader To Program The Lmk04906B

    In this example, the LMK04906B is chosen. Selecting the device does cause the device to be programmed. Figure 3 – Selecting the LMK04906B device SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 9: Program/Load Device

    This is important because when CodeLoader is closed, it remembers the last settings used for a particular device. Again, remember to press Ctrl+L as the first step after loading a default mode. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 10: Visual Confirmation Of Frequency Lock

    A balun may also be used. Ensure CLKoutX and CLKoutX* states are complementary to Figure 7: Setting LVCMOS modes each other. That is, Norm/Inv or Inv/Norm. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 11 See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock outputs. National’s Clock Design Tool can be used to calculate divider values to achieve desired clock output frequencies. See: http://www.ti.com/tool/clockdesigntool. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 12: Pll Loop Filters And Loop Parameters

    Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 13: Pll2 Loop Filter

    Note: PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 14: Evaluation Board Inputs And Outputs

    If an output pair is programmed to LVCMOS, each output can be independently configured (normal, inverted, or off/tri- state). SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 15 Power, these circuits directly or supply the on-board LDO VccVCO/Aux Input regulators. 0 Ω resistor options provide flexibility to route power. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 16 • MODE = (3) Dual PLL, Ext VCO (Fin), (5) Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext VCO (Fin) SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 17 SYNC, LEuWIRE_TP Status_Holdover, Status_LD, Status_CLKin0, and Status_CLKin1. These logic I/O signals also have dedicated SMAs and test points. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 18 PLL divider output signal) is selected by HOLDOVER_MUX, it is suggested to first remove the 270 ohm resistor to prevent the LED from loading the output. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 19 Status_CLKinX pin can be programmed on the Bits/Pins tab via the Status_CLKinX_MUX control. Refer to the LMK04906 Family Datasheet section “Status Pins” for more information. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 20 When SYNC_MUX is 3 to 6 (pin enabled as output), a status signal for the SYNC pin can be selected on the Bits/Pins tab via the SYNC_MUX control. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 21: Recommended Test Equipment

    50-ohm cables to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope probes. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 22: Appendix A: Codeloader Usage

    Legacy board or use with a LPT cable can be configured with the use of Appendix G: Properly Configuring LPT Port. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 23: Clock Outputs Tab

    • Digital Delay value and Half Step • Clock Divide value • Analog Delay value and Delay bypass/enable (per output) • Clock Output format (per output) Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 24 PLL(s) may be out of lock, as highlighted by the red box in Figure 10. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 25 Figure 10: Warning message indicating mismatch between Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 26: Pll1 Tab

    PLL1 PDF = CLKin Frequency / (PLL1_R * CLKinX_PreR_DIV), where CLKinX_PreR_DIV is the predivider value of the selected input clock. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 27: Setting The Pll1 Vco Frequency And Pll2 Reference Frequency

    PLL2 tab; otherwise, the one or both PLLs may be out of lock. Updating the Reference Oscillator frequency on the PLL2 tab will automatically update the value of OSCin_FREQ on the Bits/Pins tab. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 28: Pll2 Tab

    N Counter PLL2_N PLL2 N Counter value (1 to 262143). PLLN Prescaler PLL2_P PLL2 N Prescaler value (2 to 8). SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 29: Bits/Pins Tab

    Brief descriptions for the controls on this tab are provided in Table 9 to supplement the datasheet. Refer to the LMK04906 Family Datasheet more information. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 30 Sets I/O pin type on the Status_LD pin. HOLDOVER_MUX Sets the selected signal on the Status_HOLDOVER pin. HOLDOVER_TYPE Sets I/O pin type on the Status_Holdover pin. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 31 Vtune to provide for an accurate HOLDOVER mode. DAC_CLK_DIV should also be set so that DAC update rate is <= 100 kHz. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 32 PLL1_R divider to keep the device in lock. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 33 > 100 MHz. SYNC Sets these pins on the uWire header to logic high (checked) or logic low (unchecked). Program Pins Status_CLKin0 Status_CLKin1 Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 34: Registers Tab

    By clicking in the “bit field” it is possible to manually change the value of registers by typing ‘1’ and ‘0.’ SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 35: Appendix B: Typical Phase Noise Performance Plots

    This VCXO sets the reference noise to PLL2. Figure 15 shows the open loop typical phase noise performance of the Epson VG-4231CA 25.0000M- FGRC3 VCXO. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 36: Clock Output Measurement Technique

    Prodyn GXXX Balun and measuring the side single-ended using an Agilent E5052B Source Signal Analyzer. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 37: Clock Outputs (Clkout)

    RMS Jitter (fs) 146.0 147.4 149.5 12 kHz to 20 MHz RMS Jitter (fs) 166.4 160.6 159.8 1 kHz to 5 MHz Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 38: Appendix C: Schematics

    Appendix C: Schematics Power Supplies SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 39: Lmk04906B Device With Loop Filter And Crystal Circuits

    Designed for: Evaluation Customer Mod. Date: 8/1/2013 Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this Project: LMK049xx Evaluation Board specification or any information contained therein. Texas Instruments and/or its licensors do not Sheet Title:...

  • Page 40: Reference Inputs (Clkin0, Clkin1 & Clkin2), External Vcxo (Oscin) & Vco Circuits

    Designed for: Evaluation Customer Mod. Date: 8/1/2013 Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this Project: LMK049xx Evaluation Board specification or any information contained therein. Texas Instruments and/or its licensors do not Sheet Title:...

  • Page 41: Clock Outputs (Oscout0, Clkout0 To Clkout5)

    Clock Outputs (OSCout0, CLKout0 to CLKout5) Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 42: Uwire Header, Logic I/O Ports And Status Leds

    Header, Logic I/O Ports and Status LEDs SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 43: Appendix D: Bill Of Materials

    CAP, CERM, 0.47uF, 25V, +/-10%, X7R, 0603 MuRata GRM188R71E474KA12D CLKin0, CLKin0*, Connector, SMT, End launch SMA 50 Ohm Emerson Network 142-0701-851 CLKin2, CLKin2*, Power CLKout0, Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 44 CRCW060327K0JNEA R53, R55, R63, R64, R65 R69, R70, R72, RES, 240 ohm, 5%, 0.1W, 0603 Vishay-Dale CRCW0603240RJNEA R73, R89, R90 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 45 CAP, CERM, 0.47uF, 25V, +/-10%, X7R, 0603 MuRata GRM188R71E474KA12D Common Cathode Tuning Varactor Skyworks SMV1249-074LF D2, D3 LED 2.8X3.2MM 565NM RED CLR SMD Lumex SML-LX2832IC Opto/Components Inc. Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 46 LMP7731MF Semiconductor Ultra Low Noise, 150mA Linear Regulator for National LP5900SD-3.3 RF/Analog Circuits Requires No Bypass Capacitor Semiconductor Y300 DNP_XTAL SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 47: Appendix E: Pcb Layers Stackup

    4 mil Power plane #1 [LMK049xxENG.G2] 12.6 mil Ground plane [LMK049xxENG.GP1] 8 mil Power plane #2 [LMK049xxENG.G3] 12 mil Bottom Layer [LMK049xxENG.GBL] Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 48: Appendix F: Pcb Layout

    Appendix F: PCB Layout Layer #1 – Top SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 49: Layer #2 - Rf Ground Plane (Inverted)

    Layer #2 – RF Ground Plane (Inverted) Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 50: Layer #3 - Vcc Planes

    Layer #3 – Vcc Planes SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 51: Layer #4 - Ground Plane (Inverted)

    Layer #4 – Ground Plane (Inverted) Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 52: Layer # 5 - Vcc Planes 2

    Layer # 5 – Vcc Planes 2 SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 53: Layer #6 - Bottom

    Layer #6 – Bottom Revised December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 54: Layers #1 And 6 - Top And Bottom (Composite)

    Layers #1 and 6 – Top and Bottom (Composite) SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised - December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 55: Appendix G: Properly Configuring Lpt Port

    BIOS settings. The port address can be set in CodeLoader in the Port Setup tab as shown in Figure 18. Revised – December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 56: Correct Lpt Mode

    If LPT communication with the LMK04906B EVM is required, then the following configuration should be followed for proper operation. Ensure the LPT port is configured correctly as well. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised – December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 57: Appendix H: Troubleshooting Information

    Redesign PLL1 loop filter with higher charge pump current iii. Isolate VCXO tuning input from PLL1 charge pump with an op amp. Revised – December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...

  • Page 58: Confirm Pll2 Operation/Locking

    6) Confirm the LD pin output is high. 7) Program LD_MUX = “PLL1 & PLL2 DLD” 8) Confirm the LD pin output is high. SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised – December 2013 Copyright © 2013, Texas Instruments Incorporated...

  • Page 59: Appendix I: Evm Software And Communication

    OPTION 1 Open Codeloader.exe  Click “Select Device”  Click “Port Setup” tab  Click “LPT” (in Communication Mode) OPTION 2 Revised – December 2013 LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs SNAU126A Copyright © 2013, Texas Instruments Incorporated...
  • Page 60 Open Codeloader.exe  Click “Select Device”  Click “Port Setup” Tab  Click “USB” (in Communication Mode) *Remember to also make modifications in “Pin Configuration” Section according to Table above SNAU126A LMK04906 Family: Low-Noise Clock Jitter with Dual Loop PLLs Revised – December 2013 Copyright © 2013, Texas Instruments Incorporated...
  • Page 61 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.
  • Page 62 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments LMK04906BEVAL/NOPB...

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