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BIOS User's Manual
Type F DMA Buffer Control 1
Type F DMA Buffer Control 2
Instead of 8 sysclock, Type F DMA only requires 3 sysclock to
finish the data transfer.
These two options are device dependent.
The settings are Channel 0, Channel 1, Channel 2, Disabled,
Channel 3, Channel 5, Channel 6 or Channel 7.
DMA-0 Type
DMA-1 Type
DMA-2 Type
DMA-3 Type
DMA-5 Type
DMA-6 Type
DMA-7 Type
The settings for these Direct Memory Access channels are
Normal ISA, PC/PCI or Distributed.
AGP Aperture Size
This register determines the effective size of the Graphics Aper-
ture used in the particular PAC configuration.
This register can
be updated by the PAC-specific BIOS configuration sequence
before PCI standard bus enumeration sequence takes place.
If
the register is not updated, a default value selects aperture of
maximum size (i.e., 256 MB). The settings are: 4 MB, 8 MB, 16
MB, 32 MB, 64 MB, 128 MB or 256 MB.
System Type
The settings are: Auto, DP or UP.
USWC Write I/O Post
Use this feature for the WC Write Post During I/O Bridge Access
Enable (WPIO). When set to Enabled, posting of WC transactions
to PCI occur, even if the I/O bridge has been granted access to
the PCI bus via corresponding arbitration and buffer management
protocol. USWC Write posting should only be enabled if a USWC
region is located on the PCI bus. The settings are: Auto, Dis-
abled or Enabled.
MAA 1:0 Buf. Strength
MECC Buf. Strength
MD Buf. Strength
RCSA0/RCSB0 Buf. Strength
MAB 1:0 Buf. Strength
2-10
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