iWave iW-RainboW-G53M Hardware User's Manual
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iWave iW-RainboW-G53M Hardware User's Manual

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iW-G53M-Renesas RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide
iW-RainboW-G53M
RZ/G2UL or RZ/FIVE or RZ/A3UL
OSM Size-MF Hardware User Guide
REL0.1
iWave Systems Technologies Pvt. Ltd.
Page 1 of 66
DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE

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Summary of Contents for iWave iW-RainboW-G53M

  • Page 1 RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide iW-RainboW-G53M RZ/G2UL or RZ/FIVE or RZ/A3UL OSM Size-MF Hardware User Guide REL0.1 iWave Systems Technologies Pvt. Ltd. Page 1 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL0.1 iWave Systems Technologies Pvt.
  • Page 3 No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 4: Table Of Contents

    2.7.1 Programming Header ..........................52 RZ/G2UL, RZ/FIVE and RZ/A3UL Pin Multiplexing on OSM BGA ..............53 TECHNICAL SPECIFICATION.......................... 60 Electrical Characteristics ..........................60 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 4 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 5 3.2.3 RoHS Compliance ............................63 3.2.4 Electrostatic Discharge ..........................63 ORDERING INFORMATION .......................... 64 APPENDIX ..............................65 Renesas RZ/G2UL, RZ/FIVE and RZ/A3UL SBC ....................65 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 5 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 6 Table 4: RZ/G2UL, RZ/FIVE and RZ/A3UL MPU for OSM BGA interfaces ................ 53 Table 5: Power Input Requirement ..........................60 Table 6: Environmental Specification ..........................62 Table 7: Orderable Product Part Numbers ........................64 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 6 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 7: Introduction

    This document is the Hardware User Guide for the Renesas’s RZ/G2UL, RZ/FIVE and RZ/A3UL Application processor based on OSM v1.1 specification based LGA module. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the Renesas’s RZ/A3UL, G2UL and FIVE OSM Module from a Hardware Systems perspective.
  • Page 8 System on Chip System On Module Serial Peripheral Interface System on Module To Be Done UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus Voltage REL0.1 iWave Systems Technologies Pvt. Ltd. Page 8 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 9: Terminology Description

    On-OSM. References • RZ/G2UL Hardware User Manual • RZ/FIVE Hardware User Manual • RZ/A3UL Hardware User Manual • OSM Specification v1.1 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 9 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 10: Important Note

    In this signal, BCONFIG_0 is the GPIO functionality and GPIO1_05 is the GPIO number. Note: The above naming is not applicable for other signals which are not connected to MPU. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 10 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 11: Architecture And Design

    Available only when using RZ/FIVE MPU. Either SCIF3 or CAN1 can be supported as they are supported through same pins. By default, SCIF3 is supported. iWave Systems Technologies Pvt. Ltd. mktg@iwavesystems.com Figure 1: Renesas RZ/G2UL, RZ/FIVE or RZ/A3UL OSM LGA Block Diagram REL0.1...

  • Page 12: Rz/G2Ul, Rz/Five And Rz/A3Ul Som Features

    SCIF x 4(without Flow Control) Ports • Debug SCIF x 1 Port • ADC x 2 Ports • GPIOs • Boot mode • JTAG x 1 Port REL0.1 iWave Systems Technologies Pvt. Ltd. Page 12 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 13 • Form Factor : 30mm X 45mm (OSM v1.1 Specification – OSM Size-MF) Memory Size will differ based on iWave’s SOM Product Part Number. These features are supported only in RZ/G2UL and RZ/A3UL MPU and not in RZ/FIVE MPU. CAN support is only available in RZ/FIVE MPU and is multiplexed with SCIF3. By default, SCIF3 is supported.

  • Page 14: Rz/G2Ul Or Rz/Five Or Rz/A3Ul Mpu

    RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide RZ/G2UL or RZ/FIVE or RZ/A3UL MPU The iW-RainboW-G53M OSM LGA Module can support RZ/G2UL, RZ/FIVE or the RZ/A3UL MPUs from Renesas. The RZ/G2UL MPU features are given below: •...

  • Page 15: Figure 3: Rz/Five Mpu Block Diagram

    RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide Similarly, the features of the RZ/FIVE MPU with RISC-V CPU core that can be supported in the iW-RainboW-G53M OSM is given below: • RZ/FIVE : 1 x RISC-V (AX45MP Single) @1.0GHz The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) 1.0 GHz, 16-bit DDR3L/DDR4 interface.

  • Page 16: Figure 4: Rz/A3Ul Mpu Block Diagram

    RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide Similarly, the features of the RZ/A3UL MPU with RTOS support that can be supported in the iW-RainboW-G53M OSM is given below: • RZ/A3UL : 1 x Cortex-A55@1.0GHz The RZ/A3UL allows customers to achieve the full potential of a real-time operating system (RTOS) while leveraging the performance boost provided by the 64-bit Arm®...

  • Page 17: Pmic With Rtc

    RZ/G2UL, RZ/FIVE or RZ/A3UL MPUs. The RIIC0 I2C from the RZ/G2UL, RZ/FIVE or RZ/A3UL MPU is used connected to the PMIC. The I2C slave address of the PMIC is 0x58. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 17 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 18: Memory

    The eMMC flash memory (U2) is physically located on Top side of the Module. The memory size of the eMMC Flash can be customised based on the requirement by contacting iWave Support Team. REL0.1 iWave Systems Technologies Pvt. Ltd.

  • Page 19: Osm Lga/Bga Balls

    OSM LGA/BGA Balls has standard pinout as per OSM Specification v1.1. The interfaces which are available at 476 contacts are explained in the following sections. Figure 5: OSM LGA/BGA Balls Number of contacts - : 476 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 19 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 20: Table 3: Osm Pinouts

    ADC_CH1 BOOT_SEL0# AB17 CAN0_RX_1V8 AC17 CAN0_TX_1V8 AB19 CAN1_RX AC19 (Optionally CAN1_TX is connected) PMIC_PGOOD_1V8 AC18 DEBUGEN_1V8 ET0_RXC/RX_CLK ET0_RX_CTL/RX_DV ET0_RXD2 ET0_RXD3 ET0_TXC/TX_CLK ET0_TX_CTL/TX_EN ET0_RXD0 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 20 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 21 ET0_TXD0 ET0_TXD1 ET0_TXD2 ET0_TXD3 VCC_3V3 ET0_MDC ET0_MDIO FORCE_RECOV# AA14 AA17 AA19 AA22 AB15 AB21 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO7 P4_2_1V8 P15_2_1V8 P14_1_1V8 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 21 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 22 Signal AA15 RIIC1_SCL_1V8 AA16 RIIC1_SDA_1V8 AA20 RIIC0_SCL_1V8 AA21 RIIC0_SDA_1V8 JTAG_TRST# JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS MTIOC3A_1V8 MTIOC4D AA13 VRTC_3V0 SD1_CD_B(P0_2) SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 22 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 23 SD1_DATA2 SD1_DATA3 VDD_SD1 SDIO_A_PWR_EN SD1_WP(P0_3) QSPI0_IO3 QSPI0_IO2 QSPI0_CS0 QSPI0_SCLK QSPI0_IO0 QSPI0_IO1 AA23 RSPI0_SSL_1V8 RSPI0_CK_1V8 RSPI0_MISO_1V8 RSPI0_MOSI_1V8 SYS_RST#_1V8 SCIF2_RXD_1V8 SCIF2_TXD_1V8 SCIF1_RXD_1V8 SCIF1_TXD_1V8 SCIF4_RXD SCIF4_TXD REL0.1 iWave Systems Technologies Pvt. Ltd. Page 23 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 24 AB18 AA18 VDD_1V1 VCC_3V3 VCC_1V8 VCC_IN_5V nRESETREQ AUDIO_CLK1 AUDIO_CLK2 SIZE S GPIO5 GPIO6 CSI_CLK_N CSI_CLK_P CSI_DATA0_N CSI_DATA0_P CSI_DATA1_N CSI_DATA1_P CSI_DATA2_N CSI_DATA2_P CSI_DATA3_N CSI_DATA3_P REL0.1 iWave Systems Technologies Pvt. Ltd. Page 24 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 25 RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide OSM Pins Signal AB11 AB10 ET1_RXC/RX_CLK ET1_RX_CTL/RX_DV ET1_RXD2 ET1_RXD3 ET1_TXC/TX_CLK ET1_TX_CTL/TX_EN ET1_RXD0 ET1_RXD1 ET1_TXD0 ET1_TXD1 ET1_TXD2 ET1_TXD3 ET1_MDC ET1_MDIO AC10 AA11 AA10 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 25 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 26 RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide OSM Pins Signal RIIC1_SCL_1V8 RIIC1_SDA_1V8 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 26 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 27 DISP_CLK DISP_DATA18 DISP_DATA19 DISP_DATA20 DISP_DATA21 DISP_DATA22 DISP_DATA23 DISP_DE DISP_DATA10 DISP_DATA11 DISP_DATA12 DISP_DATA13 DISP_DATA14 DISP_DATA15 DISP_HSYNC DISP_DATA2 DISP_DATA3 DISP_DATA4 DISP_DATA5 DISP_DATA6 DISP_DATA7 RGB_RESET(P0_0) DISP_VSYNC REL0.1 iWave Systems Technologies Pvt. Ltd. Page 27 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 28 AA30 AA29 QSPI_RESET# PMIC_TP PMIC_SCL PMIC_SDA VCC_IN_5V VCC_IN_5V VCC_IN_5V VCC_IN_5V VDD_SD0 AA33 VDD_SD1 AB29 AB30 AC28 AC29 AB32 AB33 AC31 AC32 AB27 AC26 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 28 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 29 RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide OSM Pins Signal AB26 AB25 AC33 AC30 AC27 AB34 AB31 AB28 AA32 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 29 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 30 RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide OSM Pins Signal AA28 AA27 AA26 AA25 AA35 AA34 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 30 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 31 AC34 AB35 Note: These functions are supported only when using RZ/Five MPU. These functions are supported only when using RZ/G2UL & RZ/A3UL MPU. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 31 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 32: Rgmii Interface

    Receive data bit 2 port ETH_A_(R)(G)MII_RXD ET0_RXD3 P4_1/R1 I, 3.3V CMOS Receive data bit 3 port ETH_A_(R)(G)MII_RX_ ET0_RX_CTL/RX_ P3_1/N1 I, 3.3V CMOS Receive data valid port DV(_ER) REL0.1 iWave Systems Technologies Pvt. Ltd. Page 32 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 33 P9_3/AE20 I, 3.3V CMOS Receive data bit 2 port B ET1_RXD2 ETH_B_(R)(G)MII_RXD P10_0/AD20 I, 3.3V CMOS Receive data bit 3 port B ET1_RXD3 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 33 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 34 ET1_MDC P10_2/AC20 I/O, 3.3V Management bus data CMOS signal for Ethernet. ETH_B_MDIO ET1_MDIO P10_3/AE21 O, 3.3V CMOS Management bus clock signal for Ethernet. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 34 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 35: Sd Interface

    SD1 Write Protect. SDIO_A_WP SD1_WP(P0_3) P0_3/C3 CMOS, 10K PU O, 1.8/3.3V SDIO_A_PWR_EN CMOS, 10K PU SD1 Power Enable. P, 1.8V SDIO_A_IOPWR VDD_SD1 SD1 Voltage. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 35 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 36: Spi Interface

    Slave OUT. AA23 SPI_B_CS0# RSPI0_SSL_1V8 P18_5/A21 O, 1.8V CMOS RSPI0 Master Chip Select 0. SPI_B_SCK RSPI0_CK_1V8 P2_1/K6 O, 1.8V CMOS RSPI0 Serial Data Clock. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 36 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 37: Can Interface

    Note: CAN_B support on the OSM LGA is not available in RZ/G2UL and RZ/A3UL based OSM. CAN_B can be supported in RZ/FIVE based OSM only when SCIF3 interface is not used. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 37 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 38: Usb2.0 Otg Interface

    SoC Ball Name/ Signal Type/ OSM Pin Name Description Name Pin Number Termination AB23 USB_B_D_N USB1_DM USB1_DM/AE5 I/O, USB USB2.0 Port1 Data Negative. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 38 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 39 I OD 1.8V USB 2.0 Port1 Over CMOS/ 10K PU Current Indicator. AB20 USB_B_VBUS AC20 USB_B_EN USB1_VBUSEN_1 P18_4/B22 O, 1.8V CMOS USB Power Enable. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 39 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 40: I2C Interface

    2.2K PU AA20 I2C_B_SCL RIIC0_SCL_1V8 O, 1.8V CMOS RIIC0 Clock. RIIC0_SCL/B19 2.2K PU AA21 I2C_B_SDA RIIC0_SDA_1V8 IO, 1.8V CMOS RIIC0 Data. RIIC0_SDA/B20 2.2K PU REL0.1 iWave Systems Technologies Pvt. Ltd. Page 40 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 41: Data Uart

    OSM Pin Name Description Signal Name Pin Number Termination UART_CON_RX SCIF0_RXD_1V8 P6_3/AC1 I, 1.8V CMOS SCIF0 Receiver. UART_CON_TX SCIF0_TXD_1V8 P6_4/AC2 O, 1.8V CMOS SCIF0 Transmitter. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 41 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 42: Pwm Interface

    Pin Number Termination ADC_0 ADC_CH0 ADC_CH0/AE13 Analog ,1V8 Analog to Digital Converter 0. ADC_1 ADC_CH1 ADC_CH1/AD13 Analog ,1V8 Analog to Digital Converter 1. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 42 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 43: Jtag Interface

    JTAG test data input. JTAG_RTCK JTAG_TDO(SWO) JTAG_TDO TDO/V2 O CMOS ,1V8 JTAG test data output. JTAG_NTRST JTAG_TRST# TRST#/V1 I CMOS ,1V8 JTAG Reset. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 43 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 44: Rgb Display Interface

    DISP_HSYNC CMOS P13_0/ B11 O, 3.3V RGB_R0 DISP_DATA2 CMOS Red data bit 0 P13_4/A12 O, 3.3V RGB_R1 DISP_DATA3 CMOS Red data bit 1 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 44 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 45 Global Reset RGB_RESET# P0_0 CMOS P12_0/ C10 O, 3.3V Vertical sync RGB_VSYNC DISP_VSYNC CMOS Note: This feature is not available when using RZ/FIVE OSM. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 45 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 46: Mipi Csi Camera Interface

    IO, 1.8V MIPI CSI1 I2C Data. CSI_TX_N CMOS/ 2.2K PU I2C_CAM_SCL / RIIC1_SCL_1V8 RIIC1_SCL/A19 IO, 1.8V MIPI CSI1 I2C Clock. CSI_TX_P CMOS/ 2.2K PU REL0.1 iWave Systems Technologies Pvt. Ltd. Page 46 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 47: Osm Gpios

    CAM_PWR / GPIO5 O, 1.8V OSM General Purpose GPIO_C_6 CMOS Output C6. CAM_RST# / GPIO6 O, 1.8V OSM General Purpose GPIO_C_7 CMOS Output C7. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 47 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 48: Control Signals

    Audio interface. Vendor Defined3 AUDIO_CLK2 AUDIO_CLK2/B8 I, MIPI Audio Clock2 – reference clock to be used when using Audio interface. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 48 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 49: Boot Media Selection

    Pin Number Termination BOOT_SEL0# BOOT_SEL0# I, 1.8V CMOS Boot Media Select bit 0 10K PU FORCE_RECOVERY# FORCE_RECOV# I, 1.8V CMOS Force Recovery 10K PU REL0.1 iWave Systems Technologies Pvt. Ltd. Page 49 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 50: Power And Gnd

    B9, C11, D1, D5, D8, E2, H2, H4, L2, L4, P2, P4, R1, U2, U4, V1, W3, Y2, AA1, AA4, AA7, AA8, AA10, REL0.1 iWave Systems Technologies Pvt. Ltd. Page 50 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 51 C32, C35, D28, D34, F33, F35, G34, H32, J33, K34, M35, N34 RTC_PWR VRTC_3V0 I, 3V Power 3V coin cell input for RTC. REL0.1 iWave Systems Technologies Pvt. Ltd. Page 51 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 52: Other Features

    SCIF0_TXD P6_4/AC2 I, 1.8V CMOS Debug UART Transmitter Power Ground BOOT_SEL0# I, 1.8V CMOS Boot selection media FORCE_RECOV# I, 1.8V CMOS Force Recovery REL0.1 iWave Systems Technologies Pvt. Ltd. Page 52 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 53: Rz/G2Ul, Rz/Five And Rz/A3Ul Pin Multiplexing On Osm Bga

    MPUs pin connections to the OSM LGA and with selected pin function highlighted and available alternate functions. This table has been prepared by referring Renesas’s Pin Function Table. Important Note: It is strongly recommended to use the pin function same as selected in the OSM BGA for iWave’s BSP reusability and to have compatible OSM modules in future for upgradability.
  • Page 54 OM_SIO4 CAN1_TX SCIF0_SCK MTIC5U SCI0_RXD SCIF3_TXD CAN1_TX AB19 OM_SIO5 CAN1_RX SCIF0_CTS# MTIC5V SCI0_TXD SCIF4_SCK CAN1_RX USB 0 AC14 USB0_DP USB0_DP AB13 USB0 USB0_DM REL0.1 iWave Systems Technologies Pvt. Ltd. Page 54 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 55 OM_SIO7 CAN1_RX_ IRQ0 WDTOVF_PER SCI0_CTS#/RT SCIF4_TXD SCIF4_TXD DATARATE ROUT# SCIF3 OM_DQS CAN0_RX_ SCIF0_RXD SCIF3_RXD SCIF3_RXD DATARATE OM_SIO4 CAN1_TX SCIF0_SCK MTIC5U SCI0_RXD SCIF3_TXD SCIF3_TXD REL0.1 iWave Systems Technologies Pvt. Ltd. Page 55 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 56 ET1_TXD3 AC17 P8_4 ET1_RXC/R SCIF0_RTS# ADC_TRG RSPI2_SSL ET1_RXC/RX_ X_CLK P11_0 SSI0_BCK POE0# SCI1_RXD RSPI2_CK DISP_HSYNC DISP_HSYNC P11_1 SSI0_RCK POE4# SCI1_TXD RSPI2_MOSI DISP_DE DISP_DE REL0.1 iWave Systems Technologies Pvt. Ltd. Page 56 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 57 P15_3 RSPI0_SSL IRQ7 MTIOC8D DISP_DATA1 DISP_DATA14 P17_2 RSPI1_MIS SSI1_TXD CAN1_TX_DAT MTIOC3C DISP_DATA1 DISP_DATA18 ARATE_EN P18_3 IRQ5 RSPI0_MOSI SCI0_TXD SCIF3_TXD SCI0_CTS#/R DISP_DATA2 SCIF4_SCK DISP_DATA23 REL0.1 iWave Systems Technologies Pvt. Ltd. Page 57 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 58 IRQ4 IRQ0 SD1_CD P0_3 SD1_WP MTIOC1B RIIC2_SCL IRQ1 SD1_WP AE11 CSI_CLKN/ CSI_CLKN/NC AD11 CSI_CLKP/ CSI_CLKP/NC AE12 CSI_DATA CSI_DATA0_N 0_N/NC AD12 CSI_DATA CSI_DATA0_P/ 0_P/NC REL0.1 iWave Systems Technologies Pvt. Ltd. Page 58 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...
  • Page 59 SCIF1_RXD CAN1_RX MTIC5V SCI0_TXD DISP_DATA9 IRQ2 P14_1 P4_5 ET0_LINKS MTIOC3D CAN0_TX_D P4_5 ATARATE_E P14_2 SCIF1_SCK ADC_TRG CAN1_TX_DAT MTIC5W SCI0_SCK DISP_DATA8 IRQ3 P14_2 ARATE_EN REL0.1 iWave Systems Technologies Pvt. Ltd. Page 59 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 60: Technical Specification

    Table 5: Power Input Requirement Sl. No. Power Rail Min (V) Typical (V) Max(V) Max Input Ripple VCC_IN_5V ±50mV VDD_RTC 2.8V 3.3V ±20mV REL0.1 iWave Systems Technologies Pvt. Ltd. Page 60 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 61: Power Consumption

    RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide 3.1.2 Power Consumption REL0.1 iWave Systems Technologies Pvt. Ltd. Page 61 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

  • Page 62: Environmental Characteristics

    Note: iWave supports Heat Sink/ Heat Spreader Solution for Renesas’s RZ/G2UL, RZ/FIVE and RZ/A3UL OSM LGA Module. For more information on Heat Sink/ Heat Spreader contact iWave support team. Do not Power On the SOM without a proper thermal solution.

  • Page 63: Rohs Compliance

    3.2.4 Electrostatic Discharge iWave’s Renesas’s RZ/G2UL, RZ/FIVE and RZ/A3UL OSM LGA Module is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping.

  • Page 64: Ordering Information

    The below table provides the standard orderable part numbers for different Renesas RZ/G2UL, RZ/FIVE and RZ/A3UL OSM LGA Module variants. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size SOM configurations. Also, if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave.

  • Page 65: Appendix

    Renesas RZ/G2UL, RZ/FIVE and RZ/A3UL SBC iWave Systems supports iW-RainboW-G53S Renesas’s RZ/G2UL, RZ/FIVE and RZ/A3UL SBC which is targeted for quick prototyping and testing of the MPU features. The SBC being based on OSM they can also act as a development platform for the quick validation and testing of the OSM and its features.

  • Page 66: Iwave Systems Technologies Pvt. Ltd

    RZ/G2UL or RZ/FIVE or RZ/A3UL based OSM Hardware User Guide REL0.1 iWave Systems Technologies Pvt. Ltd. Page 66 of 66 DRAFT VERSION SUBJECT TO CHANGE WITHOUT NOTICE...

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