iWave iW-RainboW-G20M Hardware User's Manual
  1. Manuals
  2. Brands
  3. iWave Manuals
  4. Control Unit
  5. iW-RainboW-G20M
  6. Hardware user's manual

iWave iW-RainboW-G20M Hardware User's Manual

Rz/g1m, rz/g1n qseven som
Hide thumbs Also See for iW-RainboW-G20M:
Table of Contents

Advertisement

Quick Links

Download this manual
RZ/G1M/G1N Qseven SOM Hardware User Guide
iW-RainboW-G20M
RZ/G1M, RZ/G1N Qseven SOM
Hardware User Guide
REL1.3
iWave Systems Technologies Pvt. Ltd.
Page 1 of 80

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the iW-RainboW-G20M and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for iWave iW-RainboW-G20M

Summary of Contents for iWave iW-RainboW-G20M

  • Page 1 RZ/G1M/G1N Qseven SOM Hardware User Guide iW-RainboW-G20M RZ/G1M, RZ/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 1 of 80...
  • Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL1.3 iWave Systems Technologies Pvt.
  • Page 3 No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 4: Table Of Contents

    Power Control Signal ........................... 24 2.6.19 Reset Signal ..............................24 Expansion Connector1 Interfaces ........................38 2.7.1 Parallel Camera Interface..........................39 2.7.2 Parallel RGB Display Interface ........................40 2.7.3 Data UART Interface ........................... 40 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 4 of 80...
  • Page 5 Qseven SOM Mechanical Dimensions ......................75 3.3.2 Guidelines to insert the Qseven SOM into Carrier board ................77 ORDERING INFORMATION .......................... 78 APPENDIX II ..............................79 RZ/G1M/G1N Qseven SOM Development Platform ..................79 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 5 of 80...
  • Page 6 Table 14: Power Input Requirement ..........................70 Table 15: Power Sequence Timing ..........................71 Table 16: Power Consumption ............................72 Table 17: Environmental Specification ........................... 73 Table 18: Orderable Product Part Numbers ........................78 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 6 of 80...

  • Page 7: Introduction

    This document is the Hardware User Guide for the RZ/G1M, RZ/G1N Qseven System On Module based on the Renesas’s RZ/G1M or RZ/G1N Application processor. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the RZ/G1M, RZ/G1N Qseven System On Module from a Hardware Systems perspective.
  • Page 8 SDHI SD Card Host Interface Serial Sound Interface SDRAM Synchronous Dynamic Random Access Memory System On Module UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus USB OTG USB On The Go REL1.3 iWave Systems Technologies Pvt. Ltd. Page 8 of 80...

  • Page 9: Terminlogy Description

    Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SOM. References • RZ/G1M/G1N CPU Hardware User Manuals • Qseven® Specification Version 2.0 • Qseven-Spec_2.0_SGET_errata_sheet_E2.00-001 • Qseven® Design Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 9 of 80...

  • Page 10: Important Note

    If CPU pin doesn’t have multiplexing option, then the signal name is mentioned as, “Function name” Example: I2C5_SDA In this signal, functionality which we are using I2C5_SDA Note: The above naming is not applicable for other signals which are not connected to CPU. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 10 of 80...

  • Page 11: Architecture And Design

    This section provides detailed information about the RZ/G1M/G1N Qseven SOM features and Hardware architecture with high level block diagram. Also this section provides detailed information about Qseven edge connector & Expansion connector’s pin assignment and usage. RZ/G1M/G1N QsevenSOM Block Diagram iW-RainboW-G20M - RZ/G1M, RZ/G1N Qseven SOM Block Diagram PCIe x 1¹ DDR3 (32bit) SATA x 1¹...

  • Page 12: Rz/G1M/G1N Qsevensom Features

    Data UART (with CTS & RTS) x 1 Port • CAN x 1 Port • SPI x 1 Port (with 2 Chip selects) • I2C x 2 Ports • PWM x 2 Ports • 8 GPIO’s REL1.3 iWave Systems Technologies Pvt. Ltd. Page 12 of 80...
  • Page 13 In RZ/G1M/G1N CPU, MSIOF1 and HSCIF1 are multiplexed in same pins and so MSIOF1 cannot be supported when HSCIF1is supported with Hardware flow control signals. If HSCIF1is supported without Hardware flow control signals, then MSIOF1 also can be supported. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 13 of 80...

  • Page 14: Rz/G1M/G1N Cpu

    Figure 2: RZ/G1M Simplified Block Diagram Note: Please refer the latest RZ/G1M/G1N Datasheet & Reference Manual for Electrical characteristics of RZ/G1M/G1N CPU which may be revised from time to time. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 14 of 80...

  • Page 15: Memory

    SOM. The RAM size can be expandable up to maximum of 4GB. For customised DDR3L memory based SOM contact iWave support team Note: In RZ/G1N SOM, DDR3L-SDRAM is connected in 32bit x 1ch mode where it uses two 512MB DDR3L-SDRAM ICs by default.

  • Page 16: Emmc Flash

    3.3V voltage level. In SOM power off condition, this device will take power from Qseven Edge (VCC_RTC) coin cell power input (Pin 193) and continues to keep the current time. The interrupt output from RTC controller is connected to RZ/G1M/G1N GPIO”GP1_23”. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 16 of 80...

  • Page 17: Qseven Pcb Edge Connector

    Number of Pins - 230 Connector Part - Not Applicable (On Board PCB Edge connector) Mating Connector - IMSA-18010S-230A-GN1 from IRISO 88882-2D0K from Aces AS0B326-S78N-7F from FOXCONN CN113-230-0001VE from Yamaichi Electronics REL1.3 iWave Systems Technologies Pvt. Ltd. Page 17 of 80...

  • Page 18: Gigabit Ethernet

    Note: In RZ/G1N CPU, PCIe, USB3.0 & SATA High speed transceivers are multiplexed in same pins and so either one interface only can be used at a time. By default USB3.0 is supported. Please contact iWave if PCIe or SATA support is required in RZ/G1N CPU based Qseven SOM.

  • Page 19: Pcie Interface

    Note: In RZ/G1N CPU, PCIe, USB3.0 and SATA High speed transceivers are multiplexed in same pins and so either one interface only can be used at a time. By default USB3.0 is supported. Please contact iWave if PCIe or SATA support is required in RZ/G1N CPU based Qseven SOM.

  • Page 20: Usb 2.0 Otg Interface

    CPU GPIO GP2_30. If GP2_30 is set to low, then 1.8V IO level is selected for SDHI2 lines. If GP2_30 is set to high, then 3.3V IO level is selected for SDHI2 lines. For more details, refer Qseven Edge connector pins 42 to 51 on Table 4. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 20 of 80...

  • Page 21: Lvds Display Interface

    15.1 MHz at slave mode. SSI Module supports TDM format operation at 44.1 or 48-kHz sampling rate. For more details, refer Qseven Edge connector pins 59, 61, 63, 65 & 67 on Table 4. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 21 of 80...

  • Page 22: Data Uart Interface

    32bit x 64 stages for transmit FIFOs & 32bit × 256 stages for receive FIFOs and allows MSB first or LSB first selectable for data transmission and reception. For more details, refer Qseven Edge connector pins 199 to 203 on Table 4. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 22 of 80...

  • Page 23: I2C Interface

    Note: Most of the RZ/G1M/G1N CPU pins which are connected to Qseven Edge connector and Expansion connectors can be configured as GPIO with interrupt capable (if not used as other interface). REL1.3 iWave Systems Technologies Pvt. Ltd. Page 23 of 80...

  • Page 24: Manufacturing/Debug Uart Interface

    RZ/G1M/G1N CPU by connecting push button in the carrier board. For more details, refer Qseven Edge connector pins 28 on Table 4. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 24 of 80...

  • Page 25: Table 4: 230-Pin Pcb Edge Connector Pin Assignment

    7 & 8 pins through resistors and default populated. So use only in one place. GBE_ACT# GPHY_ACTIVITY O, 3.3V CMOS/ Gigabit Ethernet activity status _LED1 4.7K PU LED. GBE_CTREF REL1.3 iWave Systems Technologies Pvt. Ltd. Page 25 of 80...
  • Page 26 SATA_TXP) through 0.01uF AC Coupling Capacitors and default not populated. SATA1_TX+ SATA0_TX- Default NC. Note: TODN0_SATA & TODN1_SATA optionally connected this (for SATA_TXN) through 0.01uF AC Coupling Capacitors and default not populated. SATA1_TX- REL1.3 iWave Systems Technologies Pvt. Ltd. Page 26 of 80...
  • Page 27 GPIO for implementing SDIO LED indication. SDIO_CMD SD2_CMD(GP6_ SD2_CMD/ IO, 3.3V CMOS/ SD1 command. AH14 10K PU SDIO_WP SD2_WP(GP6_1 SD2_WP / I, 3.3V CMOS/ SD1 write Protect. AF14 10K PU REL1.3 iWave Systems Technologies Pvt. Ltd. Page 27 of 80...
  • Page 28 I2C5 data. GP1_I2C_DA AH18 1K PU HDA_BCLK/ SSI_SCK0129(GP SSI_SCK0129/ O, 3.3V CMOS SSI0/1 Audio transmit clock. I2S_CLK 2_0) SMB_ALERT# HDA_SDI/ SSI_SDATA0(GP SSI_SDATA0/ I, 3.3V CMOS SSI0 Audio receive data. I2S_SDI 2_2) REL1.3 iWave Systems Technologies Pvt. Ltd. Page 28 of 80...
  • Page 29 USB_6_7_OC USB_6_7_OC# USB1_OVC/ I, 3.3V CMOS Over current sense input for AD27 USB3.0 port. Note: This pin is connected to CPU USB1_OVC pin through resistor and default populated. USB_4_5_OC REL1.3 iWave Systems Technologies Pvt. Ltd. Page 29 of 80...
  • Page 30 AH31 Note: This pin is connected from CPU USB0_DM pin. USB_P0- USB_HUB1OUT IO, DIFF USB Host Port0 data negative. Note: This pin is connected from On-SOM USB Hub USBDM_DN1 pin. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 30 of 80...
  • Page 31 LVDS_B2- LVDS_PPEN GPIO_LVDS_PPE USB1_PWEN/ O, 3.3V CMOS Controls LVDS LCD panel power N(GP7_25) AE28 enable. Note: GP7_25 is connected to this pin as GPIO for implementing LVDS panel power enable. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 31 of 80...
  • Page 32 Note: This pin is connected to PWM3 for implementing PWM for LCD Panel backlight brightness control. GP_1- Wire_Bus GP2_I2C_DA Default NC. T/LVDS_DID_ Note: GP2_7 optionally connected this (for I2C2_SDA) through resistor and default not populated. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 32 of 80...
  • Page 33 I, 3.3V CMOS Receive input for CAN Channel0. AB29 DP_LANE3+/ TMDS_CLK+ RSVD DP_LANE3-/ TMDS_CLK- RSVD Power Ground. Power Ground. DP_LANE1+/ TMDS_LANE DP_AUX+ DP_LANE1-/ TMDS_LANE DP_AUX- Power Ground. Power Ground. DP_LANE2+/ TMDS_LANE RSVD REL1.3 iWave Systems Technologies Pvt. Ltd. Page 33 of 80...
  • Page 34 GPIO_PCIe_RST( IRQ9/ O, 3.3V CMOS PCIe reset. GP7_19) AB28 Note: GP7_19 is connected to this pin as GPIO for implementing PCIe reset. Power Ground. Power Ground. PCIE3_TX+ PCIE3_RX+ PCIE3_TX- PCIE3_RX- REL1.3 iWave Systems Technologies Pvt. Ltd. Page 34 of 80...
  • Page 35 _20) AA29 LPC_AD2 / Q7_GPIO2_(GP2 SSI_SCK78/ IO, 3.3V CMOS General purpose input/output 2. GPIO2 _21) AA27 188 LPC_AD3/ Q7_GPIO3_(GP2 SSI_WS6/ IO, 3.3V CMOS General purpose input/output 3. GPIO3 _19) AA30 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 35 of 80...
  • Page 36 SPI Serial clock (MSIOF2). 1_13) 204 MFG_NC4 Default NC. Note: Optionally CPU TRST# pin is connected to this pin through 1.8V to 3.3V level translator and default not populated. 205 VCC_5V_SB 206 VCC_5V_SB REL1.3 iWave Systems Technologies Pvt. Ltd. Page 36 of 80...
  • Page 37 VCC_5V I, 5V Power Supply Voltage. 228 VCC VCC_5V I, 5V Power Supply Voltage. 229 VCC VCC_5V I, 5V Power Supply Voltage. 230 VCC VCC_5V I, 5V Power Supply Voltage. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 37 of 80...

  • Page 38: Expansion Connector1 Interfaces

    The interfaces which are available at 80pin Expansion Connector1 are explained in following sections. Figure 6: Expansion Connector1 Number of Pins - 80 Connector Part Number - DF17(2.0)-80DP-0.5V(57) Mating Connector - DF17(3.0)-80DS-0.5V(57) from Hirose Staking Height - 5mm REL1.3 iWave Systems Technologies Pvt. Ltd. Page 38 of 80...

  • Page 39: Parallel Camera Interface

    Note: In RZ/G1M/G1N CPU, SCIF4 & VIN1 (some pins) are multiplexed in same pins and so SCIF4 cannot be supported when VI1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then SCIF4 also can be supported. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 39 of 80...

  • Page 40: Parallel Rgb Display Interface

    Note: In RZ/G1M/G1N CPU, SCIF4 & VIN1 (some pins) are multiplexed in same pins and so SCIF4 cannot be supported when VI1 is supported in 16bit mode. If VIN1 is supported in 8bit mode, then SCIF4 also can be supported. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 40 of 80...

  • Page 41: Table 6: Expansion Connector1 Pin Assignment

    Video Input Channel0 blue data bit3. VI1_DATA1(GP7_0) HCTS0#/ I, 3.3V CMOS Video Input Channel1 data bit1. VI0_B2/VI0_DATA2(GP4_7) VI0_DATA2/VI0_B2 I, 3.3V CMOS Video Input Channel0 data bit2 (or) /AB6 Video Input Channel0 blue data bit2. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 41 of 80...
  • Page 42 O, 3.3V CMOS/ Display Unit Channel1 Blue data AJ10 10K PD bit5. VI0_G3/VI2_VSYNC#(GP4_1 VI0_G3/ I, 3.3V CMOS Video Input Channel2 Vertical synchronization signal (or) Video Input Channel0 green data bit3. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 42 of 80...
  • Page 43 Display Unit Channel1 Green data 3_13) AF11 bit5 (or) Video Input Channel1 data bit7 (GroupB). VI0_R3/VI2_DATA4(GP4_24) VI0_R3/ I, 3.3V CMOS Video Input Channel2 data bit4 (or) Video Input Channel0 red data bit3. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 43 of 80...
  • Page 44 Display Unit Channel1 Red data bit0 3_0) AL12 (or) Video Input Channel1 data bit0 (GroupB). VI1_FIELD_C/VI1_G2_B(GP6 MSIOF0_TXD/ I, 3.3V CMOS Video Input Channel1 Field signal _26) (GroupC) (or) Video Input Channel1 green data bit2 (GroupB). REL1.3 iWave Systems Technologies Pvt. Ltd. Page 44 of 80...
  • Page 45 ¹ Important Note: These signals are also used for RZ/G1M/G1N CPU bootstrap setting on SOM and so no external loads or pull-up/pull-down resistors to be connected to these pins which will change the boot configuration. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 45 of 80...

  • Page 46: Figure 7: Expansion Connector2

    The interfaces which are available at 80pin Expansionconnector2 are explained in the following sections. Figure 7: Expansion Connector2 Number of Pins - 80 Connector Part Number - DF17(2.0)-80DP-0.5V(57) Mating Connector - DF17(3.0)-80DS-0.5V(57) from Hirose Staking Height - 5mm REL1.3 iWave Systems Technologies Pvt. Ltd. Page 46 of 80...
  • Page 47 Note: In RZ/G1M/G1N CPU, MSIOF1 and HSCIF1 are multiplexed in same pins and so MSIOF1 cannot be supported when HSCIF1is supported with Hardware flow control signals. If HSCIF1is supported without Hardware flow control signals, then MSIOF1 also can be supported. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 47 of 80...
  • Page 48 CLKOUT signal is 65.0 MHz. For more details, refer Expansion connector2 pins 1 to 40, 42, 44, 46, 47, 49, 51, 53, 55, 57 & 61 on Table 7. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 48 of 80...

  • Page 49: Table 7: Expansion Connecto2 Pin Assignment

    LBSC_A9 O, 3.3V CMOS Low Bus State Controller Address bit9. LBSC_D3 IO, 3.3V CMOS Low Bus State Controller Data bit3. LBSC_A0 O, 3.3V CMOS Low Bus State Controller Address bit0. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 49 of 80...
  • Page 50 O, 3.3V CMOS/ Low Bus State Controller Address 100K PU bit1. CAN_CLK(GP4_30/MDT0) SIM0_CLK/MDT0/ I, 3.3V CMOS/ CAN external clock input. 10K PD LBSC_A5 O, 3.3V CMOS Low Bus State Controller Address bit5. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 50 of 80...
  • Page 51 High Speed Serial Communication AC28 Interface (HSCIF1) Serial Data Transmitter. MSIOF1_TXD/HCTS1#(GP7 IRQ7/ O, 3.3V CMOS SPI transmit data output (or) High _17) AB26 Speed Serial Communication Interface (HSCIF1) ready to send handshake signal. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 51 of 80...
  • Page 52 AA25 (SCIF1) Serial Data Transmitter. DU0_DOTCLKIN(GP6_31) DU0_DOTCLKIN / I, 3.3V CMOS DU0 dot clock input. AG17 Note: MLBP_DAT_P is optionally connected to this pin through resistor and default not populated. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 52 of 80...
  • Page 53 ¹ Important Note: These signals are also used for RZ/G1M/G1N CPU bootstrap setting on SOM and so no external loads or pull-up/pull-down resistors to be connected to these pins which will change the boot configuration. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 53 of 80...

  • Page 54: Figure 8: Jtag Header

    The RZ/G1M/G1N Qseven SOM has PCB footprint option for some features which are not supported by default. These optional features are explained in the following sections. To add any of these optional features in RZ/G1M/G1N Qseven SOM, please contact iWave. 2.9.1 JTAG Header The RZ/G1M/G1N Qseven SOM supports one JTAG interface for CPU debug purpose.

  • Page 55: Table 8: Jtag Header Pin Assignment

    Only pull up is provided. 4,7K PU Power Ground. Default NC. Note: Optionally this pin is connected to CPU ACK pin (AE17) through resistor and default not populated. Power Ground. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 55 of 80...

  • Page 56: Figure 9: Spi Flash Programming Header

    RZ/G1M/G1N Qseven SOM Hardware User Guide 1.1.1 SPI Programming Header To program the boot code in to the SPI flash (for the first time or if boot code is corrupted), use iWave RZ/G1M/G1N SPI Programmer Board through SPI Flash Programming Header (Example part: TMM-103-01-L-D).Optionally the external SPI programmer can be used for programming the SPI flash through SPI Flash Programming Header (J1) Optionally JTAG debugger through JTAG Header (J4).

  • Page 57: Figure 10: 2Pin Power Connector

    The RZ/G1M/G1N Qseven SOM has PCB footprint option for some features which are not supported by default. These optional features are explained in the following sections. To add any of these optional features in RZ/G1M/G1N Qseven SOM, please contact iWave. 2.10.1 Power IN Connector The RZ/G1M Qseven SOM works with +5V power input from Qseven Edge connector.

  • Page 58: Table 11: Rz/G1M/G1N Cpu Iomux For Qseven Edge Connector Interfaces

    Renesas’s RZ/G1M Hardware User’s Manual. Important Note: It is strongly recommended to use the pin function same as selected in the Qseven SOM Edge connector for iWave’s BSP reusability and to have compatible Qseven modules in future for upgradability.
  • Page 59 GP2_26 GP2_26 AB29 SSI_SDATA9 RX3_D CAN0_RX_D GP2_27 GP2_27 Data UART HCTS1# SCIFB1_CTS# CAN1_TX_B GP7_8 GP7_8 HRTS1# SCIFB1_RTS# CAN1_RX_B GP7_9 GP7_9 AE30 IRQ0 SCIFB1_RXD GP7_10 GP7_10 AD29 IRQ2 SCIFB1_TXD GP7_12 GP7_12 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 59 of 80...
  • Page 60 VI1_R4_B GP2_17 GP2_17 EX_CS1# MSIOF2_SCK GP1_13 GP1_13 DREQ0 PWM3 TPU_TO3 GP1_24 GP1_24 DU1_DOTCLK AUDIO_CLKB PWM5_B SCIFA3_RXD_ GP7_20 GP7_20 IN_C Debug UART SSI_SDATA7 RX0_D GP2_23 GP2_23 AA26 SSI_WS78 TX0_D GP2_22 GP2_22 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 60 of 80...

  • Page 61: Table 12: Rz/G1M/G1N Cpu Iomux For Expansion Connector1 Interfaces

    PWM5 VI1_G6_B SCIFA3_RXD_C GP7_21 GP7_21 VI0 Input VI0_DATA7/VI0_B7 GP4_12 GP4_12 VI0_DATA6/VI0_B6 GP4_11 GP4_11 VI0_DATA5/VI0_B5 GP4_10 GP4_10 VI0_DATA4/VI0_B4 GP4_9 GP4_9 VI0_DATA3/VI0_B3 SCIF3_SCK_B SCIFA3_SCK_B GP4_8 GP4_8 VI0_DATA2/VI0_B2 GP4_7 GP4_7 VI0_DATA1/VI0_B1 GP4_6 GP4_6 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 61 of 80...
  • Page 62 VI0_G5 VI2_FIELD CAN0_TX_E HSCIF1_HTX1_D SCIFB0_TXD_D GP4_18 GP4_18 VI0_G4 VI2_CLKENB HSCIF2_HTX2 SCIFB2_TXD SCIFB0_SCK_D GP4_17 GP4_17 VI0_G3 VI2_VSYNC# I2C3_SDA_B HSCIF2_HRX2 SCIFB2_RXD ATACS01# GP4_16 GP4_16 VI0_G2 VI2_HSYNC# I2C3_SCL_B HSCIF2_HSCK2 SCIFB2_SCK ATARD1# GP4_15 GP4_15 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 62 of 80...

  • Page 63: Table 13: Rz/G1M/G1N Cpu Iomux For Expansion Connector2 Interfaces

    LBSC_A12 I2C3_SDA_D MSIOF1_SCK_D GP0_28 GP0_28 LBSC_D5 GP0_5 GP0_5 LBSC_A18 DREQ1 SCIFA1_RXD_C SCIFB1_RXD_C GP1_2 GP1_2 LBSC_D11 GP0_11 GP0_11 LBSC_A11 MSIOF1_RXD I2C3_SCL_D MSIOF1_RXD_D GP0_27 GP0_27 LBSC_D4 GP0_4 GP0_4 LBSC_A6 MSIOF1_SCK GP0_22 GP0_22 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 63 of 80...
  • Page 64 GP1_20 EX_WAIT0 HSCIF2_HRTS2#_B SCIFB0_CTS#_B GP1_23 GP1_23 CS0# ATAG0#_B I2C1_SCL GP1_10 GP1_10 EX_CS3# ATADIR0# MSIOF2_TXD ATAG0# EX_WAIT1 GP1_15 GP1_15 EX_CS5# ATACS00# MSIOF2_SS1 HSCIF1_HRX1_B CIFB1_RXD_B PWM1 TPU_TO1 GP1_17 GP1_17 EX_CS0# GP1_12 GP1_12 REL1.3 iWave Systems Technologies Pvt. Ltd. Page 64 of 80...
  • Page 65 RZ/G1M/G1N Qseven SOM Hardware User Guide 2.12 RZ/G1M CPU Reference Schematic RZ/G1M CPU and DDR3 reference schematic is provided below. Important Note: This schematic is provided only for reference without any warranty and support. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 65 of 80...
  • Page 66 RZ/G1M/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 66 of 80...
  • Page 67 RZ/G1M/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 67 of 80...
  • Page 68 RZ/G1M/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 68 of 80...
  • Page 69 RZ/G1M/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 69 of 80...

  • Page 70: Table 14: Power Input Requirement

    ² RZ/G1M/G1N Qseven SOM doesn’t support VCC_5V_SB standby voltage input from Qseven Edge Connector. RZ/G1M/G1N Qseven SOM use this voltage as backup power source to RTC controller when VCC is off. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 70 of 80...

  • Page 71: Figure 11: Qseven Som Power Sequence

    VCC rise time to PWGIN rise time ≥ 0 ms PWGIN fall time to VCC fall time ≥ 0 ms VCC fall time to VCC_RTC fall time ≥ 0 ms REL1.3 iWave Systems Technologies Pvt. Ltd. Page 71 of 80...

  • Page 72: Table 16: Power Consumption

    Deep Sleep Mode. 0.54A/1.782W RTC power when no VCC supply is provided VCC_RTC ¹ Power consumption measurements have been done in iWave’s RZ/G1M CPU based Qseven Development platform (iW-G20D-Q702-3D001G-E008G-LCG) with iWave’s Linux3.10.31 BSP (iW-PREWZ-SC-01-R5.0-REL1.0-Linux3.10.31). REL1.3 iWave Systems Technologies Pvt. Ltd.

  • Page 73: Table 17: Environmental Specification

    Heat spreader has to be used with application specific thermal solutions like heat sinks, Chassis, fans, Heat pipes etc. iWave supports Heat Spreader Solution for RZ/G1M/G1N Qseven SOM. Please refer the below figure for Heat spreader dimension details. For Heat spreader ordering information, refer section 4 ORDERING INFORMATION.

  • Page 74: Figure 12: Heat Spreader Dimensions

    3.2.4 Electrostatic Discharge iWave’s RZ/G1M/G1N Qseven SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation.

  • Page 75: Figure 13: Mechanical Dimension Of Qseven Som- Top View

    Figure 13: Mechanical dimension of Qseven SOM- Top View Note: The Qseven PCB cooling plate shown above is to be used as a cooling interface between the Qseven module and the application specific cooling solution. REL1.3 iWave Systems Technologies Pvt. Ltd. Page 75 of 80...

  • Page 76: Figure 14: Mechanical Dimension Of Rz/G1M/G1N Qseven Som- Bottom View

    Figure 15: Mechanical dimension of RZ/G1M/G1N Qseven SOM- Side View Note: If Optional features are considered in RZ/G1M/G1N Qseven SOM, top side maximum height component is SPI programming Header (3.2mm±0.15mm) followed by JTAG header (3.12mm±0.15mm). REL1.3 iWave Systems Technologies Pvt. Ltd. Page 76 of 80...

  • Page 77: Figure 16: Qseven Module Insertion Procedure

    Once the Qseven module is inserted to the MXM connector properly, press the board vertically down as shown below (in the second photo), such that the board is fixed firmly into the expansion connectors. Figure 16: Qseven Module Insertion procedure REL1.3 iWave Systems Technologies Pvt. Ltd. Page 77 of 80...

  • Page 78: Table 18: Orderable Product Part Numbers

    The below table provides the standard orderable part numbers for different RZ/G1M/G1N Qseven SOM variations. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size SOM configurations. Also if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave.

  • Page 79: Figure 17: Rz/G1M/G1N Qseven Som Development Platform With Add On Module

    5. APPENDIX II RZ/G1M/G1N Qseven SOM Development Platform iWave Systems supports iW-RainboW-G20D – RZ/G1M/G1N Qseven SOM Development Platform which is targeted for quick validation of RZ/G1M/G1N CPU based Qseven SOM and its features. Being a Nano-ITX form factor with 120mm x 120mm size, the carrier board is highly packed with all necessary interfaces &...
  • Page 80 RZ/G1M/G1N Qseven SOM Hardware User Guide REL1.3 iWave Systems Technologies Pvt. Ltd. Page 80 of 80...

Table of Contents