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Summary of Contents for iWave iW-RainboW-G27M
- Page 1 SMARC SOM Hardware User Guide iW-RainboW-G27M i.MX8 QuadMax/QuadPlus SMARC System On Module Hardware User Guide REL1.0 iWave Systems Technologies Pvt. Ltd. Page 1 of 71...
- Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL1.0 iWave Systems Technologies Pvt.
- Page 3 No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
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Page 4: Table Of Contents
2.7.16 Control Signals ............................41 2.7.17 Power and GND ............................41 Expansion Connector (Optional) ........................43 2.8.1 LVDS Interface (Optional) ..........................45 2.8.2 CAN Interface (Optional) ..........................46 2.8.3 USB3.0 Interface (Optional) ........................46 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 4 of 71... - Page 5 3.2.4 Electrostatic Discharge ..........................67 Mechanical Characteristics ..........................68 3.3.1 i.MX8 SMARC SOM Mechanical Dimensions ....................68 ORDERING INFORMATION .......................... 69 APPENDIX ..............................70 i.MX8 SMARC SOM Development Platform ....................70 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 5 of 71...
- Page 6 Table 9: Power Input Requirement ..........................63 Table 10: Power Sequence Timing ..........................64 Table 11: Power Consumption ............................64 Table 12: Environmental Specification ........................... 65 Table 13: Orderable Product Part Numbers ........................69 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 6 of 71...
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Page 7: Introduction
This document is the Hardware User Guide for the SMARC V2.1.1 SOM based on the NXP’s i.MX8 QM/QP (QuadMax/QuadPlus) Application processor. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the i.MX8 SMARC SOM from a Hardware Systems perspective. - Page 8 Smart Mobility ARChitecture System on Chip System On Module SPDIF The Sony/Philips Digital Interface Serial Peripheral Interface UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus Video Processing Unit Wi-Fi Wireless Fidelity REL1.0 iWave Systems Technologies Pvt. Ltd. Page 8 of 71...
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Page 9: Terminology Description
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SMARC SOM. References • iMX8QMAEC_ Rev. 0.pdf • iMX8QM_RM_Rev_F.pdf • SMARC Specification V2.1.1 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 9 of 71... -
Page 10: Important Note
In this signal, BCONFIG_0 is the GPIO functionality and GPIO1_05 is the GPIO number. Note: The above naming is not applicable for other signals which are not connected to CPU. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 10 of 71... -
Page 11: Architecture And Design
2. ARCHITECTURE AND DESIGN This section provides detailed information about i.MX8 SMARC SOM features and Hardware architecture with high level block diagram. i.MX8 QM/QP SMARC SOM Block Diagram iW-RainboW-G27M – i.MX8 QM/QP SMARC SOM Block Diagram Gigabit Ethernet LPDDR4 (64bit) RGMII... -
Page 12: I.mx8 Qm/Qp Smarc Som Features
MIPI CSI x 2 Channel (1x2lane and 1x4lane) • HDMI/DP Transmitter x 1 Port • LVDS/MIPI DSI x 2 Channel • SAI/I2S (Audio Interface) x 2 Port • SPI x 2 Port REL1.0 iWave Systems Technologies Pvt. Ltd. Page 12 of 71... - Page 13 RAM by using two 4GB LPDDR4 chips. If 8GB (64Gb) LPDDR4 chips are available then 16GB RAM can be supported on Board. Memory Size will differ based on iWave’s SOM Product Part Number. 16GB and 32GB eMMC are already validated on i.MX8 QM platform.
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Page 14: I.mx8 Cpu
SMARC SOM Hardware User Guide i.MX8 CPU iW-RainboW-G27M SMARC SOM can support i.MX8 CPUs from NXP. The i.MX 8 Family consists of two processors: i.MX 8QuadMax & iMX 8QuadPlus. The Major Difference between i.MX8 CPUs are: • i.MX8 QuadMax : 2 x Cortex-A72 @ 1.6 GHz, 4 x Cortex-A53 @ 1.2 GHz &... -
Page 15: Pf8100 Pmic
DDR_CH1 channels of CPU to support LPDDR4 up to 1.6 GHz. Both the LPDDR4 parts U5 and U9 are placed on Top side of the SOM. LPDDR4 memory size can be customised based on the requirement by contacting iWave support team. -
Page 16: Flexspi Flash (Optional)
1.8V Voltage levels. The Xccela™ Flash (U37) memory is physically located on Bottom side of the SMARC SOM. The FlexSPI can be supported with customised memory size based on the requirement by contacting iWave Support Team. Note: If FlexSPI Flash feature is required, contact iWave Support Team or refer Application Note: “AN2706-i.MX8 QM SMARC SOM-Enabling On SOM Octa SPI Support-Application Note-R4.0-REL1.0 .pdf”... -
Page 17: Network & Communiation
: 2042811100 from Molex / FXP830.24.0100B from Taoglas Limited Note: In default configuration 802.11ax (Wi-Fi 6) is not supported, but 802.11ax can be supported by changing Wi-Fi module from JODY-W2 to JODY-W3, contact iWave Support Team for further information. REL1.0 iWave Systems Technologies Pvt. -
Page 18: Smarc Pcb Edge Connector
SMARC PCB Edge Connector (J1) Figure 4: SMARC Edge Connector Number of Pins - : 314 Connector Part - : Not Applicable (On Board PCB Edge connector) Mating Connector - : 91782-3140M-001 from Aces REL1.0 iWave Systems Technologies Pvt. Ltd. Page 18 of 71... -
Page 19: Table 3: Smarc Edge Connector Pinouts
GBE1_LINK1000# GBE0_MDI2- GBE1_MDI2+ GBE0_MDI2+ GBE1_MDI2- GBE0_LINK_ACT# GBE0_MDI1- GBE1_MDI3+ GBE0_MDI1+ GBE1_MDI3- VPHY0_DVDDL VPHY1_DVDDL GBE0_MDI0- (Note: Optionally SERDES0_TX+) GBE0_MDI0+ (Note: Optionally SERDES0_TX-) SPI3_CS1 GBE1_LINK_ACT# (Note: Optionally SERDES0_RX+) GPIO_SDC1_WP(GPIO1_22) (Note: Optionally SERDES0_RX+) USDHC1_CMD REL1.0 iWave Systems Technologies Pvt. Ltd. Page 19 of 71... - Page 20 SPI2_SCLK QSPI1A_DATA2 (Note: Optionally QSPI1A_SCLK) SPI2_MIS0 QSPI1A_DATA3 (Note: Optionally QSPI1A_DATA0) SPI2_MOSI QSPI1A_RESET(GPIO4_22) (Note: Optionally QSPI1A_DATA1) USB_OTG1_DP USB_OTG1_DM USB_OTG1_PWR(GPIO4_03) USB3_HUB2_TXP VBUS_OTG1 USB3_HUB2_TXM USB_OTG_ID USB_HUB3OUT_DP USB3_HUB2_RXP USB_HUB3OUT_DM USB3_HUB2_RXM USB_HUB3_OC USB_HUB2OUT_DP USB_HUB1OUT_DP USB_HUB2OUT_DM REL1.0 iWave Systems Technologies Pvt. Ltd. Page 20 of 71...
- Page 21 (Note: Optionally DP0_HPD) HDMI_TX0_DATA0_P NC (Note: Optionally DP2_P) HDMI_TX0_DATA0_N S100 NC (Note: Optionally DP2_N) P100 S101 HDMI_TX0_CLK_P P101 S102 NC (Note: Optionally DP3_P) HDMI_TX0_CLK_N P102 S103 NC (Note: Optionally DP3_N) REL1.0 iWave Systems Technologies Pvt. Ltd. Page 21 of 71...
- Page 22 LVDS1/DSI0_CH0_CLK_N UART3_RX P135 S136 NC(Note: Optionally UART1_TX) P136 S137 LVDS1/DSI0_CH0_TX3_P NC(Note: Optionally UART1_RX) P137 S138 LVDS1/DSI0_CH0_TX3_N NC (Note: Optionally UART1_RTS_B) P138 S139 LVDS_I2C_SCL NC (Note: Optionally UART1_CTS_B) P139 S140 LVDS_I2C_SDA REL1.0 iWave Systems Technologies Pvt. Ltd. Page 22 of 71...
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Page 23: Gigabit Ethernet
CPU Ball Name/ Signal Type/ Description Pin No. Name Pin Number Termination GBE0_PPS_SDP IO, 3.3V CMOS Note: Optionally connected to GBE0_PPS_SDP GBE0_MDI3- IO, GBE Gigabit Ethernet MDI differential pair 3 negative. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 23 of 71... - Page 24 IO, GBE Second Gigabit Ethernet MDI differential pair 2 positive. GBE1_MDI2- IO, GBE Second Gigabit Ethernet MDI differential pair2 negative. GBE1_MDI3+ IO, GBE Second Gigabit Ethernet MDI differential pair 3 positive. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 24 of 71...
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Page 25: Serdes And Mdio Interface (Optional)
I, PCIE Note: Optionally connected to SERDES1_SI_P SERDES1_RX- I, PCIE Note: Optionally connected to SERDES1_SI_N SERDES1_TX+ O, PCIE Note: Optionally connected to SERDES1_SO_P SERDES1_TX- O, PCIE Note: Optionally connected to SERDES1_SO_N REL1.0 iWave Systems Technologies Pvt. Ltd. Page 25 of 71... -
Page 26: Sd Interface
CPU Ball Name/ Signal Type/ Description Pin No. Signal Name Pin Number Termination USB_OTG1_DP USB_OTG1_DP / IO, USB USB2.0 Port0 Data Plus. USB_OTG1_DM USB_OTG1_DM / IO, USB USB2.0 Port0 Data Minus. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 26 of 71... - Page 27 CPU Ball Name/ Signal Type/ Signal Name Description Pin No Pin Number Termination USB3_HUB3_TXP O, USB USB3.0 Hub Transmit channel 3 Plus. USB3_HUB3_TXM O, USB USB3.0 Hub Transmit channel 3 Minus. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 27 of 71...
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Page 28: Pcie Interface
PCIE_B_REFCLK_P O, PCIe PCIe Channel-B Clock Positive. Note: From External Oscillator. PCIE_B_REFCLK_N O, PCIe PCIe Channel-B Clock Negative. Note: From External Oscillator. PCIE1_B_RX0_P PCIE1_RX0_P/ I, PCIe PCIe Channel-B Receiver Positive. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 28 of 71... -
Page 29: Sata Interface
For more details on MIPI CSI0 SMARC pinouts, refer below table: SMARC SMARC Edge CPU Ball Name/ Signal Type/ Description Pin No. Signal Name Pin Number Termination MIPI_CSI0_I2C0_SCL MIPI_CSI0_I2C0 O, 1.8V CMOS/ MIPI CSI0 I2C Clock. _SCL/ 2.2K PU BH24 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 29 of 71... - Page 30 MIPI CSI1 differential clock negative. CLK_N/BH16 MIPI_CSI1_DATA0_P MIPI_CSI1_ I, MIPI MIPI CSI1 differential data lane 0 DATA0_P/BH18 positive. MIPI_CSI1_DATA0_N MIPI_CSI1_ I, MIPI MIPI CSI1 differential data lane 0 DATA0_N /BJ19 negative. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 30 of 71...
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Page 31: Hdmi/Display Port Interface
HDMI_TX0_CLK_P HDMI_TX0_CLK O, HDMI HDMI differential CLK Positive _EDP3_P/BL3 P102 HDMI_TX0_CLK_N HDMI_TX0_CLK O, HDMI HDMI differential CLK Negative _EDP3_N/BK2 P104 HDMI_TX_HPD HDMI_TX_HPD / I, 1.8V CMOS HDMI Hot Plug Detect REL1.0 iWave Systems Technologies Pvt. Ltd. Page 31 of 71... - Page 32 Note: Optionally connected to CPU ball BG3. EDP_AUX_N/BG3 Note: In default configuration HDMI is supported, contact iWave support team if eDP or DP supported SOM is required or refer Application Note: “AN2701-i.MX8 QM SMARC SOM-Enabling DP Support in SMARC Edge-Application Note- R4.0-REL1.0.pdf”...
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Page 33: Mipi Dsi/Lvds Display Interface
_P/ BN37 positive S112 MIPI_DSI1_TX0_N MIPI_DSI1_DATA0 O, MIPI MIPI DSI1 differential data Lane 0 _N/ BH32 negative Note: Optionally connected to LVDS1_CH1_TX0 LVDS1_CH1 differential data Lane 0 _N/ BL37 negative REL1.0 iWave Systems Technologies Pvt. Ltd. Page 33 of 71... - Page 34 LVDS1_CH0 differential data lane 0 _N/ BL37 negative S127 LCD0_1_EN LVDS0_I2C1_SCL/ O, 1.8V CMOS LCD0 Backlight Enable (GPIO1_08) BE37 S128 MIPI_DSI0_TX1_P MIPI_DSI0_DATA1 O, MIPI MIPI DSI0 differential data lane 1 _P /BK26 positive REL1.0 iWave Systems Technologies Pvt. Ltd. Page 34 of 71...
- Page 35 O, 1.8V CMOS LCD0 Back Light Brightness control (GPIO1_04) BE39 Note: Contact iWave support team if LVDS supported SOM is required or refer Application note: “AN2702-i.MX8 QM SMARC SOM-Enabling LVDS Support in SMARC Edge-Application Note-R4.0-REL1.0.pdf” REL1.0 iWave Systems Technologies Pvt. Ltd.
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Page 36: Audio Interface
Pin Number Termination SPI3_CS0 SPI3_CS0/BG5 O, 1.8V CMOS SPI0 Chip Select 0 SPI3_SCLK SPI3_SCLK/BF6 O, 1.8V CMOS/ SPI0 Clock 33E Series SPI3_MISO SPI3_MISO/BE5 I, 1.8V CMOS SPI0 Master IN Slave Out REL1.0 iWave Systems Technologies Pvt. Ltd. Page 36 of 71... - Page 37 SPI channels of the SMARC Edge connector with SPI2 or QSPI1A of CPU interface. But in default configuration SPI2 is connected over ESPI pins. QSPI1A maximum clock speed very from 60MHz to 200MHZ in different mode which can be supported over SPI pins by contacting iWave support team. For more details on 2...
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Page 38: Data Uart
UART1_CTS_B/ I, 1.8V CMOS AV46 Note: Optionally connect to UART1_CTS_B. P140 UART4_TX UART4_TX/ O, 1.8V CMOS Debug UART Transmitter. AU53 P141 UART4_RX UART4_RX/ I, 1.8V CMOS Debug UART Receiver. AR47 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 38 of 71... -
Page 39: Smarc Gpios
The FLEXCAN module is a full implementation of the CAN protocol specification, which supports both standard and extended message frames. 64 Message Buffers are supported by the FlexCAN module. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 39 of 71... -
Page 40: I2C Interface
BD38 2.2K PU S140 I2C_LCD_DAT LVDS_I2C_SDA/ IO, 1.8V CMOS Display Purpose I2C Clock. BD36 2.2K PU P121 PMIC_I2C_SCL/ O, 1.8V CMOS NC.Note: Optionally connected to (I2C_PM_CK) AY46 2.2K PU PMIC_I2C_SCL REL1.0 iWave Systems Technologies Pvt. Ltd. Page 40 of 71... -
Page 41: Control Signals
SMARC PCB Edge Connector to On-SOM RTC controller for real time clock. For more details on Power & GND Signals pinouts on SMARC PCB Edge connector, refer the below table. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 41 of 71... - Page 42 I, 5V Power Supply Voltage. P151,P152,P153,P154, P155,P156 P2,P9,P12,P15,P18,P32, Power Ground. P38,P47,P50,P53,P59, P68,P79,P82,P85,P88, P91,P94,P97,P100, P103,P120,P133,P142, S3,S10,S13,S16,S25,S34, S47,S61,S64,S67,S70, S73,S80,S83,S86,S89, S92,S101,S110,S119, S124,S130,S136,S143, S158 S147 VDD_RTC VDD_RTC I, 3V Power 3V coin cell input for RTC. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 42 of 71...
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Page 43: Expansion Connector (Optional)
: 100 Connector Part - : FX8C-100S-SV(68) from Hirose Mating Connector - : FX8C-100P-SV(91) from Hirose Note: In default configuration Expansion connector is optional, contact iWave Support Team for further information. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 43 of 71... -
Page 44: Table 4: Expansion Connector Pinouts
LVDS0_CH0_TX3_N LVDS0_CH1_TX1_N LVDS0_CH0_TX0_P LVDS0_CH1_TX1_P LVDS0_CH0_TX0_N LVDS0_CH1_TX0_P LVDS0_CH0_TX1_P LVDS0_CH1_TX0_N LVDS0_CH0_TX1_N LVDS0_CH1_CLK_N VHDMI_RX_5V LVDS0_CH1_CLK_P SNVS_TAMPER_IN0 SNVS_TAMPER_IN1 MLB_DATA_P SNVS_TAMPER_OUT1 MLB_DATA_N ESAI1_FST HDMI_RX0_CEC MLB_CLK_P HDMI_RX_HPD MLB_CLK_N HDMI_RX0_DDC_SDA SNVS_TAMPER_OUT0 MLB_SIG_P ESAI1_SCKR MLB_SIG_N ESAI1_FSR HDMI_RX0_DDC_SCL MIPI_CSI0_DATA2_P REL1.0 iWave Systems Technologies Pvt. Ltd. Page 44 of 71... -
Page 45: Lvds Interface (Optional)
LVDS0 Channel0 Transmit Lane 1 _N/ BL43 negative. LVDS0 Channel1 LVDS0_CH1_CLK_N LVDS0_CH1_CLK O, LVDS LVDS0 Channel1 Clock negative. _N/ BG45 LVDS0_CH1_CLK_P LVDS0_CH1_CLK O, LVDS LVDS0 Channel1 Clock positive. _P/ BH46 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 45 of 71... -
Page 46: Can Interface (Optional)
USB3_HUB3_RXP I, USB SS USB3.0 Hub Receive channel 3 Plus. USB3_HUB3_RXM I, USB SS USB3.0 Hub Receive channel 3 Minus. USB3_HUB4_TXP O, USB SS USB3.0 Hub Transmit channel 4 Plus. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 46 of 71... -
Page 47: Esai Interface (Optional)
FIFOs. The Channel Status and User Bits are also extracted from each frame and placed in the corresponding registers. The SPDIF receiver also provides a bypass option for direct transfer of the SPDIF input signal to the SPDIF transmitter. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 47 of 71... -
Page 48: Mlb Interface (Optional)
Media Local Bus Signal negative. MLB_DATA MLB_DATA/ IO, 1.8V CMOS Media Local Bus Data. MLB_CLK MLB_CLK/ O, 1.8V CMOS Media Local Bus Clock. MLB_SIG MLB_SIG/E1 O, 1.8V CMOS Media Local Bus Signal. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 48 of 71... -
Page 49: Mipi Csi0 (Optional)
HDMI RX0 differential data lane 0 A0_P/BM16 positive. HDMI_RX0_DATA1_N HDMI_RX0_DAT I, HDMI HDMI RX0 differential data lane 1 A1_N/BL17 negative. HDMI_RX0_DATA1_P HDMI_RX0_DAT I, HDMI HDMI RX0 differential data lane 1 A1_P/BM18 positive. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 49 of 71... -
Page 50: Gpio (Optional)
I, 5V CMOS HDMI RX0 I2C Clock. _SCL/BH10 2.8.9 GPIO (Optional) Refer GPIO Column under “i.MX8 Pin Multiplexing on Expansion Connector” for details on GPIO options available from Expansion connector. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 50 of 71... -
Page 51: Other Features
Compatible FAN (Example) - 109P0405J602 from Sanyo Denki America Inc. Table 5: FAN Header Pin Assignment Signal Type/ Pin No Signal Name Description Termination VCC_5V O, Power +5V Power output to FAN. Power Ground. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 51 of 71... -
Page 52: Debug Header (Optional)
Debug Header (J3) is physically located on topside of the SOM. This is the optional feature and will not be populated in default configuration. Number of Pins - 20 Connector Part - GRPB102MWCN-RC from Sullins Connector Solutions Mating Connector - LPPB102CFFN-RC from Sullins Connector Solutions Figure 7: Debug Header REL1.0 iWave Systems Technologies Pvt. Ltd. Page 52 of 71... -
Page 53: Table 6: Debug Header Pin Assignment
JTAG test data output. Power Ground. JTAG_RESETB I, 1.8V CMOS/ Reset input. 10K PU Power Ground. Only pull up is provided. Power Ground. Only pull down is provided. Power Ground. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 53 of 71... -
Page 54: I.mx8 Pin Multiplexing On Smarc Edge
This table has been prepared by referring NXP’s i.MX8 Hardware User’s Manual. Important Note: It is strongly recommended to use the pin function same as selected in the SMARC SOM Edge connector for iWave’s BSP reusability and to have compatible SMARC modules in future for upgradability. - Page 55 S122 BD34 LVDS1.GPIO0.IO00 LVDS1.PWM0.OUT LSIO.GPIO1.IO10 GPIO1_10 LVDS1.PWM0.OUT S116 BD32 LVDS1.I2C1.SCL DMA.UART3.TX LSIO.GPIO1.IO14 GPIO1_14 LSIO.GPIO1.IO14 S107 BN35 LVDS1.I2C1.SDA DMA.UART3.RX LSIO.GPIO1.IO15 GPIO1_15 LSIO.GPIO1.IO15 P102 HDMI_TX0.TX_M_LN_3 HDMI_TX0.TX_M_LN_3 HDMI P101 HDMI_TX0.TX_P_LN_3 HDMI_TX0.TX_P_LN_3 HDMI_TX0.TX_M_LN_2 HDMI_TX0.TX_M_LN_2 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 55 of 71...
- Page 56 GPIO4_24 LSIO.QSPI1A.DATA2 DMA.SPI2.SDO LSIO.GPIO3.IO08 GPIO3_08 DMA.SPI2.SDO LSIO.QSPI1A.DATA1 LSIO.GPIO4.IO25 GPIO4_25 DMA.SPI2.SDI LSIO.GPIO3.IO09 GPIO3_09 DMA.SPI2.SDI LSIO.QSPI1A.DATA0 LSIO.GPIO4.IO26 GPIO4_26 DMA.SPI3.SCK LSIO.GPIO2.IO17 GPIO2_17 DMA.SPI3.SCK DMA.SPI3.SDI DMA.FTM.CH1 LSIO.GPIO2.IO19 GPIO2_19 DMA.SPI3.SDI DMA.SPI3.SDO DMA.FTM.CH0 LSIO.GPIO2.IO18 GPIO2_18 DMA.SPI3.SDO REL1.0 iWave Systems Technologies Pvt. Ltd. Page 56 of 71...
- Page 57 DMA.SPI3.SCK LSIO.GPIO0.IO24 GPIO0_24 AM44 M40.I2C0.SCL M40.UART0.RX M40.GPIO0.IO02 LSIO.GPIO0.IO06 GPIO0_06 UART1 P137 AT44 DMA.UART1.RX DMA.SPI3.SDO LSIO.GPIO0.IO25 GPIO0_25 P138 AR43 DMA.UART1.RTS_B DMA.SPI3.SDI DMA.UART1.CTS_B LSIO.GPIO0.IO26 GPIO0_26 P139 AV46 DMA.UART1.CTS_B DMA.SPI3.CS0 DMA.UART1.RTS_B LSIO.GPIO0.IO27 GPIO0_27 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 57 of 71...
- Page 58 GPIO0_04 LSIO.GPIO0.IO04 P119 AP46 DMA.SIM0.POWER_EN LSIO.GPIO0.IO05 GPIO0_05 LSIO.GPIO0.IO05 AY52 LSIO.GPT0.CLK DMA.I2C1.SCL LSIO.KPP0.COL4 LSIO.GPIO0.IO14 GPIO0_14 DMA.I2C1.SCL AV52 LSIO.GPT0.CAPTURE DMA.I2C1.SDA LSIO.KPP0.COL5 LSIO.GPIO0.IO15 GPIO0_15 DMA.I2C1.SDA P126 AR45 M41.I2C0.SCL M41.UART0.RX M41.GPIO0.IO02 LSIO.GPIO0.IO10 GPIO0_10 LSIO.GPIO0.IO10 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 58 of 71...
- Page 59 Interface/ Default Edge Function 0 Function 1 Function 2 Function 3 GPIO Function State Pin Number Number S145 BC53 SCU.GPIO0.IOXX_PMIC_MEM SCU.GPIO0.IOXX_PMIC Control C_ON _MEMC_ON Signal S157 BC49 SCU.TCU.TEST_MODE_ SCU.TCU.TEST_MODE_SELECT SELECT REL1.0 iWave Systems Technologies Pvt. Ltd. Page 59 of 71...
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Page 60: I.mx8 Pin Multiplexing On Expansion Connector
LVDS0_CH1_TX2_P LVDS0_CH1_TX2_P BG37 LVDS0_CH1_TX3_N LVDS0_CH1_TX3_N BH38 LVDS0_CH1_TX3_P LVDS0_CH1_TX3_P BE41 SNVS_TAMPER_IN0 SNVS_TAMPER_IN0 BE43 SNVS_TAMPER_IN1 SNVS_TAMPER_IN1 TAMPER BD46 SNVS_TAMPER_OUT0 SNVS_TAMPER_OUT0 BD42 SNVS_TAMPER_OUT1 SNVS_TAMPER_OUT1 FLEXCAN2_RX LSIO.GPIO4.IO01 GPIO4_01 FLEXCAN2_RX CAN2 FLEXCAN2_TX LSIO.GPIO4.IO02 GPIO4_02 FLEXCAN2_TX REL1.0 iWave Systems Technologies Pvt. Ltd. Page 60 of 71... - Page 61 LSIO.GPIO2.IO15 GPIO2_15 AUD.SPDIF0.TX SPDIF AY50 LSIO.GPT1.CAPTURE DMA.I2C2.SDA LSIO.KPP0.ROW4 LSIO.GPIO0.IO18 AUD.SPDIF0.EXT_CLK DMA.DMA0.REQ_IN0 LSIO.GPIO2.IO16 GPIO2_16 AUD.SPDIF0.EXT_CLK BA53 LSIO.GPT1.CLK DMA.I2C2.SCL LSIO.KPP0.COL7 LSIO.GPIO0.IO17 BE25 MIPI_CSI0.DN2 MIPI_CSI0.DN2 MIPI CSI0 BF24 MIPI_CSI0.DP2 MIPI_CSI0.DP2 BE17 MIPI_CSI0.DN3 MIPI_CSI0.DN3 REL1.0 iWave Systems Technologies Pvt. Ltd. Page 61 of 71...
- Page 62 BF16 MIPI_CSI0.DP3 MIPI_CSI0.DP3 CONN.MLB.PADP_CLK CONN.MLB.PADP_CLK CONN.MLB.PADN_CLK CONN.MLB.PADN_CLK CONN.MLB.PADP_S CONN.MLB.PADP_S CONN.MLB.PADN_S CONN.MLB.PADN_S CONN.MLB.PADP_D CONN.MLB.PADP_D CONN.MLB.PADN_D CONN.MLB.PADN_D CONN.MLB.SIG AUD.SAI3.RXD LSIO.GPIO3.IO26 GPIO3_28 CONN.MLB.SIG CONN.MLB.CLK AUD.SAI3.RXD LSIO.GPIO3.IO27 GPIO3_28 CONN.MLB.CLK CONN.MLB.DATA AUD.SAI3.RXD LSIO.GPIO3.IO28 GPIO3_28 CONN.MLB.DATA REL1.0 iWave Systems Technologies Pvt. Ltd. Page 62 of 71...
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Page 63: Technical Specification
¹ VDD_IN can be set as low as 3.0V with sufficient current but without a FAN. As per specification FAN need minimum of 4.5V. 3.1.1 Power Input Sequencing The i.MX8 SMARC SOM’s Power Input sequence requirement is explained below. Figure 8: Power Input Sequencing REL1.0 iWave Systems Technologies Pvt. Ltd. Page 63 of 71... -
Page 64: Power Consumption
0.67A/3.35W RTC power when no VIN_3V3 supply is provided VRTC_3V0 5.1µA/15.3µW ¹ Power consumption measurements are done in iWave ’s i.MX8 QM CPU based SMARC Development platform with iWave ‘s iW-PRFHZ-SC-01-R4.0-REL0.1-Linux5.4.24. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 64 of 71... -
Page 65: Environmental Characteristics
Heat spreader has to be used with application specific thermal solutions like heat sinks, Chassis, fans, Heat pipes etc. Note: iWave supports Heat Sink/ Heat Spreader Solution for i.MX8 SMARC SOM SOM. For more information on Heat Sink/ Heat Spreader contact iWave support team. Do not Power On the SOM without a proper thermal solution. -
Page 66: Figure 9: Mechanical Dimension Of Heat Sink
SMARC SOM Hardware User Guide Figure 9: Mechanical dimension of Heat Sink Figure 10: Mechanical dimension of Heat Spreader REL1.0 iWave Systems Technologies Pvt. Ltd. Page 66 of 71... -
Page 67: Rohs Compliance
3.2.4 Electrostatic Discharge iWave’s i.MX8 SMARC SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation. -
Page 68: Mechanical Characteristics
(3.95mm) followed by Bulk Capacitors (1.35mm). Please refer the below figure which gives height details of the i.MX8 SMARC SOM. Please refer the above figure for the details of the Expansion connector location on i.MX8 SMARC SOM. REL1.0 iWave Systems Technologies Pvt. Ltd. Page 68 of 71... -
Page 69: Ordering Information
The below table provides the standard orderable part numbers for different i.MX8 SMARC SOM variations. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size SOM configurations. Also, if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave. -
Page 70: Appendix
5. APPENDIX i.MX8 SMARC SOM Development Platform iWave Systems supports iW-RainboW-G27D-i.MX8 SMARC SOM Development Platform which is targeted for quick validation of i.MX8 CPU based SMARC SOM and its features. Being a Nano-ITX form factor with 120mm x 120mm size, the carrier board is highly packed with all necessary interfaces &... - Page 71 SMARC SOM Hardware User Guide REL1.0 iWave Systems Technologies Pvt. Ltd. Page 71 of 71...
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