iWave iW-RainboW-G17M Hardware User's Manual
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iWave iW-RainboW-G17M Hardware User's Manual

Cyclone v soc qseven som
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Cyclone V SoC Qseven SOM Hardware User Guide
iW-RainboW-G17M
Cyclone V SoC Qseven SOM
Hardware User Guide
REL 1.0
iWave Systems Technologies Pvt. Ltd.
Page 1 of 53

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Summary of Contents for iWave iW-RainboW-G17M

  • Page 1 Cyclone V SoC Qseven SOM Hardware User Guide iW-RainboW-G17M Cyclone V SoC Qseven SOM Hardware User Guide REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 1 of 53...
  • Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL 1.0 iWave Systems Technologies Pvt.
  • Page 3 (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 4: Table Of Contents

    Electrical Characteristics ..........................43 3.1.1 Power Input Requirement ........................... 43 3.1.2 Power Input Sequencing ..........................43 3.1.3 Power Consumption ............................ 44 Environmental Characteristics ........................45 3.2.1 Environmental Specification ........................45 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 4 of 53...
  • Page 5 ORDERING INFORMATION .......................... 50 APPENDIX I ..............................51 Cyclone V SoC Qseven SOM Silk Screen ......................51 APPENDIX II ..............................53 Cyclone V SoC Qseven SOM Development Platform ..................53 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 5 of 53...
  • Page 6 Table 11: Power Input Requirement ..........................43 Table 12: Power Sequence Timing ..........................44 Table 13: Power Consumption ............................44 Table 14: Environmental Specification ........................... 45 Table 15: Orderable Product Part Numbers ........................50 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 6 of 53...

  • Page 7: Introduction

    This document is the Hardware User Guide for the Cyclone V SoC Qseven System On Module based on the Altera’s Cyclone V SoC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design, technical specification and usage of the Cyclone V SoC Qseven System On Module from a Hardware Systems perspective.
  • Page 8 Synchronous Dynamic Random Access Memory SMBUS System Management Bus System on Chip System On Module Serial Peripheral Interface Synchronous Serial Interface UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus WDOG Watch Dog REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 8 of 53...

  • Page 9: Terminlogy Description

    Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SOM. References  Cyclone V Device Handbook  Cyclone V Device Overview  Qseven Specification Revision 2.0 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 9 of 53...

  • Page 10: Important Note

    In this signal, AH23 is the Cyclone V SoC Pin number and LVDS_A0P is the functionality which we are using with this FPGA pin. Note: The above naming is not applicable for other signals which are not connected to Cyclone V SoC. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 10 of 53...

  • Page 11: Architecture And Design

    Also this section provides detailed information about Qseven edge connector & Expansion connector pin assignment and usage. Cyclone V SoC Qseven SOM Block Diagram iW-RainboW-G17M-Cyclone V SoC Qseven SOM Block Diagram Power Power IN...

  • Page 12: Cyclone V Soc Qseven Som Features

    Debug UART  Data UART x 1 Port  CAN x 1 Port  I2C x 2 Ports  SPI x 1 Port (with 2 Chip selects )  WDOG REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 12 of 53...
  • Page 13 Note: If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement, same interface pins can be used for custom Industrial/Networking interface requirements. Note: iWave supports different Soft IPs for Cyclone V FPGA. Please contact iWave for more details. REL 1.0 iWave Systems Technologies Pvt.

  • Page 14: Cyclone V Soc

    Note: Please refer the latest Cyclone V SoC Datasheet & Handbook from Altera website for Electrical characteristics of Cyclone V SoC which may be revised from time to time. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 14 of 53...

  • Page 15: Boot Switches

    Cyclone V SoC Qseven SOM supports below mentioned switches for boot purposes which are explained in following section.  Boot Media Switch  Boot Clock Switch (Optional)  Reset Switch Figure 3: Boot Switches REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 15 of 53...

  • Page 16: Boot Media Switch

    Cyclone V SoC Qseven SOM supports On-SOM reset switch (SW1). This momentary push-button switch can be used to reset the Cyclone V SoC. This reset is connected to Cyclone V HPS’s HPS_NPOR pin and Cyclone V FPGA IO pin (SoC Pin number D12). REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 16 of 53...

  • Page 17: Memory

    This Flash is connected to the FPGA Block of the Cyclone V SoC and operating under 3.3V Voltage level. This is the optional feature and will not be populated in default configuration. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 17 of 53...

  • Page 18: Other Features

    JTAG connector is physically located on top of the SOM. Figure 4: HPS JTAG Connector Number of Pins - 20 Connector Part - GRPB102MWCN-RC from Sullins Connector Solutions Mating Connector - LPPB102CFFN-RC from Sullins Connector Solutions REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 18 of 53...

  • Page 19: Table 4: Hps Jtag Header Pin Assignment

    JTAG test Clock. 1K PD Power Ground. Power Ground. HPS_TDO O, 3.3V CMOS JTAG test data output. Power Ground. RSTBTN I, 3.3V CMOS Reset Signal. Power Ground. Power Ground. Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 19 of 53...

  • Page 20: Fpga Jtag Header

    JTAG test data output. VCC_3V3 O, 3.3V Power Supply Voltage. FPGA_JTAG_TMS I, 3.3V CMOS/ JTAG test mode select. 10K PU FPGA_JTAG_TDI I, 3.3V CMOS/ JTAG test data input. 10K PU Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 20 of 53...

  • Page 21: Fpga As Header (Optional)

    O, 3.3V CMOS Serial data output from configuration flash. FPGA_CSOn I, 3.3V CMOS Chip select input to configuration flash. FPGA_AS_DATA0 I, 3.3V CMOS Serial data input to configuration flash. Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 21 of 53...

  • Page 22: Power In Connector (Optional)

    0050375023 Mating connector SHROUD for P1 CONN FEMALE 22-28AWG 0008701039 Mating connector 2.5MM TIN crimp pin Note: For Cyclone V SoC Qseven SOM Silkscreen identifier details, refer APPENDIX I. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 22 of 53...

  • Page 23: Qseven Pcb Edge Connector

    Figure 8: Qseven PCB Edge Connector Number of Pins - 230 Connector Part - Not Applicable (On Board PCB Edge connector) Mating Connector - AS0B326-S78N-7F from FOXCONN or 88882-2D0K from Aces REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 23 of 53...

  • Page 24: Qseven Interfaces From Hps

    Qseven Edge connector has one SPI interface with two chip selects. This is supported using Cyclone V HPS SPIM0 interface.  WDOG interface Qseven Edge connector has Watchdog trigger input and event indicator output. This is supported through Cyclone V HPS GPIOs. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 24 of 53...

  • Page 25: Qseven Interfaces From Fpga High Speed Transceiver

    Qseven Edge connector supports 8 SE IOs which is connected to 3.3V FPGA Bank IOs of Cyclone V SoC. This can be used as GPIOs or LPC interface. Note: iWave supports different Soft IPs for Cyclone V FPGA. Please contact iWave for more details. REL 1.0 iWave Systems Technologies Pvt.

  • Page 26: Table 9: 230-Pin Pcb Edge Connector Pin Assignment

    Note: This Pin is connected to Cyclone V HPS_GPIO62 for GPIO purpose. Since same signal is also used internally in SOM to select HPS boot clock, it is recommended not to drive externally. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 26 of 53...
  • Page 27 SATA_ACT# FPGA_Y5_SATA FPGA IO/ O, 3.3V OC SATA command activity line. _ACTn Power Ground. SATA0_RX+ FPGA_F2_SATA GXB_RX_L5P/ I, DIFF/ SATA0 receive input differential 0_RXP 0.1uf AC coupled positive. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 27 of 53...
  • Page 28 SD/MMC card data line 4. SDIO_DAT7 HPS_SDMMC_D SDMMC_D7/ IO, 3.3V CMOS SD/MMC card data line 7. SDIO_DAT6 HPS_SDMMC_D SDMMC_D6/ IO, 3.3V CMOS SD/MMC card data line 6. RSVD1 Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 28 of 53...
  • Page 29 HPS GPIO50. THRMTRIP# WDOUT HPS_GPIO49(TR TRACE_D0/ O, 3.3V CMOS Watchdog event indicator Output. ACE_D0) This is connected to HPS GPIO49. Power Ground. Power Ground. USB_P7-/ USB_SSTX0- USB_P6-/ USB_SSRX0- REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 29 of 53...
  • Page 30 O, 2.5V LVDS LVDS primary channel differential LVDS_A0+ DS_A0P AH23 pair0 positive. 100 eDP1_TX0+/ FPGA_AA19_LV FPGA IO/ O, 2.5V LVDS LVDS secondary channel LVDS_B0+ DS_B0P AA19 differential pair0 positive. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 30 of 53...
  • Page 31 O, 2.5V LVDS LVDS secondary channel LVDS_B_CLK + DS_BCLKP AG23 differential clock Positive. 121 eDP0_AUX-/ FPGA_AH13_LV FPGA IO/ O, 2.5V LVDS LVDS primary channel differential LVDS_A_CLK- DS_ACLKN AH13 clock negative. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 31 of 53...
  • Page 32 I, 3.3V CMOS CAN Receive line. RACE_D4) 131 DP_LANE3+/ TMDS_CLK+ 132 RSVD 133 DP_LANE3-/ TMDS_CLK- 134 RSVD 135 GND Power Ground. 136 GND Power Ground. 137 DP_LANE1+/ TMDS_LANE 138 DP_AUX+ REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 32 of 53...
  • Page 33 157 PCIE_CLK_RE PCIe_CLK_REFN O, DIFF PCIe differential reference clock negative. 158 PCIE_RST# FPGA_AC4_PCIe FPGA IO/ O, 3.3V CMOS PCIe Reset signal. _RSTn 159 GND Power Ground. 160 GND Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 33 of 53...
  • Page 34 PCI Express channel 0 transmit 0_TXN 0.1uf AC coupled output differential pair negative. 182 PCIE0_RX- FPGA_AF1_PCIe GXB_RX_L0N/ I, DIFF PCI Express channel 0 receive input 0_RXN differential pair negative. 183 GND Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 34 of 53...
  • Page 35 SPI chip select 0. 4.7K PU 201 SPI_MISO HPS_SPIM0_MI SPIM0_MISO/ I, 3.3V CMOS SPI Master In Slave Out. 202 SPI_CS1# HPS_SPIM0_SS1 UART0_RX/ O, 3.3V CMOS SPI chip select 1. (UART0_RX) REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 35 of 53...
  • Page 36 Input Supply Voltage. 228 VCC VCC_5V I, 5V Power Input Supply Voltage. 229 VCC VCC_5V I, 5V Power Input Supply Voltage. 230 VCC VCC_5V I, 5V Power Input Supply Voltage. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 36 of 53...

  • Page 37: Expansion Connector

    Cyclone V SoC Qseven SOM design to provide maximum interfaces of Cyclone V SoC to the carrier board by adding an Expansion connector. Figure 9: Expansion Connector Number of Pins - 80 Connector Part Number - DF17(2.0)-80DP-0.5V(57) Mating Connector - DF17(3.0)-80DS-0.5V(57) from Hirose Staking Height - 5mm REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 37 of 53...

  • Page 38: Expansion Connector Interfaces From Fpga

     FPGA JTAG Expansion connector supports Cyclone V FPGA’s JTAG interface for debug and Configuration purpose. Note: iWave supports different Soft IPs for Cyclone V FPGA. Please contact iWave for more details. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 38 of 53...

  • Page 39: Table 10: Expansion Connector Pin Assignment

    FPGA_AG11_DFIO4A_TXB48P FPGA IO/ O, 2.5V LVDS Transmit output differential pair AG11 positive. FPGA_AF27_DFIO4A_TXB80P FPGA IO/ O, 2.5V LVDS Transmit output differential pair AF27 positive. Power Ground. Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 39 of 53...
  • Page 40 FPGA_AE24_DFIO4A_RXB74P FPGA IO/ I, 2.5V LVDS Receive input differential pair positive. AE24 FPGA_AC22_DFIO4A_RXB75P FPGA IO/ I, 2.5V LVDS Receive input differential pair positive. AC22 Power Ground. Power Ground. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 40 of 53...
  • Page 41 Receive input differential pair positive. FPGA_T8_SMBUS_SDA FPGA IO/ IO, 3.3V OD/ SMBUS serial data. 4.7K PU Power Ground. FPGA_AF18_SEIO4A FPGA IO/ IO, 2.5V CMOS Single ended bidirectional signal. AF18 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 41 of 53...
  • Page 42 FPGA IO/ IO, 2.5V CMOS Single ended bidirectional signal. AG26 FPGA_JTAG_TDI TDI/ I, 3.3V CMOS JTAG Test data input. FPGA_AH26_SEIO4A FPGA IO/ IO, 2.5V CMOS Single ended bidirectional signal. AH26 REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 42 of 53...

  • Page 43: Technical Specification

    PWGIN signal from Qseven Edge must be inactive at the same time or before VCC goes down.  VCC must go down at the same time or before VCC_RTC goes down. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 43 of 53...

  • Page 44: Power Consumption

    Table 13: Power Consumption Task/Status Power Rail Current Drawn In System Idle In HPS Full load and FPGA LCD,PWM & GPIOs RTC power when VCC Power OFF state VCC_RTC 1.5uA REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 44 of 53...

  • Page 45: Environmental Characteristics

    Heat spreader has to be used with application specific thermal solutions like heat sinks, Chassis, fans, Heat pipes etc. iWave supports Heat Spreader Solution for Cyclone V SoC Qseven SOM. Please refer the below figure for Heat spreader dimension details. For Heat spreader ordering information, please refer section 4 ORDERING INFORMATION.

  • Page 46: Rohs Compliance

    3.2.4 Electrostatic Discharge iWave’s Cyclone V SoC Qseven SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation.

  • Page 47: Mechanical Characteristics

    Figure 12: Mechanical dimension of Qseven SOM- Top View Note: The Qseven PCB cooling plate shown above is to be used as a cooling interface between the Qseven module and the application specific cooling solution. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 47 of 53...

  • Page 48: Figure 13: Mechanical Dimension Of Qseven Som- Bottom View

    (4.5mm) and bottom side maximum height component is expansion connector (4.30mm) followed by Crystal (1.9mm). Please refer the below figure which gives height details of the Cyclone V SoC Qseven SOM. Figure 14: Mechanical dimension of Qseven SOM- Side View REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 48 of 53...

  • Page 49: Guidelines To Insert The Qseven Som Into Carrier Board

    (in the second photo), such that the board is fixed firmly into the expansion connectors. Figure 15: Qseven Module Insertion procedure Note: Photo shown above is for only reference and not exactly represents Cyclone V SoC Qseven SOM. REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 49 of 53...

  • Page 50: Ordering Information

    Heat Spreader for Cyclone V SoC Qseven SOM with 0.75mm thickness gap filler for CPU Important Note: Some of the above mentioned Part Numbers are subject to MOQ purchase. Please contact iWave for further details. Note: For SOM identification purpose, Product Part Number and SOM Unique Serial Number are pasted as Label with Barcode readable format on SOM.

  • Page 51: Cyclone V Soc Qseven Som Silk Screen

    Cyclone V SoC Qseven SOM’s PCB silkscreen top view and bottom view for Optional Feature’s Identifier are shown in the below Figures. This will be useful while mounting the Optional Features in Cyclone V SoC Qseven SOM. Figure 16: Silk Screen Top View REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 51 of 53...

  • Page 52: Figure 17: Silk Screen Bottom View

    Cyclone V SoC Qseven SOM Hardware User Guide Figure 17: Silk Screen Bottom View REL 1.0 iWave Systems Technologies Pvt. Ltd. Page 52 of 53...

  • Page 53: Cyclone V Soc Qseven Som Development Platform

    Cyclone V SoC Qseven SOM Development Platform iWave Systems supports Generic Qseven Carrier Board which is targeted for quick validation of high performance Qseven compatible CPU modules. Being a Nano-ITX form factor with 120mmx120mm size, the carrier board is highly packed with all necessary interfaces &...

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