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Summary of Contents for iWave iW-RainboW-G18M
- Page 1 SODIMM SOM Hardware User Guide iW-RainboW-G18M i.MX6UL/i.MX6ULL SODIMM SOM Hardware User Guide REL1.2 iWave Systems Technologies Pvt. Ltd. Page 1 of 55...
- Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL1.2 iWave Systems Technologies Pvt.
- Page 3 No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
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Page 4: Table Of Contents
2.7.1 eMMC Flash ..............................36 2.7.2 Micro SD Slot ............................... 36 2.7.3 QSPI Flash ..............................36 2.7.4 PMIC OTP Header ............................37 i.MX6UL/i.MX6ULL Pin Multiplexing on SODIMM Edge ................. 38 REL1.2 iWave Systems Technologies Pvt. Ltd. Page 4 of 55... - Page 5 Guidelines to insert the SODIMM SOM into Carrier board ................53 Guidelines to remove the SODIMM SOM from Carrier board ................ 53 APPENDIX II ..............................54 i.MX6UL/i.MX6ULL SODIMM SOM Development Platform ................54 REL1.2 iWave Systems Technologies Pvt. Ltd. Page 5 of 55...
- Page 6 Table 8: Power Input Requirement ..........................45 Table 9: Power Sequence Timing ............................ 46 Table 10: Power Consumption ............................47 Table 11: Environmental Specification ........................... 48 Table 12: Orderable Product Part Numbers ........................51 REL1.2 iWave Systems Technologies Pvt. Ltd. Page 6 of 55...
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Page 7: Introduction
SODIMM System On Module based on the NXP’s i.MX6UL/i.MX6ULL Applications Processor with PMIC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the i.MX6UL/i.MX6ULL SODIMM System On Module from a Hardware Systems perspective. - Page 8 Small Outline Dual in-line Memory Module System On Module Micro Ampere UART Universal Asynchronous Receiver/Transmitter Ultra Lite uSDHC Ultra Secured Digital Host Controller Universal Serial Bus USB OTG USB On The Go Voltage REL1.2 iWave Systems Technologies Pvt. Ltd. Page 8 of 55...
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Page 9: Terminlogy Description
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SOM. References • i.MX6UL/i.MX6ULL Applications Processors Datasheet • i.MX6UL/i.MX6ULL Applications Processors Reference Manual REL1.2 iWave Systems Technologies Pvt. Ltd. Page 9 of 55... -
Page 10: Important Note
In this signal, PWM4_OUT is the functionality which we are using and GPIO1_IO05 is the CPU pad name. Note: The above naming is not applicable for other signals which are not connected to CPU. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 10 of 55... -
Page 11: Architecture And Design
This section provides detailed information about the i.MX6UL/i.MX6ULL SODIMM SOM Features and Hardware architecture with high level block diagram. Also this section provides detailed information about SODIMM edge connector pin assignment and usage. i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram iW-RainboW-G18M-i.MX6UL/i.MX6ULL SODIMM SOM Block Diagram 10/100Mbps DDR3 (16bit) RMII... -
Page 12: I.mx6Ul/I.mx6Ull Sodimm Som Features
10/100Mbps Ethernet x 2 Ports • I2C x 1 Port • PWM x 2 Ports • Tamper Signals • General Purpose Clock • Boot Mode Signals • Power Control Signals REL1.2 iWave Systems Technologies Pvt. Ltd. Page 12 of 55... - Page 13 SODIMM edge connector, either one interface only can be used at a time. Only i.MX6UL3 version CPU supports tamper functionality. For all other i.MX6UL/i.MX6ULL CPU versions, tamper pins are used as only GPIOs. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 13 of 55...
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Page 14: I.mx6Ul/I.mx6Ull Cpu
Figure 2: i.MX6UL Simplified Block Diagram Note: Please refer the latest i.MX6UL/i.MX6ULL Datasheet & Reference Manual from NXP website for Electrical characteristics of i.MX6UL/i.MX6ULL Application CPU which may be revised from time to time. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 14 of 55... -
Page 15: Figure 3: I.mx6Ul/I.mx6Ull Cpu Devices Comparison
CPU has many sub version CPUs i.MX6UL0, i.MX6UL1, i.MX6UL2 & i.MX6UL3. Also i.MX6ULL CPU has many sub version CPUs i.MX6ULL0, i.MX6ULL1 & i.MX6ULL2 The difference between these CPUs from NXP’s factsheet is shown below for reference. Figure 3: i.MX6UL/i.MX6ULL CPU devices comparison REL1.2 iWave Systems Technologies Pvt. Ltd. Page 15 of 55... -
Page 16: Pmic
CPU and operates at 3.3 Voltage level. The NAND flash memory is physically located on topside of the SODIMM SOM. The NAND Flash size is expandable. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 16 of 55... -
Page 17: Sodimm Pcb Edge Connector
Important Note: Some of the interfaces mentioned in the following section are subject to available based on the i.MX6UL/i.MX6ULL CPU device version used in the SODIMM SOM. For more details, refer i.MX6UL/i.MX6ULL documents from NXP or contact iWave. REL1.2 iWave Systems Technologies Pvt. Ltd. -
Page 18: Uart Interface
LCD display,. For more details, refer SODIMM Edge Connector pins 143 to 146 & 148 to 174 on Table 5. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 18 of 55... -
Page 19: Parallel Camera Interface
Important Note: Since Audio and JTAG interface signals are multiplexed in same pins on i.MX6UL/i.MX6ULL CPU, these pins are connected to two places in SODIMM Edge connector and either one interface only can be used at a time. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 19 of 55... -
Page 20: Usb 2.0 Otg Interface
SODIMM edge connector. If ENET2 Ethernet PHY is not used on SOM, the same signals which are optionally connected to SODIMM edge can be used for RMII interface or UART interface (3ports) or Keypad (4x4) interface. Please contact iWave for more details on this support. REL1.2 iWave Systems Technologies Pvt. -
Page 21: I2C Interface
When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce Core interrupts. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 21 of 55... -
Page 22: General Purpose Clock
In this mode, i.MX6UL/i.MX6ULL boot media is selected by CPU eFUSE settings. Boot From eFuses Note: i.MX6 eFuse setting is not modified by iWave from silicon shipped value. In this mode, i.MX6UL/i.MX6ULL boot Serial Downloader media can be Programmed through its USB Mode OTG interface using MFG Tool. -
Page 23: Power Input
CPU power supply is Off, a button press greater in duration than 750ms asserts an output signal to request power from a power IC to power up the i.MX6UL/i.MX6ULL CPU. For more details, refer SODIMM Edge connector pins 179 on Table 5. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 23 of 55... -
Page 24: Table 5: 200-Pin Pcb Edge Connector Pin Assignment
(for I2C1_SDA) through resistor and default not populated. Note: Same signal is by default connected to SODIMM edge connector 115 pin. VIN_3V3 I, 3.3V Power Supply Voltage. Power Ground. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 24 of 55... - Page 25 UART5_RTS(GPIO1_IO GPIO1_IO08/N17 I, 3.3V CMOS UART5 ready to send data. USB_OTG2_OC(GPIO1 GPIO1_IO08/L17 I, 3.3V CMOS Over current sense for USB OTG2. _IO03) Power Ground. Power Ground. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 25 of 55...
- Page 26 GPIO functionality. Power Ground. VIN_3V3 I, 3.3V Power Supply Voltage. JTAG_TCK/SAI2_RX_D JTAG_TCK/ I, 3.3V CMOS Audio receive data. Note: Same signal is also connected to 197 pin of SODIMM edge connector. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 26 of 55...
- Page 27 Tamper functionality. In all other i.MX6UL/i.MX6ULL CPU version SODIMM SOM, this pin can be used as only GPIO functionality. USB_OTG1_CHD_B USB_OTG1_CHD_B I, 3.3V CMOS USB Charge Detect. /U16 REL1.2 iWave Systems Technologies Pvt. Ltd. Page 27 of 55...
- Page 28 Note: Same signal is also connected to 195 pin of SODIMM edge connector. Default NC. Note: Boot_Mode0 is optionally connected to this pin (for GPIO) through resistor and default not populated. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 28 of 55...
- Page 29 I, 3.3V CMOS UART5 serial data receiver. CSI_DATA04 CSI_DATA04/ I, 3.3V CMOS Parallel camera data 4. SD1_CD_B(UART1_RTS UART1_RTS_B/ I, 3.3V CMOS SD Card Detect. VIN_3V3 I, 3.3V Power Supply Voltage. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 29 of 55...
- Page 30 O, 3.3V CMOS Parallel Camera Master Clock. CSI0_HSYNC CSI0_HSYNC/ I, 3.3V CMOS Parallel Camera HSYNC. VIN_3V3 I, 3.3V Power Supply Voltage. GPIO1_IO18(UART1_C UART1_CTS_B/ IO, 3.3V CMOS General purpose input/output. TS_B) REL1.2 iWave Systems Technologies Pvt. Ltd. Page 30 of 55...
- Page 31 Note: GPIO1_IO05 is optionally connected to this pin (for OTG2_ID) through resistor and default not populated. USB_OTG2_PWR(GPIO GPIO1_IO02/ O, 3.3V CMOS Power enable signal to control USB Power switch, to supply VBUS voltage 1_IO02) REL1.2 iWave Systems Technologies Pvt. Ltd. Page 31 of 55...
- Page 32 O, 3.3V CMOS/ Parallel LCD data 10 (Green data2). 10K PD² VIN_3V3 I, 3.3V Power Supply Voltage. LCD_DATA11 LCD_DATA11/ O, 3.3V CMOS/ Parallel LCD data 11 (Green data3). 10K PD² REL1.2 iWave Systems Technologies Pvt. Ltd. Page 32 of 55...
- Page 33 CPU’s ONOFF pin which has internal pullup and so don’t add any external pullup in carrier board on this pin. VIN_3V3 I, 3.3V Power Supply Voltage. Power Ground. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 33 of 55...
- Page 34 192 VIN_3V3 I, 3.3V Power Supply Voltage. 193 JTAG_TRST_B/SAI2_TX JTAG_TRST_B/ I, 3.3V CMOS JTAG reset. _DATA Note: Same signal is also connected to 67 of SODIMM edge connector. 194 NC REL1.2 iWave Systems Technologies Pvt. Ltd. Page 34 of 55...
- Page 35 ² Termination value is mentioned based on NAND flash as boot media. If boot media is changed, termination value also may change. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 35 of 55...
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Page 36: Optional Features
SODIMM SOM has PCB footprint option for some features which are not supported by default. These optional features are explained in the following sections. To add any of these optional features in i.MX6UL/i.MX6ULL SODIMM SOM, please contact iWave. 2.7.1 eMMC Flash i.MX6UL/i.MX6ULL SODIMM SOM supports an eMMC memory as mass storage and also can be used as boot device. -
Page 37: Pmic Otp Header
Supply voltage to PMIC OTP fuses. VIN_3V3 I, Power Input Voltage. I, Power Ground. I2C1_SCL(UART4_TX_DATA)_PMIC I, 3.3V OD I2C clock. I2C1_SDA(UART4_RX_DATA)_PMIC IO, 3.3V OD I2C data. PWRON I, Power Power ON/OFF input from CPU REL1.2 iWave Systems Technologies Pvt. Ltd. Page 37 of 55... -
Page 38: I.mx6Ul/I.mx6Ull Pin Multiplexing On Sodimm Edge
Applications Processor Reference Manual (Rev0). Important Note: It is strongly recommended to use the pin function same as selected in the i.MX6UL/i.MX6ULL SOIDMM SOM Edge connector for iWave’s BSP reusability and to have compatible SODIMM modules in future for upgradability. - Page 39 SAI2_RX_D FLEXCAN2_T EIM_ADDR2 GPIO2_IO20 CCM_CLKO1 USB_OTG2_ USDHC1_DATA URE1 SD1_DATA3 USDHC1_DA GPT2_CAPT SAI2_TX_D FLEXCAN2_R EIM_ADDR2 GPIO2_IO21 CCM_CLKO2 ANATOP_OT USDHC1_DATA URE2 G2_ID UART1_RTS_B UART1_RTS ENET1_TX_ USDHC1_C CSI_DATA05 ENET2_1588 GPIO1_IO19 USDHC2_CD UART1_RTS_B _EVENT1_O REL1.2 iWave Systems Technologies Pvt. Ltd. Page 39 of 55...
- Page 40 FLEXCAN2_T LCDIF_DATA10 LCDIF_DATA1 LCDIF_DATA SAI3_RX_BC CSI_DATA19 EIM_DATA0 GPIO3_IO16 SRC_BT_CFG FLEXCAN2_R LCDIF_DATA11 LCDIF_DATA1 LCDIF_DATA SAI3_TX_SY CSI_DATA20 EIM_DATA0 GPIO3_IO17 SRC_BT_CFG ECSPI1_RDY LCDIF_DATA12 LCDIF_DATA1 LCDIF_DATA SAI3_TX_BC CSI_DATA21 EIM_DATA0 GPIO3_IO18 SRC_BT_CFG USDHC2_RE LCDIF_DATA13 SET_B REL1.2 iWave Systems Technologies Pvt. Ltd. Page 40 of 55...
- Page 41 LCDIF_DATA23 LCDIF_ENABL LCDIF_ENAB LCDIF_RD_E UART4_RX SAI3_TX_SY EIM_CS3_B GPIO3_IO01 ECSPI2_RDY LCDIF_ENABLE LCDIF_HSYNC LCDIF_HSYN LCDIF_RS UART4_CTS SAI3_TX_BCL WDOG3_WD GPIO3_IO02 ECSPI2_SS1 LCDIF_HSYNC OG_RST_B_ LCDIF_VSYNC LCDIF_VSYN LCDIF_BUSY UART4_RTS SAI3_RX_DA WDOG2_WD GPIO3_IO03 ECSPI2_SS2 LCDIF_VSYNC OG_B REL1.2 iWave Systems Technologies Pvt. Ltd. Page 41 of 55...
- Page 42 CCM_CLKO2 CCM_STOP GPIO1_IO12 MQS_RIGHT EPIT2_OUT SJC_TDO Audio URE2 JTAG_TMS SJC_TMS GPT2_CAPT SAI2_MCLK CCM_CLKO1 CCM_WAIT GPIO1_IO11 SDMA_EXT_ EPIT1_OUT SJC_TMS URE1 EVENT01 JTAG_TRST_B SJC_TRSTB GPT2_COM SAI2_TX_D PWM8_OUT GPIO1_IO15 CAAM_RNG SJC_TRSTB PARE3 _OSC_OBS REL1.2 iWave Systems Technologies Pvt. Ltd. Page 42 of 55...
- Page 43 EIM_EB_B02 GPIO2_IO11 KPP_COL05 ENET2_TX_DA TA00 0_SVEN ENET2_TX_DA ENET2_TDA UART8_TX SIM2_PORT ECSPI4_SCLK EIM_EB_B03 GPIO2_IO12 KPP_ROW06 USB_OTG2_ ENET2_TX_DA TA01 0_TRXD ENET2_TX_EN ENET2_TX_ UART8_RX SIM2_PORT ECSPI4_MOS EIM_ACLK_F GPIO2_IO13 KPP_COL06 USB_OTG2_ ENET2_TX_EN 0_CLK REERUN REL1.2 iWave Systems Technologies Pvt. Ltd. Page 43 of 55...
- Page 44 ¹ Only i.MX6UL3 version CPU supports tamper functionality on these pins and doesn’t support GPIO functionality. For all other i.MX6UL/i.MX6ULL CPU versions, these tamper pins are used as only GPIOs. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 44 of 55...
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Page 45: Technical Specification
² i.MX6UL/i.MX6ULL SODIMM SOM uses this voltage as backup power source to RTC when VIN_3V3 is off. This is an optional power and required only if RTC functionality is used. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 45 of 55... -
Page 46: Power Input Sequencing
Important Note: i.MX6UL/i.MX6ULL CPU IO pins should not be externally driven from the carrier board until VIN_3V3 is powered up. Otherwise this can cause internal latch-up and malfunctions due to reverse current flows. REL1.2 iWave Systems Technologies Pvt. Ltd. Page 46 of 55... -
Page 47: Power Consumption
VRTC_3V0 500uA provided Power consumption measurements have been done in iWave’s i.MX6UL3 CPU based SODIMM SOM with iWave’s SODIMM Carrier board running iWave’s Linux3.14.38 BSP (iW-RainboW-G18M-SM-R2.0-REL1.0-Linux3.14.38- YoctoFido_Deliverables). i.MX6UL/i.MX6ULL CPU’s RTC controller draws more power from VRTC_3V0 coin cell power input and so could drain the coin cell faster. -
Page 48: Environmental Characteristics
3.2.3 Electrostatic Discharge iWave’s i.MX6UL/i.MX6ULL SODIMM SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation. -
Page 49: Mechanical Characteristics
Please refer the JEDEC Physical standard DDR S.O.DIMM specification for SODIMM Edge connector mechanical details. Figure 7: Mechanical dimension of SODIMM SOM - Top View Figure 8: Mechanical dimension of SODIMM SOM - Bottom View REL1.2 iWave Systems Technologies Pvt. Ltd. Page 49 of 55... -
Page 50: Figure 9: Mechanical Dimension Of Sodimm Som - Side View
1.45mm) followed by CPU (1.32mm) and bottom side maximum height component is Capacitor (C68, 1.45mm) followed by Diode (D3,1.0mm ). Please refer the below figure which gives height details of the i.MX6UL/i.MX6ULL SODIMM SOM. Figure 9: Mechanical dimension of SODIMM SOM - Side View REL1.2 iWave Systems Technologies Pvt. Ltd. Page 50 of 55... -
Page 51: Ordering Information
If the desired part number is not listed in below table, or if any custom configuration part number is required, please contact iWave. Also please contact iWave for orderable part number of i.MX6UL/i.MX6ULL SODIMM SOM with higher RAM memory size or Flash memory size configurations. - Page 52 256MB NAND Flash with Boot Code. Important Note: Some of the above mentioned Part Number is subject to MOQ purchase. Please contact iWave for further details. Note: For SOM identification purpose, Product Part Number and SOM Unique Serial Number are pasted as Label with Barcode readable format on SOM.
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Page 53: Guidelines To Insert The Sodimm Som Into Carrier Board
When you remove the SODIMM SOM, pull away the retention clips (A) on each side of the SOM. • The SODIMM SOM pops up. Grasp the edge of the SOM (B) and gently pull the SOM out of the connector. Figure 11: SODIMM SOM Removal procedure REL1.2 iWave Systems Technologies Pvt. Ltd. Page 53 of 55... -
Page 54: I.mx6Ul/I.mx6Ull Sodimm Som Development Platform
6. APPENDIX II i.MX6UL/i.MX6ULL SODIMM SOM Development Platform iWave Systems supports iW-RainboW-G18D – i.MX6UL/i.MX6ULL SODIMM Development Platform which is targeted for quick validation of i.MX6UL/i.MX6ULL CPU. iWave's i.MX6UL/i.MX6ULL SODIMM Development Board incorporates i.MX6UL/i.MX6ULL SODIMM SOM and SODIMM Carrier board for complete validation of i.MX6UL/i.MX6ULL SODIMM SOM functionality with complete BSP support. - Page 55 SODIMM SOM Hardware User Guide REL1.2 iWave Systems Technologies Pvt. Ltd. Page 55 of 55...
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