Analog Devices DC981A Demo Manual page 3

OPERATING PRINCIPLES
The DC981 provides two implementations of a PSE con-
trolled by the LTC4263, a midspan PSE and an endpoint
PSE. A single 48V supply is all that is required to power
the board. This in turn provides power to the midspan PSE
and endpoint PSE outputs. On each solution, an LTC4263
provides detection, classification, power management, safe
power on, port current limit, and disconnect detection.
Midspan PSE
In the midspan solution, a legacy device (router, switch,
etc.) that does not have PoE is connected to MIDSPAN
IN. Data is passed through to MIDSPAN OUT along with
PoE which goes out to a PD. Power is applied directly
to Ethernet pairs 4/5 and 7/8. The LTC4263 circuitry is
located in a small layout area behind the RJ45 connec-
tor and switches power on the negative rail. To show the
different functions of the LTC4263, jumpers allow for the
user to select the options of AC or DC disconnect, legacy
detection, midspan backoff timing, and class enforce-
ment. An LED that shows the status of the port is driven
by a switcher in the LTC4263 to improve efficiency when
VDD5 is provided internally. Push button switch SW1 ties
the shutdown pin to ground to disable the LTC4263 in the
midspan solution.
A PSE implementing alternative B pin out must back off
from detection for at least two seconds after a failed at-
tempt. This is to avoid conflict of detection, for example,
should a potential endpoint PSE and midspan PSE be
connected to the same PD. To enable this feature, set JP2
to DIS. JP2 ties the MIDSPAN pin to VDD5 to enable the
LTC4263 backoff timer or to VSS to disable. A 3.2s delay
occurs after every failed detect cycle unless the result is
open circuit. If held at VSS, no delay occurs after failed
detect cycles.
Endpoint PSE
The endpoint solution is primarily shown on a small
daughter card (DC981B). This card is the same height
and width as the integrated RJ45 connector that it slides
behind on the main board (DC981A). The RJ45 includes
Ethernet magnetics and common mode termination. A
layout option shows the same components can be placed
DEMO MANUAL
DC981A/DC981B
under the same RJ45 connector. The minimum connections
to the daughter card are VSS, VDD48 and VOUT. Power is
switched over from the daughter card out to the Ethernet
data pairs (1/2 and 3/6). A PHY can be connected to the
TO PHY connector to pass data through to the data pairs
along with PoE. LED drive and power management pins
are also brought out for additional board functions. The
board is set up for AC disconnect, but can be reworked
for DC disconnect by removing components and replac-
ing with shorts in certain locations. Two solder jumpers
also provide selectable options for legacy detection and
class enforce.
Power Management
The midspan and endpoint PSEs, although separate solu-
tions on the DC981, are tied together at the PWRMGT pin
for demonstration of the LTC4263 power management
capability. Programmable onboard power management
circuitry allows multiple LTC4263s to allocate and share
power in multiport systems, allowing maximum utilization
of the 48V power supply – all without the intervention of
a host processor.
The LTC4263 sources current (IPM) at the PWRMGT pin
proportional to the class of the PD that it is powering. The
voltage of this pin (VPM) is checked before powering the
port (Table 2). The port will not turn on if this pin is more
than 1V above VSS. The PWRMGT pins of the LTC4263s
are tied together and connect to a resistor (RPM) and
capacitor (CPM) in parallel to VSS to implement power
management. This resistor is selected with the following
equation:
R = 213kΩ • W/P
PM FULL_LOAD
On the DC981A, the default RPM is 12.4kΩ for a full load
power of 17W.
Table 2. Power Management Voltage
PD CLASS POWER
REQUEST
Class 1 4W
Class 2 7W
Class 0, 3, or 4 15.4W
*RPM = 12.4kΩ
IPM (TYP) VPM*
19μA 236mV
33μA 409mV
73μA 905mV
Rev A
3