ARTERY AT32A403A Series Reference Manual

Arm-based 32-bit cortex-m4f mcu+fpu with 256 to 1024 kb flash, slib, usb, 2 cans, 17 timers, 3 adcs, 20 communication interfaces

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ARM

-based 32-bit Cortex

USB, 2 CANs, 17 timers, 3 ADCs, 20 communication interfaces

Feature



Core: ARM

32-bit Cortex

− 200 MHz maximum frequency, with a Memory

Protection Unit (MPU), single-cycle multiplication

and hardware division

− Floating Point Unit (FPU)

− DSP instructions



Memories

− 256 to 1024 KBytes of Flash memory

− sLib: configure any part of main Flash as a library

area that is code executable but secured and non-

readable

− SPIM interface: extra interfacing up to 16 Mbytes of

external SPI Flash (as instruction/data memory)

− Up to 96 + 128 KBytes of SRAM

− External memory controller (XMC) with 2 Chip

Select, supporting multiplexed SRAM/NOR/PSRAM

and NAND memories

− LCD parallel interface, 8080/6800 modes



Clock, Reset, and Power management

− 2.6 V ~ 3.6 V application supply and I/Os

− Power on reset (POR)/ low voltage reset (LVR), and

power voltage monitor (PVM)

− 4 to 25 MHz crystal (HEXT)

− Internal 48 MHz factory-trimmed RC (accuracy 1%

at T

=25 °C, 2.5 % at T

automatic clock calibration (ACC)

− Internal 40 kHz RC oscillator (LICK)

− 32.768 kHz crystal oscillator (LEXT)



Low power consumption

− Sleep, Deepsleep, and Standby modes

− V

supply for RTC and 42 x 16-bit battery powered

BAT

registers (BPR)



3 x 12-bit 0.5 μs A/D converters, up to 16 channels

− Conversion range: 0 V to 3.6 V

− Triple sample and hold capability

− Temperature sensor



2 x 12-bit D/A converters



DMA: 14-channel DMA controller

− Peripherals supported: timers, ADCs, SDIOs,

Ss, SPIs, I

Cs, and USARTs



Debug Mode

−

Serial wire debug (SWD) and JTAG interface

2022.11.11

AT32A403A Series Reference Manual

-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,

-M4F CPU with FPU

=-40 to +105 °C), with

− Cortex

-M4F Embedded Trace Macrocell (ETM



Up to 80 Fast I/O Interfaces

− 37/51/80 multifunctional and bidirectional I/Os, all

mappable to 16 external interrupt vectors and almost 5

V-tolerant

− All fast I/Os, control registers accessible with f



Up to 17 Timers

− Up to 8 x 16-bit general-purpose timers + 2 x 32-bit

general-purpose timers; each with 4 IC/OC/PWM or

pulse counter and quadrature (incremental) encoder

input.

− Up to 2 x 16-bit motor control PWM advanced timers

with dead-time generator and emergency brake

− 2 x Watchdog timers

− SysTick timer: 24-bit downcounter

− 2 x 16-bit basic timers to drive the DAC



Up to 20 Communication Interfaces

− Up to 3 x I

C interfaces (SMBus/PMBus)

− Up to 8 x USARTs (ISO7816 interface, LIN, IrDA

capability, and modem control)

− Up to 4 x SPIs (50 Mbit/s), all with I

multiplexed, I

S2/ I

− Up to 2 x CAN interfaces (2.0B Active)

− USB2.0 full-speed interface supporting Crystal-less

− Up to 2 x SDIO interfaces



CRC Calculation Unit



96-bit unique ID (UID)



Packages

− LQFP100 14x14 mm

− LQFP64 10x10 mm

− LQFP48 7x7 mm

− QFN48 6 x 6 mm



List of Models

Internal Flash

AT32A403ACGU7, AT32A403ACGT7,

1024 KBytes

AT32A403ARGT7, AT32A403AVGT7

AT32A403ACEU7, AT32A403ACET7,

512 KBytes

AT32A403ARET7, AT32A403AVET7

AT32A403ACCU7, AT32A403ACCT7,

256 KBytes

AT32A403ARCT7, AT32A403AVCT7

AT32A403A series: AEC-Q100 Grade 2 certified

Page 1

AHB

S interface

S3 support full-duplex

Model

)

speed

Rev 2.00

Table of Contents

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Summary of Contents for ARTERY AT32A403A Series

Page 1 − Peripherals supported: timers, ADCs, SDIOs, AT32A403ACCU7, AT32A403ACCT7, 256 KBytes Ss, SPIs, I Cs, and USARTs AT32A403ARCT7, AT32A403AVCT7  AT32A403A series: AEC-Q100 Grade 2 certified Debug Mode − Serial wire debug (SWD) and JTAG interface 2022.11.11 Page 1 Rev 2.00...
Page 2: Table Of Contents
AT32A403A Series Reference Manual Contents System architecture ..............30 System overview ................32 ® 1.1.1 ARM Cortex -M4F processor ............32 1.1.2 Bit band ..................33 1.1.3 Interrupt and exception vectors ............ 35 1.1.4 System Tick (SysTick) ..............38 1.1.5 Reset ..................38 List of abbreviations for registers ..........
Page 3 AT32A403A Series Reference Manual 4.1.1 Clock sources ................52 4.1.2 System clock ................53 4.1.3 Peripheral clock ................53 4.1.4 Clock fail detector ............... 54 4.1.5 Auto step-by-step system clock switch .......... 54 4.1.6 Internal clock output ..............54 4.1.7 Interrupts ..................54 Reset ..................
Page 4 AT32A403A Series Reference Manual 5.4.1 Unlock/lock ................. 79 5.4.2 Erase operation ................79 5.4.3 Programming operation..............80 5.4.4 Read operation ................81 Flash memory protection .............. 81 5.5.1 Access protection ................ 82 5.5.2 Erase/program protection............. 82 Special functions ................. 82 5.6.1 Security library settings ...............
Page 5 AT32A403A Series Reference Manual 5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) ....92 5.7.27 Flash CRC check result register (FLASH_CRC_CHKR) ....92 General-purpose I/Os (GPIOs) ............93 Introduction ................. 93 Function overview ................ 93 6.2.1 GPIO structure ................93 6.2.2 GPIO reset status ................ 94 6.2.3 General-purpose input configuration ..........
Page 6 AT32A403A Series Reference Manual 7.4.1 Event output control register (IOMUX_EVTOUT) ......109 7.4.2 IOMUX remap register (IOMUX_REMAP) ........110 7.4.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1) 112 7.4.4 IOMUX external interrupt configura tion register2 (IOMUX_EXINTC2)113 7.4.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3) 113 7.4.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4) 114...
Page 7 AT32A403A Series Reference Manual 9.3.7 Fixed DMA request mapping ............128 9.3.8 Flexible DMA request mapping ............ 130 DMA registers ................131 9.4.1 DMA interrupt status register (DMA_STS) ........132 9.4.2 DMA interrupt flag clear register (DMA_CLR) ....... 134 (x = 1…7) 136 9.4.3 DMA channelx configuration register (DMA_CxCTRL)
Page 8 AT32A403A Series Reference Manual 11.5.2 Control register2 (I2C_CTRL2) ............ 158 11.5.3 Own address register 1 (I2C_OADDR1) ........159 11.5.4 Own address register 2 (I2C_OADDR2) ........159 11.5.5 Data register (I2C_DT) ............... 160 11.5.6 Status register1 (I2C_STS1) ............160 11.5.7 Status register 2 (I2C_STS2) ............162 11.5.8 Clock control register (I2C_ CLKCTRL) ........
Page 9 AT32A403A Series Reference Manual 12.11.3 Baud rate register (USART_BAUDR) ........177 12.11.4 Control register1 (USART_CTRL1) ........... 178 12.11.5 Control register2 (USART_CTRL2) ........... 179 12.11.6 Control register3 (USART_CTRL3) ........... 180 12.11.7 Guard time and divider register (GDIV) ........181 Serial peripheral interface (SPI) ..........182 13.1 SPI introduction .................
Page 10 AT32A403A Series Reference Manual 13.4.3 SPI status register (SPI_STS) ............. 203 13.4.4 SPI data register (SPI_DT) ............204 13.4.5 SPICRC register (SPI_CPOLY) (Not used in I S mode) ....204 13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode) ....204 13.4.7 SPITxCRC register (SPI_TCRC) ..........
Page 11 AT32A403A Series Reference Manual 14.2.4.2 Control register2 (TMRx_CTRL2) ........... 229 14.2.4.3 Slave timer control register (TMRx_STCTRL) ......229 14.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ......230 14.2.4.5 Interrupt status register (TMRx_ISTS) ........231 14.2.4.6 Software event register (TMRx_SW EVT) ......... 232 14.2.4.7 Channel mode register1 (TMRx_CM1) ........
Page 12 AT32A403A Series Reference Manual 14.3.4.9 Division value (TMRx_DIV) ............ 256 14.3.4.10 Period register (TMRx_PR) ..........256 14.3.4.11 Channel 1 data register (TMRx_C1DT) ....... 256 14.3.4.12 Channel 2 data register (TMRx_C2DT) ....... 256 14.3.5 TMR10, TMR11, TMR13 and TMR14 registers ......257 14.3.5.1 Control register1 (TMRx_CTRL1) ...........
Page 13 AT32A403A Series Reference Manual 14.4.4.12 TMR1 and TMR8 period register (TMRx_PR) ....... 294 14.4.4.13 TMR1 and TMR8 repetition period register (TMRx_RPR) ..294 14.4.4.14 TMR1 and TMR8 channel 1 data register (TMRx_C1DT) ..294 14.4.4.15 TMR1 and TMR8 channel 2 data register (TMRx_C2DT) ..294 14.4.4.16...
Page 14 AT32A403A Series Reference Manual 17.4 RTC functional overview ............. 305 17.4.1 Configuring RTC registers............305 17.4.2 Reading RTC registers ............... 306 17.4.3 RTC interrupts ................306 17.5 RTC registers ................307 17.5.1 RTC control register high (RTC_CTRLH) ........307 17.5.2 RTC control register low (RTC_CTRLL) ........308 17.5.3 RTC divider register (RTC_ DIVH/RTC_DIVL) ......
Page 15 AT32A403A Series Reference Manual 19.4.3.1 Sequence mode ..............319 19.4.3.2 Automatic preempted group conversion mode ......319 19.4.3.3 Repetition mode..............320 19.4.3.4 Partition mode ..............320 19.4.4 Data management ..............321 19.4.4.1 Data alignment ..............321 19.4.4.2 Data read ................321 19.4.5 Voltage monitor ................
Page 16 AT32A403A Series Reference Manual 20.4 Function overview ..............337 20.4.1 Trigger events ................337 20.4.2 Noise/Triangular-wave generation ..........337 20.4.3 DAC data alignment ..............339 20.5 DAC registers ................339 20.5.1 DAC control register (DAC_CTRL) ..........339 20.5.2 DAC software trigger register (DAC_SWTRG) ......342 20.5.3 DAC1 12-bit right-aligned data holding register (DAC_D1DTH12R) 342...
Page 17 AT32A403A Series Reference Manual 21.7.1.1 CAN master control register (CAN_MCTRL) ......356 21.7.1.2 CAN master status register (CAN_MSTS) ........ 357 21.7.1.3 CAN transmit status register (CAN_TSTS) ......359 21.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ........ 361 21.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ........ 362 21.7.1.6 CAN interrupt enable register (CAN_INTEN) ......
Page 18 AT32A403A Series Reference Manual 22.4.2.2 Read/write operation with different timings ......380 22.4.2.3 Multiplexed mode ..............388 22.4.2.4 Synchronous mode..............390 22.5 NAND ..................392 22.5.1 Operation mode ................. 392 22.5.2 Access timings ................393 22.5.3 ECC computation ............... 395 22.6 XMC registers ................
Page 19 AT32A403A Series Reference Manual 23.3.3.3 SDIO AHB interface .............. 422 23.3.3.4 Hardware flow control............423 23.3.4 SDIO I/O card-specific operations ..........423 23.4 SDIO registers ................424 23.4.1 SDIO power control register (SDIO_ PWRCTRL) ......424 23.4.2 SDIO clock control register (SDIO_ CLKCTRL) ......425 23.4.3 SDIO argument register (SDIO_ARG) ..........
Page 20 AT32A403A Series Reference Manual 24.5.2 USBFS control register (USBFS_CTRL) ........439 24.5.3 USBFS interrupt status register (USBFS_INTSTS) ....... 440 24.5.4 USBFS SOF frame number register (USBFS_ SOFRNUM) ..... 441 24.5.5 USBFS device address register (USBFS_DEVADDR) ....441 24.5.6 USBFS buffer table address register (USBFS_ BUFTBL) ....441 24.5.7 USBFS CFG control register (USBFS_CFG) .........
Page 21 AT32A403A Series Reference Manual List of figures Figure 1-1 AT32A403A Series microcontrollers system architecture .............. 31 Figure 1-2 Internal block diagram of Cortex ® -M4F ..................32 Figure 1-3 Comparison between bit-band region and its alias region: image A ......... 33 Figure 1-4 Comparison between bit-band region and its alias region: image B .........
Page 22 AT32A403A Series Reference Manual Figure 12-6 Silent mode using Idle line or Address mark detection ............168 Figure 12-7 8-bit format USART synchronization mode ................168 Figure 12-8 Word length ..........................169 Figure 12-9 Stop bit configuration ......................170 Figure 12-10 TDC/TDBE behavior when transmitting ................172 Figure 12-11 Data sampling for noise detection ..................
Page 23 AT32A403A Series Reference Manual Figure 14-18 Counter timing diagram with internal clock divided by 4 ............. 217 Figure 14-19 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32....218 Figure 14-20 Encoder mode structure ....................... 218 Figure 14-21 Example of counter behavior in encoder interface mode (encoder mode C) ...... 219 Figure 14-22 Input/output channel 1 main circuit ..................
Page 24 AT32A403A Series Reference Manual Figure 14-63 Counting in external clock mode A, PR=0x32, DIV=0x0 ............. 266 Figure 14-64 Block diagram of external clock mode B ................266 Figure 14-65 Counting in external clock mode B, PR=0x32, DIV=0x0 ............. 266 Figure 14-66 Counter timing with prescaler value changing from 1 to 4 ..........267 Figure 14-67 Basic structure of a counter ....................
Page 25 AT32A403A Series Reference Manual Figure 19-11 Regular simultaneous mode ....................323 Figure 19-12 Alternate preempted trigger mode ..................323 Figure 19-13 Fast switch mode ......................... 324 Figure 19-14 Fast slow mode ........................325 Figure 20-1 DAC1/DAC2 block diagram ....................336 Figure 20-2 LFSR register calculation algorithm ..................
Page 26 AT32A403A Series Reference Manual Figure 23-5 SDIO sequential write operation .................... 406 Figure 23-6 SDIO block diagram ....................... 418 Figure 23-7 Command channel state machine (CCSM) ................420 Figure 23-8 SDIO command transfer ......................421 Figure 23-9 Data channel state machine (DCSM) ..................421 Figure 24-1 Buffer description table of regular endpoint vs.
Page 27 Table 1-1 Bit-band address mapping in SRAM ................... 34 Table 1-2 Bit-band address mapping in the peripheral area ............... 34 Table 1-3 AT32A403A series vector table ....................35 Table 1-4 List of abbreviations for registers ....................39 Table 1-5 List of abbreviations for registers ....................40 Table 2-1 Peripheral boundary address ......................
Page 28 AT32A403A Series Reference Manual Table 14-7 TMRx internal trigger connection ..................... 241 Table 14-8 TMR9/12 register map and reset value ................... 249 Table 14-9 Standard CxOUT channel output control bit ................255 Table 14-10 TMR10/11/13/14 register map and reset value ..............257 Table 14-11 Standard CxOUT channel output control bit ................
Page 29 AT32A403A Series Reference Manual Table 22-25 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) ... 389 Table 22-26 Synchronous mode — SRAM/NOR Flash chip select control register (XMC_ BK1CTRL) .. 390 Table 22-27 Synchronous mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) ..391 Table 22-28 Typical pin signals for NAND Flash ..................
Page 30: System Architecture
AT32A403A Series Reference Manual 1 System architecture ® ® AT32A403A series microcontrollers consist of 32-bit ARM Cortex -M4F processor core, multiple 16-bit and 32-bit timers, DMA controller, RTC, communication interfaces such as SPI, I2C, USART/UART and SDIO, CANs, external memory controller (XMC), USB2.0 full-speed interface, HICK with automatic clock calibration (ACC), 12-bit ADC, 12-bit DAC, programmable voltage monitor (PVM) and other peripherals.
Page 31: Figure 1-1 At32A403A Series Microcontrollers System Architecture
AT32A403A Series Reference Manual Figure 1-1 AT32A403A Series microcontrollers system architecture HEXT 4~25MHz SWJTAG HICK 48MHz Max. 200MHz SDIO1/2 Cortex-M4 FCLK (Freq. Max. 200MHz) HCLK PCLK1 NVIC PCLK2 DMA1 7 Channel @VDD Flash DMA2 Flash POR/LVR Controller 7 Channel SRAM SRAM LDO 1.2V...
Page 32: System Overview
AT32A403A Series Reference Manual 1.1 System overview ® 1.1.1 ARM Cortex -M4F processor Cortex ® -M4F processor is a low power consumption processor featuring low gate count, low interrupt latency, and low-cost debug. It supports DSP instruction set and FPU, and is applicable to deeply-embedded applications that require quicker response to interruption.
Page 33: Bit Band
AT32A403A Series Reference Manual 1.1.2 Bit band Through bit-band operations, read and write access to a single bit can be performed using common load/store operations. The Cortex ® -M4F memory includes two bit-band regions: the least significant 1M byte of SRAM and the least significant 1M byte of peripherals. In addition to access to bit-band addresses, their respective bit-band alias area can be used to access to any bit of any address.
Page 34: Table 1-1 Bit-Band Address Mapping In Sram
AT32A403A Series Reference Manual number, then perform read-modify-write operation on bit level. The address ranges of two memories supporting bit-band operations: The lowest 1 Mbyte of SRAM: 0x2000_0000~0x200F_FFFF The lowest 1 Mbyte of peripherals: 0x4000_0000~0x400F_FFFF For a bit in the SRAM bit-band region, if the byte address is A, the bit number is n (0<=n<=7), then the...
Page 35: Interrupt And Exception Vectors
When it comes to multiples tasks, it turns the read-modify-write operations into a hardware-supported atomic operation to avoid the scenario where the read-modify-write operation is disrupted, resulting in disorder. 1.1.3 Interrupt and exception vectors Table 1-3 AT32A403A series vector table Priority Pos. Priority Name Description...
Page 36 AT32A403A Series Reference Manual Configur EXINT3 EXINT line3 interrupt 0x0000_0064 able Configur EXINT4 EXINT line4 interrupt 0x0000_0068 able Configur DMA1 channel1 DMA1 channel1 global interrupt 0x0000_006C able Configur DMA1 channel2 DMA1 channel2 global interrupt 0x0000_0070 able Configur DMA1 channel3 DMA1 channel3 global interrupt...
Page 37 AT32A403A Series Reference Manual Configur TMR8 break interrupt and TMR12 global TMR8_BRK_TMR12 0x0000_00EC able interrupt Configur TMR8 overflow interrupt and TMR13 TMR8_OVF_TMR13 0x0000_00F0 able global interrupt Configur TMR8_TRG_HALL_TMR TMR8 trigger and HALL interrupt and 0x0000_00F4 able TMR14 global interrupt Configur...
Page 38: System Tick (Systick)
AT32A403A Series Reference Manual Configur UART7 UART7 global interrupt 0x0000_0174 able Configur UART8 UART8 global interrupt 0x0000_0178 able Note: USBFS module interrupt supports remap through the USBINTMAP bit in the CRM_INTMAP register. When USBINTMAP=0, use USBFS_H (19th) and USBFS_ L (20th) interrupts; when USBINTMAP=1, use USB_MAPH (73rd) and USB_MAPL (74th) interrupts.
Page 39: List Of Abbreviations For Registers
0x0000_0004 0x0000_0000 0x2000_8000 In the AT32A403A series, the main Flash memory, boot memory or SRAM can be remapped to the code area between 0x0000_0000 and 0x07FF_FFFF. BOOT1 and BOOT0 are used to set the specific memory from which CODE starts.
Page 40: Device Characteristics Information
AT32A403A Series Reference Manual 1.3 Device characteristics information Table 1-5 List of abbreviations for registers Register abbr. Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID[31: 0] 0x1FFF F7E8 0xXXXX XXXX UID[63: 32] 0x1FFF F7EC 0xXXXX XXXX UID[95: 64] 0x1FFF F7F0 0xXXXX XXXX 1.3.1...
Page 41: Memory Resources
AT32A403A Series Reference Manual 2 Memory resources 2.1 Internal memory address map Internal memory contains program memory (Flash), data memory (SRAM), peripheral registers and core registers. Their respective address mapping are shown in Figure 2-1. Figure 2-1 AT32A403A address mapping...
Page 42: Flash Memory
AT32A403A Series Reference Manual 2.2 Flash memory AT32A403A series provide up to 1024 KB of on-chip Flash memory, supporting a zero wait state single cycle 32-bit read operation. Refer to Chapter 5 for more details about Flash memory controller and register configuration.
Page 43: Sram Memory
0x1FFF F800 – 0x1FFF F82F 2.3 SRAM memory The AT32A403A series contains up to 96 KB of on-chip SRAM which starts at the address 0x2000_0000. It supports byte, half-word (16 bit) and word (32 bit) accesses. In addition, AT32A403A also provides a special mode that supports dynamic switch between 96 KB and 224 KB.
Page 44 AT32A403A Series Reference Manual 0x4001 5C00 - 0x4001 5FFF 0x4001 5800 - 0x4001 5BFF 0x4001 5400 - 0x4001 57FF TMR11 timer 0x4001 5000 - 0x4001 53FF TMR10 timer 0x4001 4C00 - 0x4001 4FFF TMR9 timer 0x4001 4400 - 0x4001 4BFF...
Page 45 AT32A403A Series Reference Manual 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Watchdog timer (WDT) Window watchdog timer 0x4000 2C00 - 0x4000 2FFF (WWDT) 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF...
Page 46: Power Control (Pwc)
3 Power control (PWC) 3.1 Introduction For AT32A403A series, its operating voltage supply is 2.6 V ~ 3.6 V, with an operating temperature range of -40~+105 °C. To reduce power consumption, this series provides three types of power saving modes, including Sleep, Deepsleep and Standby modes so as to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 47: Power Voltage Monitor (Pvm)
AT32A403A Series Reference Manual Figure 3-2 Power-on reset/Low voltage reset waveform hysteresis Temporization tRESTTEMPO Reset 3.4 Power voltage monitor (PVM) The PVM is used to monitor the power supply variations. It is enabled by setting the PVMEN bit in the power control register (PWC_CTRL), and the threshold value for voltage monitor is selected with the PVMSEL[2: 0].
Page 48: Power Domain
AT32A403A Series Reference Manual 3.5 Power domain 1.2 V domain 1.2 V core domain includes a CPU core, SRAM, embedded digital peripherals and Phase Locked Loop (PLL). Such power domain is supplied by LDO (voltage regulator). VDD/VDDA domain VDD/VDDA domain includes VDD domain and VDDA domain. The VDD domain contains I/O circuit, power-saving mode wakeup circuit, watchdog timer, power-on reset/low voltage reset (POR/LVR), LDO and all PAD circuits other than PC13, PC14 and PC15.
Page 49 AT32A403A Series Reference Manual  Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit. When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must be cleared.  Configuring an internal EXINT line as an event mode to generate a wakeup event.
Page 50: Pwc Registers
AT32A403A Series Reference Manual 3.7 PWC registers The peripheral registers can be accessed by words (32 bit) Table 3-1 PW register map and reset values Register abbr. Offset Reset value PWC_CTRL 0x00 0x0000 0000 PWC_CTRLSTS 0x04 0x0000 0000 3.7.1 Power control register (PWC_CTRL) Abbr.
Page 51: Power Control/Status Register (Pwc_Ctrlsts)
AT32A403A Series Reference Manual 3.7.2 Power control/status register (PWC_CTRLSTS) Additional APB cycles are needed to read this register versus a standard APB read. Abbr. Reset value Type Description resd Kept at its default value. Bit 31: 9 Reserved 0x000000 Standby wake-up pin enable...
Page 52: Clock And Reset Manage (Crm)
HICK clock is 48 MHz. Although it is less accurate, its startup time is shorter than the HEXT crystal oscillator. The HICK clock frequency of each device is calibrated by ARTERY for 1% accuracy (25°C) in factory. The factory calibration value is loaded in the HICKCAL[7: 0] bit of the clock control register. The RC oscillator speed may be affected by voltage or temperature variations.
Page 53: System Clock
AT32A403A Series Reference Manual The HICK clock signal is not released until it becomes stable. PLL clock  The HICK or HEXT clock can be used as an input clock source of PLL, and the input clock ranges from 2 M to 16 MHz. The input clock source and multiplication factor must be configured before enabling the PLL.
Page 54: Clock Fail Detector
If a failure is detected on the HEXT clock, the CFD interrupt is generated. Such interrupt is directly linked to CPU NMI. 4.2 Reset 4.2.1 System reset AT32A403A series provides the following system reset sources:  NRST reset: on the external NRST pin  WDT reset: watchdog overflow ...
Page 55: Battery Powered Domain Reset
AT32A403A Series Reference Manual Figure 4-2 System reset circuit Pulse generator (Min 20 µs) NRST CTRL NRST reset Filter WDT reset System WWDT reset reset CPU software reset Low-power management reset POR reset LVR reset standby return reset 4.2.2 Battery powered domain reset Battery powered domain has two specific reset sources: ...
Page 56: Clock Control Register (Crm_Ctrl)
AT32A403A Series Reference Manual 4.3.1 Clock control register (CRM_CTRL) Abbr. Reset value Type Description Kept at its default value. Bit 30: 26 Reserved 0x00 resd PLL clock stable This bit is set by hardware after PLL is ready. Bit 25 PLLSTBL 0: PLL clock is not ready.
Page 57: Clock Configuration Register (Crm_Cfg)
AT32A403A Series Reference Manual High speed internal clock enable This bit is set and cleared by software. It can also be set by hardware when exiting Standby or Deepsleep mode. When a HEXT clock failure occurs. This bit can also be set. When...
Page 58 AT32A403A Series Reference Manual 1: HEXT is divided according to the setting of HEXTDIV. PLL entry clock select Bit 16 PLLRCS 0: HICK clock divided (4MHz) to be PLL entry clock 1: HEXT clock is used as PLL entry clock ADC division The divided PCLK is used as ADC clock.
Page 59: Clock Interrupt Register (Crm_Clkint)
AT32A403A Series Reference Manual 4.3.3 Clock interrupt register (CRM_CLKINT) Abbr. Reset value Type Description resd Kept at its default value. Bit 31: 24 Reserved 0x00 Clock failure detection flag clear Writing 1 by software to clear CFDF. Bit 23 CFDFC...
Page 60: Apb2 Peripheral Reset Register (Crm_Apb2Rst)
AT32A403A Series Reference Manual 0: PLL is not ready. 1: PLL is ready. HEXT stable flag Set by hardware. Bit 3 HEXTSTBLF 0: HEXT is not ready. 1: HEXT is ready. HICK stable flag Set by hardware. Bit 2 HICKSTBLF 0: HICK is not ready.
Page 61 AT32A403A Series Reference Manual TMR8 reset 0: No effect Bit 13 TMR8RST 1: Reset SPI1 reset 0: No effect Bit 12 SPI1RST 1: Reset TMR1 reset 0: No effect Bit 11 TMR1RST 1: Reset ADC2 reset 0: No effect Bit 10...
Page 62: Apb1 Peripheral Reset Register (Crm_Apb1Rst)
AT32A403A Series Reference Manual 4.3.5 APB1 peripheral reset register (CRM_APB1RST) Abbr. Reset value Type Description Kept at its default value. Bit 31:30 Reserved resd DAC reset 0: No effect Bit 29 DACRST 1: Reset PWC reset 0: No effect Bit 28...
Page 63: Apb Peripheral Clock Enable Register (Crm_Ahben)
AT32A403A Series Reference Manual 1: Reset Kept at its default value. Bit 10: 9 Reserved resd TMR14 reset 0: No effect Bit 8 TMR14RST 1: Reset TMR13 reset 0: No effect Bit 7 TMR13RST 1: Reset TMR12 reset 0: No effect...
Page 64: Apb2 Peripheral Clock Enable Register (Crm_Ahb2En)
AT32A403A Series Reference Manual Kept at its default value. Bit 3 Reserved resd SRAM clock enable This bit is used to enable SRAM clock in Sleep or Deepsleep mode. Bit 2 SRAMEN 0: Disabled 1: Enabled DMA2 clock enable 0: Disabled...
Page 65 AT32A403A Series Reference Manual TMR1 clock enable 0: Disabled Bit 11 TMR1EN 1: Enabled ADC2 clock enable 0: Disabled Bit 10 ADC2EN 1: Enabled ADC 1 clock enable 0: Disabled Bit 9 ADC1EN 1: Enabled Kept at its default value.
Page 66: Apb1 Peripheral Clock Enable Register (Crm_Ahb1En)
AT32A403A Series Reference Manual 4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) Abbr. Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. DAC clock enable 0: Disabled Bit 29 DACEN 1: Enabled Power control clock enable...
Page 67: Battery Powered Domain Control Register (Crm_Bpdc)
AT32A403A Series Reference Manual 1: Enabled Kept its default value. Bit 10: 9 Reserved resd TMR14 clock enable 0: Disabled Bit 8 TMR14EN 1: Enabled TMR13 clock enable 0: Disabled Bit 7 TMR13EN 1: Enabled TMR12 clock enable 0: Disabled...
Page 68: Control/Status Register (Crm_Ctrlsts)
AT32A403A Series Reference Manual 11: HEXT/128 Kept at its default value. Bit 7: 3 Reserved 0x00 resd Low speed external crystal bypass 0: Disabled Bit 2 LEXTBYPS 1: Enabled Low speed external oscillator stable Set by hardware after the LEXT is ready.
Page 69: Additional Register1 (Crm_Misc1)
AT32A403A Series Reference Manual 4.3.11 Additional register1 (CRM_MISC1) Abbr. Reset value Type Description Clock output division Set the frequency division of CLKOUT. 0xxx: Clock output 1000: Clock output divided by 2 1001: Clock output divided by 4 1010: Clock output divided by 8...
Page 70: Additional Register3 (Crm_Misc3)
AT32A403A Series Reference Manual 4.3.13 Additional register3 (CRM_MISC3) Abbr. Reset value Type Description Bit 31: 14 Reserved 0x0000 resd Kept at its default value. HEXT division 00: HEXT clock is divided by 2. 01: HEXT clock is divided by 3.
Page 71: Flash Memory Controller (Flash)
AT32A403A Series Reference Manual 5 Flash memory controller (FLASH) 5.1 Flash memory introduction Flash memory is divided into four parts: main Flash memory, external memory, information block and Flash memory registers.  Main Flash memory is up to 1024 KB, including bank 1 and bank 2.
Page 72: Figure 5-1 External Memory Ciphertext Protection
AT32A403A Series Reference Manual Main Flash memory (256 KB) has only bank 1, including 128 sectors, 2 K per sector. External memory size is up to 16 MB, including 4096 sectors, 4 K per sector. Table 5-3 Flash memory architecture (256 K)
Page 73: Figure 5-2 Reference Circuit For External Memory
AT32A403A Series Reference Manual Figure 5-2 Reference circuit for external memory SPIM_CS SPIM_IO1 SPIM_IO3 DO/DQ1 HOLD#/DQ3 SPIM_SCK SPIM_IO2 WP#/DQ2 SPIM_IO0 DI/DQ0 Table 5-4 Instruction set supported by external memory FLASH_SELECT Instruction Code Description register config. Write Enable 0x06 0x1/0x2 Both 0x1 and 0x2 Flash must support 0x06 instruction...
Page 74: Table 5-5 User System Data Area
AT32A403A Series Reference Manual and low byte are all 0xFF), the system data loader will issue a system data error flag (USDERR) and the corresponding system data and their inverse codes are forced 0xFF. Note: The update of the contents in the user system data area becomes effective only after a system reset.
Page 75: Flash Memory Operation
AT32A403A Series Reference Manual Note: Switching from 1 to 0 is valid only when the security library is disabled. [15: 8] nEOPB0[7:0]: Inverse code of EOPB0[7:0] [31: 16] Reserved [7: 0] Data2[7: 0]: User data 2 [15: 8] nData2[7: 0]: Inverse code of Data2[7: 0]...
Page 76: Erase Operation
AT32A403A Series Reference Manual 5.2.2 Erase operation Erase operation must be done before programming. Flash memory erase includes mass erase and sector erase. Sector erase Any sector in the Flash memory can be erased with sector erase function. Below should be followed during erase: ...
Page 77: Figure 5-4 Flash Memory Bank Erase Process
AT32A403A Series Reference Manual The following process is recommended: Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming  operation in progress; Set the BANKERS and ERSTR bits in the FLASH_CTRLx register to enable bank erase;...
Page 78: Programming Operation
AT32A403A Series Reference Manual 5.2.3 Programming operation The Flash memory can be programmed with 32 bits, 16 bits or 8 bits at a time. The following process is recommended:  Check the OBF bit in the FLASH_STSx register to confirm that there is no other programming operation in progress;...
Page 79: Read Operation
AT32A403A Series Reference Manual 5.2.4 Read operation Flash memory can be accessed through AHB bus of the CPU. 5.3 External memory operation External memory has the same operation method as that of Flash memory, including read, unlock, erase and programming except that the external memory only supports 32-bit and 16-bit operations, rather than 8 bits.
Page 80: Programming Operation
AT32A403A Series Reference Manual Figure 5-6 System data area erase process Start Check the OBF bit in FLASH_STS OBF = 0? Set USDERS = 1 and ERSTR =1 in FLASH_CTRL Check the OBF bit in FLASH_STS OBF = 0 ? Read ODF bit in FLASH_STS 5.4.3...
Page 81: Read Operation
AT32A403A Series Reference Manual Figure 5-7 System data area programming process Start Check the OBF bit in FLASH_STS OBF = 0? Set the USDPRGM bit = 1 in FLASH_CTRL Write word/half-word (32bits/16 bits) data Check the OBF bit in FLASH_STS...
Page 82: Access Protection
AT32A403A Series Reference Manual 5.5.1 Access protection When the contents in the nFAP and FAP byte are 0xFF, the Flash memory will activate access protection after a system reset. In this case, only the Flash program is allowed to read Flash memory data. This read operation is not permitted in debug mode or by booting from non-Flash memory.
Page 83 AT32A403A Series Reference Manual Advantages of security library: Security library is protected by codes so that solution providers can program core algorithm into this area; Security library cannot be read or deleted (including ISP/IAP/SWD) but only executed unless code defined by the solution provider is keyed in;...
Page 84: Flash Memory Registers
AT32A403A Series Reference Manual 5.7 Flash memory registers Table 5-7 lists Flash register map and their reset values. These peripheral registers must be accessed by words (32 bits). Table 5-7 Flash memory register map and reset value Register Offset Reset value...
Page 85: Flash User System Data Unlock Register (Flash_Usd_Unlock)
AT32A403A Series Reference Manual 5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) Abbr. Reset value Type Description Bit 31: 0 USD_UKVAL 0xXXXX XXXX wo User system data unlock key value Note: All these bits are write-only, and return 0 when being read.
Page 86: Flash Address Register (Flash_Addr)
AT32A403A Series Reference Manual User system data erase Bit 5 USDERS It indicates the user system data erase. User system data program Bit 4 USDPRGM It indicates the user system data program. Bank erase Bit 2 BANKERS It indicates bank erase operation.
Page 87: Flash Status Register2 (Flash_Sts2)
AT32A403A Series Reference Manual 5.7.10 Flash status register2 (FLASH_STS2) Only used in Flash memory bank 2. Abbr. Reset value Type Description Bit 31: 6 Reserved 0x0000000 resd Kept at its default value Operation done flag This bit is set by hardware when Flash memory Bit 5 operations (program/erase) is completed.
Page 88: Flash Address Register2 (Flash_Addr2)
AT32A403A Series Reference Manual 5.7.12 Flash address register2 (FLASH_ADDR2) Only used in Flash memory bank 2. Abbr. Reset value Type Description Flash address Bit 31: 0 0x0000 0000 Select the address of sectors to be erased in sector erase operation.
Page 89: Flash Address Register3 (Flash_Addr3)
AT32A403A Series Reference Manual 1: Interrupt is enabled. Kept at its default value Bit 9,8 Reserved resd Operation lock This bit is set by default, indicating that Flash memory is protected against operations. This bit is cleared by Bit 7...
Page 90: Flash Security Library Status Register1 (Slib_Sts1)
AT32A403A Series Reference Manual 5.7.20 Flash security library status register1 (SLIB_STS1) Only used in Flash security library. Abbr. Reset value Type Description Security library end sector 0: Sector 0 1: Sector 1 Bit 31: 22 SLIB_ES 0x000 2: Sector 2 …...
Page 91: Security Library Password Setting Register (Slib_Set_Pwd)
AT32A403A Series Reference Manual 5.7.23 Security library password setting register (SLIB_SET_PWD) Only used for Flash security library password setting. Abbr. Reset value Type Description Security library password setting value Note: This register can be written only after unlocking security library lock. It is used to set up the startup...
Page 92: Flash Crc Check Control Register (Flash_Crc_Ctrl)
AT32A403A Series Reference Manual 5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) Only used in main Flash memory. Abbr. Reset value Type Description CRC start Set this bit to enable user code or security library code Bit 31 CRC_STRT CRC calibration. This bit is cleared automatically after the hardware enables CRC.
Page 93: General-Purpose I/Os (Gpios)
AT32A403A Series Reference Manual 6 General-purpose I/Os (GPIOs) 6.1 Introduction AT32A403A supports up to 80 bidirectional I/O pins, which are grouped as five categories, namely PA, PB, PC, PD and PE. Each of the GPIO group provides up to 16 I/O pins that feature communication, control and data collection.
Page 94: Gpio Reset Status
AT32A403A Series Reference Manual 6.2.2 GPIO reset status After power-on or system reset, all pins are configured as floating input mode except JATG-related pins. JTAG pin configuration are as follows:  PA15/JTDI, PA13/JTMS and PB4/JNTRST in pull-up input mode; PA14/JTCK in pull-down input mode;...
Page 95: Gpio Registers
AT32A403A Series Reference Manual 6.3 GPIO registers Table 6-1 lists GPIO register map and their reset values. These peripheral registers must be accessed by words (32 bits). Table 6-1 GPIO register map and reset values Register Offset Reset value GPIOx_CFGLR...
Page 96: Gpio Configuration Register High (Gpiox_Cfghr) (A
AT32A403A Series Reference Manual 6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..E) Abbr. Reset value Type Description GPIOx function configuration (y=8~15) In input mode (IOMCy[1: 0]=00): 00: Analog mode Bit 31: 30 01: Floating input (reset state) Bit 27: 26 Bit 23: 22...
Page 97: Gpio Set/Clear Register (Gpiox_Scr) (X=A..e
AT32A403A Series Reference Manual 6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..E) Abbr. Reset value Type Description GPIOx clear bit The corresponding ODT register bits are cleared by writing “1” to these bits. Writing 0 has no effect on the ODT register bits, which is equivalent to ODT register bit...
Page 98: Multiplexed Function I/Os (Iomux)
AT32A403A Series Reference Manual 7 Multiplexed function I/Os (IOMUX) 7.1 Introduction AT32A403A support up to 80 bi-directional I/O pins, which are grouped as five categories, namely PA, PB, PC, PD and PE. Each of the GPIO group provides up to 16 I/O pins that feature communication, control and data collection.
Page 99: Mux Input Configuration
AT32A403A Series Reference Manual 7.2.2 MUX Input configuration When I/O ports are configured as multiplexed function input:  Get I/O pin state by reading input data registers  The pin be configured as floating input, pull-up or pull-down input ...
Page 100: Hardware Preemption
AT32A403A Series Reference Manual 7.2.4.1 Hardware preemption Certain pins are occupied by specific hardware functions regardless of the GPIO configuration. Table 7-3 Hardware preemption Enable bit Description PWC_CTRLSTS[8] =1 Once enabled, PA0 pin acts as WKUP function of PWC. DAC_CTRL[2] =1 Once enabled, PA4 pin acts as DAC1 analog channel.
Page 101: Multiplexed Input/Output (Iomux)
AT32A403A Series Reference Manual 7.3 Multiplexed input/output (IOMUX) IP name IP multiplexed pin GPIO configuration CAN1 CAN1_GMUX CAN_TX: push-pull multiplexed output 00: RX/PA11, TX/PA12 CAN_RX:floating input 10: RX/ PB8, TX/ PB9 or pull-up input 11: RX/ PD0, TX/ PD1 Others: Unused...
Page 102 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration 1: ADC2 preempted group conversion external trigger is connected to TMR8 channel 4 ADC2_ETO_GMUX 0: ADC2 ordinary group conversion external trigger is connected to EXINT11 1: ADC2 ordinary group conversion external trigger is...
Page 103 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration Others: Unused TMR4 TMR4_MUX 0: CH1/PB6, CH2/PB7, CH3/PB8, CH4/PB9 1: CH1/PD12, CH2/PD13, CH3/PD14 CH4/PD15 TMR4_GMUX 0000: CH1/PB6 CH2/PB7 CH3/PB8 CH4/PB9 0001: CH1/PD12 CH2/PD13 CH3/PD14 CH4/PD15 Others: Unused TMR5 TMR5CH4_MUX...
Page 104 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration USART3 USART3_MUX 00: TX/PB10,RX/PB11,CK/PB12,CTS/PB13,RTS/PB14 01:TX/PC10,RX/PC11,CK/PC12,CTS/PB13,RTS/PB14 10: Unused 11:TX/PD8,RX/PD9,CK/PD10,CTS/PD11,RTS/PD12 USART3_GMUX 0000: TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 0001: TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 0011: TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12 Others: Unused...
Page 105 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration 0000: SCL/PA8 SDA/PC9 SMBA/PA9 0001:SCL/PA8 SDA/PB4 SMBA/PA9 Others: Unused SPI1 SPI1_MUX SPIx_SCK 00: CS/PA4,SCK/PA5,MISO/PA6,MOSI/PA7 MCK/PB0 . In master mode, it is used as push-pull 01:CS/PA15,SCK/PB3,MISO/PB4,MOSI/PB5 MCK/PB0 multiplexed output; 10:CS/PA4,SCK/PA5,MISO/PA6,MOSI/PA7 MCK/PB6...
Page 106 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration SDIO2 SDIO2_MUX Configured as push- pull multiplexed output 00: D0/PC0 D1/PC1 D2/PC2 D3/PC3 D4/PA4 D5/PA5 D6/PA6 D7/PA7 CK/PC4 CMD/PC5 SDIO_CMD 01: D0/PA4 D1/PA5 D2/PA6 D3/PA7 CK/PC4 CMD/PC5 Configured as push-...
Page 107 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration pull multiplexed output XMC_GMUX XMC_NOE 0000: NEW/PD5 D0/PD14 D1/PD15 D2/PD0 D3/PD1 D4/PE7 D5/PE8 D6/PE9 D7/PE10 D13/PD8 NOE/PD4 Configured as push- pull multiplexed output 0001: NEW/PD2 D0/PB14 D1/PC6 D2/PC11 D3/PC12...
Page 108 AT32A403A Series Reference Manual IP name IP multiplexed pin GPIO configuration input TAMPER_RTC NA Refer to 7.2.4.1 CLKOUT Configured as push- pull multiplexed output EXINT input Configured as floating line input or pull-up or pull- down input Note: “NA” indicates no pin multiplexed function. Refer to the Datasheet for information on IP pin multiplexed function.
Page 109: Iomux Registers
AT32A403A Series Reference Manual 7.4 IOMUX registers Table 7-5 shows IOMUX register map and their reset values. These peripheral registers must be accessed by words (32 bits). Table 7-5 IOMUX register map and reset value Register Offset Reset value IOMUX_EVTOUT...
Page 110: Iomux Remap Register (Iomux_Remap)
AT32A403A Series Reference Manual 7.4.2 IOMUX remap register (IOMUX_REMAP) Abbr. Reset value Type Description SPI1 IO multiplexing Bit 31 SPI1_MUX Refer to bit 0 SPI1_MUX[1:0] for more details. Kept at its default value. Bit 30 Reserved resd Kept at its default value.
Page 111 AT32A403A Series Reference Manual 0: ADC1 external trigger preempted conversion is connected to EXINT15. 1: ADC1 external trigger preempted conversion is connected to TMR8 channel 4. TMR5 channel4 multiplexing Select internal map for TMR5 channel 4. Bit 16 TMR5CH4_MUX 0: TMR5_CH4 is connected to PA3.
Page 112: Iomux External Interrupt Configuration Register1 (Iomux_Exintc1)
AT32A403A Series Reference Manual 11: TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12 USART2 IO multiplexing Select IO multiplexing for USART2. Bit 3 USART2_MUX 0: CTS/PA0, RTS/PA1, TX/PA2, RX/PA3 and CK/PA4 1: CTS/PD3, RTS/PD4, TX/PD5, RX/PD6 and CK/PD7 USART1 IO multiplexing Select USART1 IO multiplexing...
Page 113: Iomux External Interrupt Configuration Register3 (Iomux_Exintc3)
AT32A403A Series Reference Manual 0001: GPIOB pin0 0010: GPIOC pin0 0011: GPIOD pin0 0100: GPIOE pin0 Others: Reserved. 7.4.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value.
Page 114: Iomux External Interrupt Configuration Register4 (Iomux_Exintc4)
AT32A403A Series Reference Manual 0100: GPIOE pin11 Others: Reserved. EXINT10 input source configuration Select the input source for EXINT10 external interrupt. 0000: GPIOA pin10 0001: GPIOB pin10 Bit 11: 8 EXINT10 0x0000 0010: GPIOC pin10 0011: GPIOD pin10 0100: GPIOE pin10 Others: Reserved.
Page 115: Iomux Remap Register2 (Iomux_Remap2)
AT32A403A Series Reference Manual 0100: GPIOE pin13 Others: Reserved. EXINT12 input source configuration Select the input source for EXINT12 external interrupt. 0000: GPIOA pin12 0001: GPIOB pin12 Bit 3: 0 EXINT12 0x0000 0010: GPIOC pin12 0011: GPIOD pin12 0100: GPIOE pin12 Others: Reserved.
Page 116: Iomux Remap Register4 (Iomux_Remap4)
AT32A403A Series Reference Manual 7.4.9 IOMUX remap register4 (IOMUX_REMAP4) Abbr. Reset value Type Description Bit 31: 20 Reserved 0x000 resd Kept at its default value. TMR5 channel4 general multiplexing Select TMR5 channel4 general multiplexing Bit 19 TMR5CH4_GMUX 0: TMR5_CH4 is connected to PA3.
Page 117: Iomux Remap Register6 (Iomux_Remap6)
AT32A403A Series Reference Manual Others: Unused. SPI3 IO general multiplexing Select IO multiplexing for SPI3. 0000: CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5 MCK/PC7 0001: CS/PA4, SCK/PC10, MISO/PC11, MOSI/PC12 MCK/PC7 Bit 27: 24 SPI3_GMUX 0010: CS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5 MCK/PB10 0011: CS/PA4, SCK/PC10, MISO/PC11, MOSI/PC12...
Page 118 AT32A403A Series Reference Manual Select IO multiplexing for USART3. 0000: TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14 0001: TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14 0011: TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12 Others: Unused USART2 IO general multiplexing Select IO multiplexing for USART2. 0000: CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4...
Page 119: Iomux Remap Register7 (Iomux_Remap7)
AT32A403A Series Reference Manual 7.4.12 IOMUX remap register7 (IOMUX_REMAP7) Abbr. Reset value Type Description Bit 31: 28 Reserved resd Kept at its default value. XMC NADV IO general multiplexing Select whether to use XMC_NADV signal. 0: XMC_NADV is connected to the corresponding pin (by...
Page 120 AT32A403A Series Reference Manual multiplexing Select external trigger input for ADC1 ordinary conversion. 0: ADC1 external trigger ordinary conversion is connected to EXINT11 1: ADC1 external trigger ordinary conversion is connected to TMR8_TRGO ADC1 External trigger preempted conversion general multiplexing Select external trigger input for ADC1 preempted conversion.
Page 121: Iomux Remap Register8 (Iomux_Remap8)
AT32A403A Series Reference Manual 7.4.13 IOMUX remap register8 (IOMUX_REMAP8) Abbr. Reset value Type Description UART8 IO general multiplexing Select IO multiplexing for UART8. 0000: TX/PE1 RX/PE0 Bit 31: 28 UART8_GMUX 0001: TX/PC2 RX/PC3 Others: Unused UART7 IO general multiplexing Select IO multiplexing for UART7.
Page 122: External Interrupt/Event Controller (Exint)
AT32A403A Series Reference Manual 8 External interrupt/Event controller (EXINT) 8.1 EXINT introduction EXINT consists of 19 interrupt lines EXINT_LINE[18:0], each of which can generate an interrupt or event by edge detection trigger or software trigger. EXINT can enable or disable an interrupt or event...
Page 123: Exint Registers
AT32A403A Series Reference Manual  Generate software trigger by setting EXINT_SWTRG register (This is applied to only software trigger interrupt) Note: To change the interrupt source configuration, the EXINT_INTEN and EXINT_EVTEN registers should be disabled before starting interrupt initialization procedures.
Page 124: Polarity Configuration Register2 (Exint_ Polcfg2)
AT32A403A Series Reference Manual 8.3.4 Polarity configuration register2 (EXINT_ POLCFG2) Abbr. Reset value Type Description Bit 31: 19 Reserved 0x000 resd Forced to 0 by hardware. Falling edge event configuration bit on line x These bits are used to select falling edge to trigger an interrupt and event on line x.
Page 125: Dma Controller (Dma)
AT32A403A Series Reference Manual 9 DMA controller (DMA) 9.1 Introduction Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of enhancing system performance and reducing the generation of interrupts. There are two DMA controllers in the microcontroller. Each controller contains 7 DMA channels. Each channel manages memory access requests from one or more peripherals.
Page 126: Function Overview
AT32A403A Series Reference Manual 9.3 Function overview 9.3.1 DMA configuration 1. Set the peripheral address in the DMA_CxPADD register The initial peripheral address for data transfer remains unchanged during transmission. 2. Set the memory address in the DMA_CxMADDR register The initial memory address for data transfer remains unchanged during transmission.
Page 127: Arbiter
AT32A403A Series Reference Manual 9.3.3 Arbiter When several channels are enabled simultaneously, the arbiter will restart arbitration after full data transfer by the master controller. The channel with very high priority waits until the channel of the master controller has completed data transfers before taking control of it. The master controller will re-arbitrate to serve other channels as long as the channel completes a single transfer based on the master controller priority.
Page 128: Errors
AT32A403A Series Reference Manual Figure 9-4 PWIDTH: half-word, MWIDTH: word AHB Read Sequence AHB Write Sequence HW3 HW2 HW1 HW0 W3 W2 W1 W0 word2 word0 word3 word1 Figure 9-5 PWIDTH: word, MWIDTH: byte AHB Read Sequence AHB Write Sequence...
Page 129: Table 9-3 Dma1 Requests For Each Channel
AT32A403A Series Reference Manual Table 9-3 DMA1 requests for each channel Periphe Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 rals ADC1 ADC1 SPI/I SPI1/I2S1_RX SPI1/I2S1_TX SPI2/I2S2_RX SPI2/I2S2_TX USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX...
Page 130: Flexible Dma Request Mapping
AT32A403A Series Reference Manual 9.3.8 Flexible DMA request mapping In flexible request mapping mode (DMA_FLEX_EN = 1), the request source of each channel is programmed by CHx_SRC [x=1~7]. For example, to specify DMA channel 1 as USART3_TX, and channel 3 as USART3_RX, and others are unused, then it is necessary that DMA_FLEX_EN=1, CH1_SRC=30, CH3_SRC=29 and CH[2/4/5/6/7]_SRC=0.
Page 131: Dma Registers
AT32A403A Series Reference Manual reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved...
Page 132: Dma Interrupt Status Register (Dma_Sts)
AT32A403A Series Reference Manual DMA_C6DTCNT 0x70 0x0000 0000 DMA_C6PADDR 0x74 0x0000 0000 DMA_C6MADDR 0x78 0x0000 0000 DMA_C7CTRL 0x80 0x0000 0000 DMA_C7DTCNT 0x84 0x0000 0000 DMA_C7PADDR 0x88 0x0000 0000 DMA_C7MADDR 0x8C 0x0000 0000 DMA_SRC_SEL0 0xA0 0x0000 0000 DMA_SRC_SEL1 0xA4 0x0000 0000 Note: In the following registers, all bits related to channel 6 and channel 7 are not relevant for DMA 2 fixed request mapping since it has only 5 channels.
Page 133 AT32A403A Series Reference Manual Channel 5 transfer complete event flag 0: No transfer complete event occurred. Bit 17 FDTF5 1: Transfer complete event occurred. Channel 5 global event flag 0: No transfer error, half transfer or transfer complete Bit 16 event occurred.
Page 134: Dma Interrupt Flag Clear Register (Dma_Clr)
AT32A403A Series Reference Manual Channel 1 transfer complete event flag 0: No transfer complete event occurred. Bit 1 FDTF1 1: Transfer complete event occurred. Channel 1 global event flag 0: No transfer error, half transfer or transfer complete Bit 0 event occurred.
Page 135 AT32A403A Series Reference Manual Channel 4 half transfer flag clear Bit 14 HDTFC4 rw1c 0: No effect 1: Clear the HDTF4 flag in the DMA_STS register Channel 4 transfer complete flag clear Bit 13 FDTFC4 rw1c 0: No effect 1: Clear the FDTF4 flag in the DMA_STS register...
Page 136 AT32A403A Series Reference Manual 9.4.3 DMA channelx configuration register (DMA_CxCTRL) (x = 1… 7) Abbr. Reset value Type Description Bit 31: 15 Reserved 0x00000 resd Kept at its default value. Memory to memory mode 0: Disabled Bit 14 1: Enabled.
Page 137: Dma Channelx Number Of Data Register (Dma_Cxdtcnt) (X = 1
AT32A403A Series Reference Manual 9.4.4 DMA channelx number of data register (DMA_CxDTCNT) (x = 1… 7) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Number of data to transfer The number of data to transfer is from 0x0 to 0xFFFF.
Page 138: Channel Source Register1 (Dma_Src_ Sel1)
AT32A403A Series Reference Manual 9.4.8 Channel source register1 (DMA_SRC_SEL1) Abbr. Reset value Type Description Bit 31: 25 Reserved 0x00 resd Kept at its default value. DMA flexible request mapping enable 0: DMA fixed request mapping mode Bit 24 DMA_FLEX_EN 1: DMA flexible request mapping mode...
Page 139: Crc Calculation Unit (Crc)
AT32A403A Series Reference Manual 10 CRC calculation unit (CRC) 10.1 CRC introduction The Cyclic Redundancy Check (CRC) is an independent peripheral with CRC check feature. It follows CRC32/MPEG-2 standard. The CRC_CTRL register is used to select output data reverse (word, REVOD=1) or input data reverse (byte, REVID=01;...
Page 140: Crc Registers
AT32A403A Series Reference Manual  Output data toggle. Select whether to perform word toggle before output CRC value through the REVOD bit in the CRC_CTRL register CRC-32/MPEG-2 parameters  Generator polynominal: 0x4C11DB7 that is, �� + �� + �� + ��...
Page 141: Control Register (Crc_Ctrl)
AT32A403A Series Reference Manual 10.3.3 Control register (CRC_CTRL) Abbr. Reset value Type Description Bit 31: 8 Reserved 0x000000 resd Kept at its default value. Reverse output data Set and cleared by software. This bit is used to control whether to reverse output data.
Page 142: C Interface
AT32A403A Series Reference Manual 11 I C interface 11.1 I C introduction C (inter-integrated circuit) bus interface manages the communication between the microcontroller and serial I C bus. It supports master and slave modes, with up to 400 Kbit/s of communication speed.
Page 143: I 2 C Interface
AT32A403A Series Reference Manual 11.4 I C interface Figure 11-2 shows the block diagram of I C function Figure 11-2 I2C function block diagram Comparator Data Control Shift Register APB Interface Control register Data Clock OADDR Register Control Status I2C_DMA_req_tx...
Page 144 AT32A403A Series Reference Manual  In 10-bit mode ― Only match OADDR1 Support special slave address:  Broadcast call address (0b0000000x): This address is enabled when GCAEN=1.  SMBus device default address (0b1100001x): This address is enabled for SMBus address resolution protocol in SMBus device mode.
Page 145: C Slave Communication Flow
AT32A403A Series Reference Manual 11.4.1 I C slave communication flow Initialization Enable I C peripheral clock, and configure the clock-related bits in the I2C_CTRL2 register for a correct timing, and then wait for I C master to send a Start condition.
Page 146: Figure 11-4 Transfer Sequence Of Slave Receiver
AT32A403A Series Reference Manual EV2: When the data is written to DT register, it is directly moved to the shift register, and SCL bus is released. The TDBE is still set 1 at this time. EV3: At this point, the DT register is empty but the shift register is not. Writing to the DT register will clear the TDBE bit.
Page 147: C Master Communication Flow
AT32A403A Series Reference Manual EV3: After receiving the Stop condition from the master, STOPF=1. Read STS1 and then write to CTRL1 register will clear the event. End of communication. 11.4.2 I C master communication flow Initialization Program input clock to generate correct timing through the CLKFREQ bit in the I2C_CTRL2 register;...
Page 148: Figure 11-5 Transfer Sequence Of Master Transmitter
AT32A403A Series Reference Manual Master transmitter Figure 11-5 Transfer sequence of master transmitter Example : I2C Master transfer N bytes to I2C Slave . 7-bit address Address Data1 Data2 DataN Stretch Stretch TDBE 10-bit address Address Head Address Stretch Stretch...
Page 149: Figure 11-6 Transfer Sequence Of Master Receiver
AT32A403A Series Reference Manual EV4: At this point, the DT register is empty but the shift register is full. Writing to the DT register will clear the TDBE bit. The TDBE bit is set only after the second-to-last byte is sent.
Page 150: Figure 11-7 Transfer Sequence Of Master Receiver When N>2
AT32A403A Series Reference Manual EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV5: 10-bit address head sequence is sent. Read STS1 and write to DT register can clear the ADDRHF bit. EV2: Address is matched successfully (ADDR7F=1). Read STS1 and then STS2 will clear the ADDR7F bit, and the master re-send Start condition (GENSTART=1).
Page 151: Figure 11-8 Transfer Sequence Of Master Receiver When N=2
AT32A403A Series Reference Manual is read. End of communication.  10-bit address mode: Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV5: 10-bit address head sequence is sent. Read STS1 and write to DT register can clear the ADDRHF bit.
Page 152 AT32A403A Series Reference Manual  7-bit address mode: Set MACKCTRL=1 in the I2C_CTRL1 register Generate Start condition (GENSTART=1) EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register. EV2: Address is matched successfully (ADDR7F=1). Clear the ACKEN bit and read STS1 before reading STS2 and clearing ADDR7F bit, the master enters receive state at this time.
Page 153: Figure 11-9 Transfer Sequence Of Master Receiver When N=1
AT32A403A Series Reference Manual Figure 11-9 Transfer sequence of master receiver when N=1 Example : I2C Master receive 1 bytes from I2C Slave . 7-bit address Address Data1 Stretch Stretch RDBF 10-bit address Address Head Address Address Head SCL Stretch...
Page 154: Utilize Dma For Data Transfer
AT32A403A Series Reference Manual 11.4.3 Utilize DMA for data transfer C data transfer can be done using DMA controller. An interrupt is generated by enabling the transfer complete interrupt bit. The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for data transfer.
Page 155 AT32A403A Series Reference Manual another, or even keeping STOP and other parameter monitor. There is no limit for I SMBus transmission speed ranges from 10 kHz to 100 kHz. In contrast,I2C has no minimum requirement, and its maximum speed varies from one mode to another, namely, 100 kHz in standard mode and 400 kHz in fast mode.
Page 156: C Interrupt Requests
AT32A403A Series Reference Manual C(x) = x + x + 1 PEC calculation is enabled when PECEN=1 to check address and data. It becomes invalid when the arbitration is lost. PEC transmission:  Common mode: Set PECTRA=1 after the last TDBE event so that PEC is transferred after the last transmitted byte.
Page 157: I 2 C Registers
AT32A403A Series Reference Manual 11.5 I C registers These peripheral registers must be accessed by word (32 bits). Table 11-1 I C register map and reset value Register Offset Reset value I2C_CTRL1 0x00 0x0000 I2C_CTRL2 0x04 0x0000 I2C_OADDR1 0x08 0x0000...
Page 158: Control Register2 (I2C_Ctrl2)
AT32A403A Series Reference Manual 1: Stop condition is generate. The salve releases the SCL and SDA lines when this bit is set in slave mode. Generate start condition This bit is set or cleared by software. It is cleared when a Start condition is sent.
Page 159: Own Address Register 1 (I2C_Oaddr1)
AT32A403A Series Reference Manual 1: Enabled Event interrupt enable 0: Disabled 1: Enabled An interrupt is generated in the following conditions: – STARTF = 1 (Master mode) – ADDR7F = 1 (Master/slave mode) Bit 9 EVTIEN – ADDRHF= 1 (Master mode) –...
Page 160: Data Register (I2C_Dt)
AT32A403A Series Reference Manual 11.5.5 Data register (I2C_DT) Abbr. Reset value Type Description Kept at its default value Bit 15: 8 Reserved 0x00 resd This field is used to store data received or to be transferred. Transmitter mode: Data transfer starts automatically when a byte is written to the DT register.
Page 161 AT32A403A Series Reference Manual This bit is cleared by software, or by hardware when I2CEN=0. Arbitration lost flag 0: No arbitration lost is detected. 1: Arbitration lost is detected. Bit 9 ARLOST rw0c This bit is cleared by software, or by hardware when I2CEN=0.
Page 162: Status Register 2 (I2C_Sts2)
AT32A403A Series Reference Manual When STRETCH=0 In reception mode, when a new byte (including ACK pulse) is received and the data register is not read yet (RDBF=1) In transmission mode, when a new byte is sent and the data register is not written yet (TDBE=1) The TDC is set under both conditions.
Page 163: Clock Control Register (I2C_ Clkctrl)
AT32A403A Series Reference Manual Transmission mode 0: Slave mode 1: Master mode Bit 0 TRMODE Set by hardware when the GENSTART is set and a Start condition is sent. Cleared by hardware when a Stop condition is detected. 11.5.8 Clock control register (I2C_ CLKCTRL) Abbr.
Page 164: Universal Synchronous/Asynchronous Receiver/Transmitter (Usart)
AT32A403A Series Reference Manual 12 Universal synchronous/asynchronous receiver/transmitter (USART) 12.1 USART introduction The universal synchronous/asynchronous receiver/transmitter (USART) serves an interface for communication by means of various configuration and peripherals with different data formats. It supports asynchronous full-duplex and half-duplex as well as synchronous transfer. With a programmable baud rate generator, USART offers up to 6.25 Mbits/s of baud rate by setting the system frequency and...
Page 165 AT32A403A Series Reference Manual  Programmable communication modes ─ NRZ standard format (Mark/Space) ─ LIN (Local Interconnection Network): ─ IrDA SIR: ─Asynchronous SmartCard protocol defined in ISO7816-3 standard: Support 0.5 or 1.5 stop bits in Smartcard mode ─ RS-232 CTS/RTS (Clear To Send/Request To Send) hardware flow operation ─...
Page 166: Full-Duplex/Half-Duplex Selector
AT32A403A Series Reference Manual 12.2 Full-duplex/half-duplex selector The full-duplex and half-duplex selector enables USART to perform data exchanges with peripherals in full-duplex or half-duplex mode, which is achieved by setting the corresponding registers. In two-wire unidirectional full-duplex mode (by default), TX pin is used for data output, while the RX pin is used for data input.
Page 167: Figure 12-3 Smartcard Frame Format
AT32A403A Series Reference Manual 2. Smartcard mode: Parameters configuration: SCMEN=1, LINEN=0, SLHDEN=0, IRDAEN=0, CLKEN=1, DBN=1, PEN=1, and STOPBN[1: 0]=11. The polarity, phase and pulse number of the clock can be configured by setting the CLKPOL, CLKPHA and LBCP bits (Refer to Synchronous mode for details).
Page 168: Figure 12-6 Silent Mode Using Idle Line Or Address Mark Detection
AT32A403A Series Reference Manual RTS follow control： frame1 frame0 RX pin CTS follow control： frame0 frame1 frame2 TX pin 5. Silent mode Silent mode can be entered by setting RM=1. It is possible to wake up from silent mode by setting WUM=1 (ID match) and WUM=0 (idle bus), respectively.
Page 169: Usart Frame Format And Configuration
AT32A403A Series Reference Manual CK pin (CLKPOL=0 CLKPHA=0) CK pin (CLKPOL=1 CLKPHA=0) CK pin (CLKPOL=0 CLKPHA=1) CK pin (CLKPOL=1 CLKPHA=1) Start TX pin Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop...
Page 170: Dma Transfer Introduction
AT32A403A Series Reference Manual Figure 12-9 Stop bit configuration Clock PEN = 1, Next STOPBN = 00 Data frame Parity bit Start Start 1 Stop bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...
Page 171: Baud Rate Generation
AT32A403A Series Reference Manual DMA transfer in the DMA control register. Data will be loaded from the USART_DT register to the programmed destination after reception request is received by DMA. Configure the total number of bytes to be transferred in the DMA control register.
Page 172: Transmitter
AT32A403A Series Reference Manual 12.7 Transmitter 12.7.1 Transmitter introduction USART transmitter has its individual TEN control bit. The transmitter and receiver share the same baud rate that is programmable. There is a transmit data buffer (TDR) and a transmit shift register in the USART.
Page 173: Receiver
AT32A403A Series Reference Manual 12.8 Receiver 12.8.1 Receiver introduction USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer (RDR) and a receive shift register in the USART.
Page 174: Start Bit And Noise Detection
AT32A403A Series Reference Manual buffer. In non-DMA mode, both FERR and RDBF are set at the same time. The latter will generate an  interrupt. In DMA mode, an interrupt is generated if the ERRIEN. When an overrun error occurs: ...
Page 175: Interrupt Requests
AT32A403A Series Reference Manual  No interrupt is generated in non-DMA mode. However, since the NERR bit is set at the same time as the RDBF bit, the RDBF bit will generate an interrupt. In DMA mode, an interrupt will be issued if the ERRIEN is set.
Page 176: I/O Pin Control
AT32A403A Series Reference Manual 12.10 I/O pin control The following five interfaces are used for USART communication. RX: Serial data input. TX: Serial data output. In single-wire half-duplex and Smartcard mode, the TX pin is used as an I/O for data transmission and reception.
Page 177: Data Register (Usart_Dt)
AT32A403A Series Reference Manual cleared by software. (Option 1: read USART_DT register; Option 2: write “0” to this bit) 0: Data is not received. 1: Data is received. Idle flag This bit is set by hardware when an idle line is detected. It is cleared by software.
Page 178: Control Register1 (Usart_Ctrl1)
AT32A403A Series Reference Manual 12.11.4 Control register1 (USART_CTRL1) Abbr. Reset value Type Description Forced to be 0 by hardware. Bit 31: 14 Reserved 0x00000 resd USART enable 0: USART is disabled. Bit 13 1: USART is enable. Data bit num This bit is used to program the number of data bits.
Page 179: Control Register2 (Usart_Ctrl2)
AT32A403A Series Reference Manual to wake up from mute mode, this bit is cleared by hardware after wake up. When the address match is used to wake up from mute mode, it is cleared by hardware after wake up. When address mismatches, this bit is set by hardware to enter mute mode again.
Page 180: Control Register3 (Usart_Ctrl3)
AT32A403A Series Reference Manual This bit is used to select 11-bit or 10-bit break frame. 0: 10-bit break frame 1: 11-bit break frame Keep at its default value. Bit 4 Reserved resd USART identification Bit 3: 0 Configurable USART ID.
Page 181: Guard Time And Divider Register (Gdiv)
AT32A403A Series Reference Manual 12.11.7 Guard time and divider register (GDIV) Abbr. Reset value Type Description Forced to be 0 by hardware. Bit 31: 16 Reserved 0x0000 resd Smartcard guard time value This field specifies the guard time value. The...
Page 182: Serial Peripheral Interface (Spi)
AT32A403A Series Reference Manual 13 Serial peripheral interface (SPI) 13.1 SPI introduction The SPI interface supports either the SPI protocol or the I S protocol, depending on software configuration. This chapter gives an introduction of the main features and configuration procedure of SPI used as SPI or I 13.2 Function overview...
Page 183: Full-Duplex/Half-Duplex Selector
AT32A403A Series Reference Manual  Programmable clock polarity and phase Programmable data transfer order (MSB-first or LSB-first)   Programmable error interrupt flags (receiver overflow error, master mode error and CRC error)  Programmable transmit data buffer empty interrupt and receive data buffer full interrupt ...
Page 184: Figure 13-3 Single-Wire Unidirectional Receive Only In Spi Master Mode
AT32A403A Series Reference Manual Figure 13-3 Single-wire unidirectional receive only in SPI master mode SPI master SPI slave MISO MISO MOSI MOSI Figure 13-4 Single-wire unidirectional receive only in SPI slave mode SPI master SPI slave MISO MISO MOSI MOSI In master mode, it is necessary to wait until the second-to-last RDBF bit is set and then another SPI_CPK period before disabling the SPI.
Page 185: Chip Select Controller
AT32A403A Series Reference Manual Figure 13-5 Single-wire bidirectional half-duplex mode SPI master SPI slave MISO MISO MOSI MOSI When the SPI is selected for data transmission in single-wire bidirectional half-duplex mode (master or slave), the TDBE bit must be set, and the BF must be 0 before disabling the SPI. The power-saving mode (or disabling SPI system clock) cannot be entered unless the SPI is disabled.
Page 186: Spi_Sck Controller
AT32A403A Series Reference Manual 13.2.4 SPI_SCK controller The SPI protocol adopts synchronous transmission. In master mode with the SPI being as SPI, it is required to generate a communication clock for data reception and transmission on the SPI, and the communication clock should be output to the slave via IO for data reception and transmission.
Page 187: Dma Transfer
AT32A403A Series Reference Manual 13.2.6 DMA transfer The SPI supports write and read operations with DMA. Refer to the following configuration procedure. Special attention should be paid to: when the CRC calculation and check is enabled, the number of data transferred by DMA is configured as the number of the data to be transferred. The number of data read with DMA is configured as the number of the data to be received.
Page 188: Receiver
AT32A403A Series Reference Manual configuration information, go to the Chip select controller chapter for specific chip select mode, check the SPI_SCK controller chapter for information on communication clock, and refer to CRC and DMA transfer chapter to configure CRC and DMA (if necessary). The recommended configuration procedure are as follows.
Page 189: Figure 13-6 Master Full-Duplex Communications
AT32A403A Series Reference Manual MSTEN=1: Master enable SLBEN=0: Full-duplex mode CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling FBN=0: 8-bit frame Master transmit (MOSI): 0xaa, 0xcc, 0xaa Slave transmit (MISO): 0xcc, 0xaa, 0xcc Figure 13-6 Master full-duplex communications...
Page 190: Figure 13-9 Slave Half-Duplex Receive
AT32A403A Series Reference Manual Drive MOSI TDBE flag Transmit buffer empty and BF flag software can write data Half-duplex communication – slave receive Configured as follows: MSTEN=0: Slave enable SLBEN=1: Single line bidirectional mode SLBTD=0: Receive mode CLKPOL=0, CLKPHA=0: SCK idle output low, use the first edge for sampling...
Page 191: Interrupt
AT32A403A Series Reference Manual Master receive: 0xaa, 0xcc, 0xaa Figure 13-11 Master half-duplex receive Sampling MOSI Software needs to read the received data RDBF flag BF flag remains low BF flag 13.2.10 Interrupt Figure 13-12 SPI interrupts RDBF RDBFIE TDBE...
Page 192: Precautions
AT32A403A Series Reference Manual 13.2.12 Precautions The software is required to read the DT register in order to get CRC value at the end of CRC reception. 13.3 I S functional description 13.3.1 I S introduction The I2S can be configured by software as master...
Page 193: S Full-Duplex
AT32A403A Series Reference Manual ─ LSB-aligned standard (right-aligned) ─ PCM standard (long or short frame) S full-duplex   DMA transfer  Main peripheral clock with a fixed frequency of 256x Fs (audio sampling frequency) 13.3.2 I S full-duplex Two extra I2S modules (I2S2EXT and I2S3EXT) are used to support I2S full-duplex mode.
Page 194: Audio Protocol Selector
AT32A403A Series Reference Manual Figure 13-16 I S slave device reception I2S master I2S slave Master device transmission: Set the I2SMSEL bit, and OPERSEL[1:0]=10, the I S will work in master device transmission mode. Figure 13-17 I S master device transmission...
Page 195: I2S_Clk Controller
AT32A403A Series Reference Manual data bits and channel bits through software configuration. Meanwhile, the audio protocol selector manages the WS controller, output or detect the WS signal that meets the protocol requirements.  Select audio protocol by setting the STDSEL bit...
Page 196: Figure 13-19 Ck & Mck Source In Master Mode
AT32A403A Series Reference Manual detailed as follows: When used as I2S master, the SPI can provide communication clock (CK) and main peripheral clock (MCK) shown in Figure 13-13. The CK and MCK are generated by HCLK divider, with the prescaler of the MCK determined by I2SDIV and I2SODD.
Page 197 AT32A403A Series Reference Manual 32000 31887.76 0.35% 31887.76 0.35% 22050 22007.04 0.19% 22007.04 0.19% 16000 16025.64 0.16% 15943.88 0.35% 11025 11042.4 0.16% 11003.52 0.19% 8000 7992.327 0.10% 8012.821 0.16% 96000 97656.25 1.73% 97656.25 1.73% 48000 48828.13 1.73% 48828.13 1.73% 44100 43402.78...
Page 198: Dma Transfer
AT32A403A Series Reference Manual 13.3.6 DMA transfer The SPI supports write and read operations with DMA. Whether used as SPI or I S, read/write request using DMA comes from the same peripheral. As a result, their configuration procedure are the same, described as follows.
Page 199: S Communication Timings
AT32A403A Series Reference Manual ─ I2SDBN, I2SCBN,STDSLE combination: wait for the second-to-last RDBF=1 and one CK period before disabling the I S transmitter configuration procedure:  Configure operation mode selector  Configure audio protocol selector  Configure I2S_SCK controller ...
Page 200: Io Pin Control
AT32A403A Series Reference Manual RDBF RDBFIE TDBE TDBEIE I2S interrupt ERRIE ROERR TUERR 13.3.10 IO pin control The I S needs three pins for transfer operation, namely, the SD, WS and CK. The MCLK pin is also required if need to provide main clock for peripherals. The I...
Page 201: Spi Registers
AT32A403A Series Reference Manual 13.4 SPI registers These peripheral registers must be accessed by words (32 bits). Table 13-2 SPI register map and reset value Register Offset Reset value SPI_CTRL1 0x00 0x0000 SPI_CTRL2 0x04 0x0000 SPI_STS 0x08 0x0002 SPI_DT 0x0C...
Page 202: Spi Control Register2 (Spi_Ctrl2)
AT32A403A Series Reference Manual Software CS internal level This bit is valid only when the SWCSEN is set. It determines the level on the CS pin. Bit 8 SWCSIL In master mode, this bit must be set. 0: Low level...
Page 203: Spi Status Register (Spi_Sts)
AT32A403A Series Reference Manual 0: Disabled 1: Enabled Kept at its default value Bit 4: 3 Reserved resd Hardware CS output enable This bit is valid only in master mode. When this bit is set, the I/O output on the CS pin is low; when this bit is 0, the...
Page 204: Spi Data Register (Spi_Dt)
AT32A403A Series Reference Manual 13.4.4 SPI data register (SPI_DT) Abbr. Reset value Type Description Data value This register controls read and write operations. When Bit 15: 0 0x0000 the data bit is set as 8 bit, only the 8-bit LSB [7: 0] is valid.
Page 205: Spi_I2S Prescaler Register (Spi_I2Sclkp)
AT32A403A Series Reference Manual This bit is valid only when the PCM standard is used. 0: Short frame synchronization 1: Long frame synchronization Kept at its default value Bit 6 Reserved resd S standard select 00: Philips standard 01: MSB-aligned standard (left-aligned)
Page 206: Timer
AT32A403A Series Reference Manual 14 Timer AT32A403A timers include basic timers, general-purpose timers, and advanced-control timers. Please refer to Section 14.1 ~ Section 14.4 for the detailed function modes. All functions of different timers are shown in the following tables.
Page 207: Basic Timer (Tmr6 And Tmr7)
AT32A403A Series Reference Manual 14.1 Basic timer (TMR6 and TMR7) 14.1.1 TMR6 and TMR7 introduction Each of the basic timers (TMR6 and TMR7) includes a 16-bit upcounter and the corresponding control logic, without being connected to external I/Os. They can be used for a basic timing and providing clocks for the digital-to-analog converter (DAC).
Page 208: Figure 14-3 Basic Structure Of A Counter
AT32A403A Series Reference Manual An overflow event is enabled by default. It can be disabled by setting OVFEN=1 in the TMRx_CTRL1 register. The OVFS bit in the TMRx_CTRL1 register is used to select the source of an overflow event, which is, by default, counter overflow or underflow, setting OVFSWTR, reset signal generated by slave mode timer controller in reset mode.
Page 209: Debug Mode
AT32A403A Series Reference Manual 14.1.3.3 Debug mode ® When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops counting when the TMRx_PAUSE bit is set. 14.1.4 TMR6 and TMR7 registers These peripheral registers must be accessed by words (32 bits).
Page 210: Tmr6 And Tmr7 Control Register1 (Tmrx_Ctrl1)
AT32A403A Series Reference Manual 14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1) Abbr. Reset value Type Description Kept at its default value. Bit 15: 8 Reserved 0x00 resd Period buffer enable 0: Period buffer is disabled. Bit 7 PRBEN 1: Period buffer is enabled.
Page 211: Tmr6 And Tmr7 Dma/Interrupt Enable Register (Tmrx_Iden)
AT32A403A Series Reference Manual 14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) Abbr. Reset value Type Description Kept at its default value. Bit 15: 9 Reserved 0x00 resd Overflow event DMA request enable 0: Disabled Bit 8 OVFDEN 1: Enabled Kept at its default value.
Page 212: General-Purpose Timer (Tmr2 To Tmr5)
AT32A403A Series Reference Manual 14.2 General-purpose timer (TMR2 to TMR5) 14.2.1 TMRx introduction The general-purpose timer (TMR2 to TMR5) consists of a 16-bit counter supporting up, down, up/down (bidirectional) counting modes, four capture/compare registers, and four independent channels to achieve input capture and programmable PWM output.
Page 213: Tmrx Functional Overview
AT32A403A Series Reference Manual 14.2.3 TMRx functional overview 14.2.3.1 Counting clock The count clock of TMR2~TMR5 can be provided by the internal clock (CK_INT), external clock (external clock mode A and B) and internal trigger input (ISx) Figure 14-8 Counting clock...
Page 214: Figure 14-10 Block Diagram Of External Clock Mode A
AT32A403A Series Reference Manual If the TMRx_CH2 is used as source of TRGIN, it is necessary to configure channel 1 input filter (C2DF[3:0] in TMRx_CM1 register) and channel 2 input polarity (C2P/C2CP in TMRx_CCTR register); If the TMRx_EXT is used as a source of TRGIN, it is necessary to configure the external signal polarity (ESP in TMRx_STCTRL register), external signal frequency division (ESDIV[1:0] in TMRx_STCTRL) and external signal filter (ESF[3:0] in TMRx_STCTRL register).
Page 215: Figure 14-13 Counting In External Clock Mode B, Pr=0X32, Div=0X0
AT32A403A Series Reference Manual the synchronization circuit. Figure 14-13 Counting in external clock mode B, PR=0x32, DIV=0x0 TMR_CLK CNT_CLK COUNTER ESDIV[1:0] ESF[3:0] 0000 OVFIF Clear Internal trigger input (ISx) Timer synchronization allows interconnection between several timers. The TMR_CLK of one timer can be provided by the TRGOUT signal output by another timer.
Page 216: Counting Mode
AT32A403A Series Reference Manual Figure 14-14 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER DIV[15：0] PR[15：0] OVFIF Clear 14.2.3.2 Counting mode The timer (TMR2 to TMR5) supports several counting modes to meet different application scenarios.
Page 217: Figure 14-18 Counter Timing Diagram With Internal Clock Divided By 4
AT32A403A Series Reference Manual Figure 14-16 Overflow event when PRBEN=0 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Figure 14-17 Overflow event when PRBEN=1 TMR_CLK COUNTER PR[15:0] DIV[15:0] OVFIF Clear Clear Clear Downcounting mode This mode is enabled by setting CMSEL[1:0]=2’b00, OWCDIR=1’b1 in the TMRx_CTRL1 register.
Page 218: Figure 14-19 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32A403A Series Reference Manual Figure 14-19 Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32 TMR_CLK COUNTER PR[15:0] DIV[15:0] TWCMSEL [1：0] OVFIF Clear Clear Clear Encoder interface mode In this mode, the two input (TMRx_CH1 and TMRx_CH2) signals are required. Depending on the level on one input, the counter counts up or down on the edge of the other input signal.
Page 219: Tmr Input Function
AT32A403A Series Reference Manual Table 14-4 Counting direction versus encoder signals C1IFP1 signal C2IFP2 signal Level on opposite signal Active edge (C1IFP1 to C2IFP2, C2IFP2 to C1IFP1) Rising Falling Rising Falling High Down No count No count Count on C1IFP1 only...
Page 220: Figure 14-22 Input/Output Channel 1 Main Circuit
AT32A403A Series Reference Manual Figure 14-22 Input/output channel 1 main circuit C1INSEL TMRx_CH3 edge detector input divider STCI TMRx_CH2 C1DF C1P/C1CP C1IRAW C1IDIV C1EN C1IFP1 C1IN TMRx_CH1 C2IFP1 filter Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL...
Page 221: Tmr Output Function
AT32A403A Series Reference Manual  Set C2P=1’b1, select C1IFP2 falling edge active  Set STIS=3’b101, select the slave mode timer trigger signal as C1IFP1  Set SMSEL=3‘b100: configure the slave mode controller in reset mode  Set C1EN=1’b1 and C2EN=1’b1. Enable channel 1 and input capture After above configuration, the rising edge of channel 1 input signal will trigger the capture and stores the capture value into C1DT register, and it will reset the counter at the same time.
Page 222 AT32A403A Series Reference Manual Output mode Write CxC[1: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this case, the counter value is compared with the value in the TMRx_CxDT register, and the intermediate signal CxORAW is generated according to the output mode selected by CxOCTRL[2: 0], which is sent to IO after being processed by the output control circuit.
Page 223: Figure 14-27 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32A403A Series Reference Manual mode B. The counter only counts only one cycle, and the output signal sends only one pulse. Figure 14-27 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW...
Page 224: Tmr Synchronization
AT32A403A Series Reference Manual Figure 14-30 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer. This is done by setting the PTOS bit in the TMRxCTRL2 register.
Page 225: Figure 14-32 Example Of Reset Mode
AT32A403A Series Reference Manual Figure 14-32 Example of reset mode TMR_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] C1IF1 OVFIF TRGIF Slave mode: Suspend mode In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the trigger input is high and stops as soon as the trigger input is low.
Page 226: Figure 14-35 Master/Slave Timer Connection
AT32A403A Series Reference Manual Figure 14-35 Master/slave timer connection Master Timer Slave Timer MMSEL STIS SMSEL Slave CK_DIV TRGOUT mode Prescaler TMREN C1INC Select C1IFP1 CxORAW C2IFP2 Counter Master mode Input trigger selection selection Using master timer to clock the slave timer: ...
Page 227: Debug Mode
AT32A403A Series Reference Manual  Configure master timer output signal TRGOUT as an overflow event (PTOS[2: 0]=3’b010). The master timer outputs a pulse signal at each counter overflow event, which is used as the counting clock of the slave timer.
Page 228: Control Register1 (Tmrx_Ctrl1)
AT32A403A Series Reference Manual TMRx_C4DT 0x40 0x0000 0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.2.4.1 Control register1 (TMRx_CTRL1) Abbr. Reset value Type Description Kept at its default value. Bit 15: 11 Reserved 0x00 resd Plus Mode Enable This bit is used to enable TMRx plus mode. In this mode, TMRx_CVAL, TMRx_PR and TMRx_CxDT are extended from 16-bit to 32-bit.
Page 229: Control Register2 (Tmrx_Ctrl2)
AT32A403A Series Reference Manual Overflow event enable 0: Enabled Bit 1 OVFEN 1: Disabled TMR enable 0: Disabled Bit 0 TMREN 1: Enabled 14.2.4.2 Control register2 (TMRx_CTRL2) Abbr. Reset value Type Description Kept at its default value. Bit 15: 8...
Page 230: Dma/Interrupt Enable Register (Tmrx_Iden)
AT32A403A Series Reference Manual 0100: f /2, N=6 �� 0101: f /2, N=8 �� 0110: f /4, N=6 �� 0111: f /4, N=8 �� 1000: f /8, N=6 �� 1001: f /8, N=8 �� ...
Page 231: Interrupt Status Register (Tmrx_Ists)
AT32A403A Series Reference Manual 1: Enabled Channel 3 DMA request enable 0: Disabled Bit 11 C3DEN 1: Enabled Channel 2 DMA request enable 0: Disabled Bit 10 C2DEN 1: Enabled Channel 1 DMA request enable 0: Disabled Bit 9 C1DEN...
Page 232: Software Event Register (Tmrx_Swevt)
AT32A403A Series Reference Manual 0: No trigger event occurs 1: Trigger event is generated. Trigger event: an active edge is detected on TRGIN input, or any edge in suspend mode. Kept at its default value resd Bit 5 Reserved Channel 4 interrupt flag...
Page 233: Channel Mode Register1 (Tmrx_Cm1)
AT32A403A Series Reference Manual 1: Generate an overflow event. 14.2.4.7 Channel mode register1 (TMRx_CM1) Output compare mode: Abbr. Reset value Type Description Channel 2 output switch enable Bit 15 C2OSEN Channel 2 output control Bit 14: 12 C2OCTRL Channel 2 output buffer enable...
Page 234 AT32A403A Series Reference Manual Channel 1 output enable immediately In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event. Bit 2 C1OIEN 0: Need to compare the CVAL with C1DT before generating an output 1: No need to compare the CVAL and C1DT.
Page 235: Channel Mode Register2 (Tmrx_Cm2)
AT32A403A Series Reference Manual 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’ Channel 1 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C1EN=’0’:...
Page 236: Channel Control Register (Tmrx_Cctrl)
AT32A403A Series Reference Manual Channel 3 digital filter Bit 7: 4 C3DF Channel 3 input divider Bit 3: 2 C3IDIV Channel 3 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C3EN=’0’:...
Page 237: Counter Value (Tmrx_Cval)
AT32A403A Series Reference Manual Table 14-6 Standard CxOUT channel output control bit CxEN bit CxOUT output state Output disabled (CxOUT=0, Cx_EN=0) CxOUT = CxORAW + polarity, Cx_EN=1 Note: The state of the external I/O pins connected to the standard CxOUT channel depends on the CxOUT channel state and the GPIO and IOMUX registers.
Page 238: Channel 3 Data Register (Tmrx_C3Dt)
AT32A403A Series Reference Manual Channel 2 data register When the channel 2 is configured as input mode: The C2DT is the CVAL value stored by the last channel 2 input event (C1IN) Bit 15: 0 C2DT 0x0000 When the channel 2 is configured as output mode: C2DT is the value to be compared with the CVAL value.
Page 239: Dma Data Register (Tmrx_Dmadt)
AT32A403A Series Reference Manual 00010: TMRx_STCTRL ..14.2.4.18 DMA data register (TMRx_DMADT) Abbr. Reset value Type Description DMA data register read or write operation to the DMADT register accesses the TMR registers at the following address: Bit 15: 0 DMADT...
Page 240: Tmrx Functional Overview
AT32A403A Series Reference Manual Figure 14-39 Block diagram of general-purpose TMR10/11/13/14 Capture Compare CNT counter IN MODE OUT MODE Output1 CH1 edge C1IN(C1IFP1) C1IN DIV C1C 0 C1DT C1C=0 C1DT C1ORAW TMRx_CH1 control C1OUT detector C1IF preload TMRx_DIV CH1 filter...
Page 241: Figure 14-42 Block Diagram Of External Clock Mode A
AT32A403A Series Reference Manual -Set external source TRGIN parameters If the TMRx_CH1 is used as a source of TRGIN, it is necessary to configure channel 1 input filter (C1DF[3:0] in TMRx_CM1 register) and channel 1 input polarity (C1P/C1CP in TMRx_CCTRL register);...
Page 242: Counting Mode
AT32A403A Series Reference Manual Slave controller (STIS=000) (STIS = 001) (STIS = 010) (STIS = 011) TMR9 TMR2_TRGOUT TMR3_TRGOUT TMR10_OC TMR11_OC TMR12 TMR4_TRGOUT TMR5_TRGOUT TMR13_OC TMR14_OC Note: If there is no corresponding timer in a device, the corresponding trigger signal ISx is not present.
Page 243: Tmr Input Function
AT32A403A Series Reference Manual restarts from 0, and generates a counter overflow event, with setting OVFIF=1. If the overflow event is disabled, the counter is no longer reloaded with the prescaler value and period value at a counter overflow event, otherwise, the counter is updated with the prescaler value and period value on an overflow event.
Page 244: Figure 14-48 Input/Output Channel 1 Main Circuit
AT32A403A Series Reference Manual Figure 14-48 Input/output channel 1 main circuit edge detector input divider STCI C1DF C1P/C1CP C1IRAW TMRx_CH1 C1IFP1 C1IN C1IDIV C1EN C2IFP1 filter Capture trigger C1DT_shadow Compare CNT counter Capture C1DT C1DT preload C1OCTRL C1OBEN Overflow event...
Page 245: Tmr Output Function
AT32A403A Series Reference Manual Figure 14-50 PWM input mode configuration example C1C(2'b01) edge detector STCI C1P=0 C1DF C1IF C1IRAW C1EN Capture C1DT C1IFP1(pos) C1IN Capture trigger C1CP=0 filter C2IFP1 SMSEL(3'b110) (CH1 period) STIS(3'b101) Trigger mode C1INC CNT counter Hang reset...
Page 246 AT32A403A Series Reference Manual when TMRx_C1DT>TMRx_CVAL, otherwise, it is low; In downcounting mode, C1ORAW outputs low when TMRx_C1DT<TMRx_CVAL, otherwise, it is high. To use PWM mode A, the following procedures are recommended: - Set PWM periods through TMRx_PR register - Set PWM duty cycles through TMRx_CxD - Select PWM mode A by setting CxOCTRL=3’b110 in the TMRx_CM1/CM2 register...
Page 247: Figure 14-53 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32A403A Series Reference Manual Figure 14-53 C1ORAW toggles when counter value matches the C1DT value TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL [2：0] C1DT[15：0] C1ORAW Figure 14-54 Upcounting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW C1DT[15：0]...
Page 248: Tmr Synchronization
AT32A403A Series Reference Manual 14.3.3.5 TMR synchronization TMR9 and TMR12 are linked together internally for timer synchronization. Slave timer is selected by setting the SMSEL[2: 0] bit. Slave mode: Reset mode The counter and its prescaler can be reset by a selected trigger signal. An overflow event is generated when OVFS=0.
Page 249: Debug Mode
AT32A403A Series Reference Manual Figure 14-58 Example of trigger mode TMR_CLK CI1F1 TMR_EN COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] OVFIF Please refer to section 14.2.3.5 for more information on timer synchronization. 14.3.3.6 Debug mode When the microcontroller enters debug mode (Cortex -M4F core halted), the TMRx counter stops ®...
Page 250: Control Register1 (Tmrx_Ctrl1)
AT32A403A Series Reference Manual 14.3.4.1 Control register1 (TMRx_CTRL1) Abbr. Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at its default value Clock divider This field is used to define the relationship between digital filter sampling frequency (...
Page 251: Slave Timer Control Register (Tmrx_Stctrl)
AT32A403A Series Reference Manual 14.3.4.2 Slave timer control register (TMRx_STCTRL) Abbr. Reset value Type Description Bit 15:7 Reserved 0x000 resd Kept at its default value Subordinate TMR input selection This field is used to select the subordinate TMR input. 000: Internal selection 0 (IS0)
Page 252: Interrupt Status Register (Tmrx_Ists)
AT32A403A Series Reference Manual 14.3.4.4 Interrupt status register (TMRx_ISTS) Abbr. Reset value Type Description Kept at its default value. Bit 15: 11 Reserved 0x00 resd Channel 2 recapture flag Bit 10 C2RF rw0c Please refer to C1RF description. Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF=1.
Page 253: Channel Mode Register1 (Tmrx_Cm1)
AT32A403A Series Reference Manual This bit is set by software to generate an overflow event. 0: No effect 1: Generate an overflow event. 14.3.4.6 Channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits.
Page 254 AT32A403A Series Reference Manual 1: Buffer function of TMRx_C1DT is enabled. The value to be written to the TMRx_C1DT is stored in the buffer register, and can be sent to the TMRx_C1DT register only on an overflow event. Channel 1 output enable immediately In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event.
Page 255: Channel Control Register (Tmrx_Cctrl)
AT32A403A Series Reference Manual 00: No divider. An input capture is generated at each active edge. 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’...
Page 256: Counter Value (Tmrx_Cval)
AT32A403A Series Reference Manual 14.3.4.8 Counter value (TMRx_CVAL) Abbr. Reset value Type Description Bit 15: 0 CVAL 0x0000 Counter value 14.3.4.9 Division value (TMRx_DIV) Abbr. Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1).
Page 257: Tmr10, Tmr11, Tmr13 And Tmr14 Registers
AT32A403A Series Reference Manual 14.3.5 TMR10, TMR11, TMR13 and TMR14 registers These peripheral registers must be accessed by words (32 bits). All TMRx register are mapped into a 1-bit addressable space. Table 14-10 TMR register map and reset value 10/11/13/14...
Page 258: Control Register1 (Tmrx_Ctrl1)
AT32A403A Series Reference Manual 14.3.5.1 Control register1 (TMRx_CTRL1) Abbr. Reset value Type Description Bit 15: 10 Reserved 0x00 resd Kept at its default value Clock divider This field is used to define the relationship between digital filter sampling frequency (...
Page 259: Software Event Register (Tmrx_Sw Evt)
AT32A403A Series Reference Manual If the channel 1 is configured as input mode: This bit is set by hardware on a capture event. It is cleared by software or read access to the TMRx_C1DT 0: No capture event occurs 1: Capture event is generated If the channel 1 is configured as output mode: This bit is set by hardware on a compare event.
Page 260 AT32A403A Series Reference Manual －OWCDIR=1, C1ORAW is low once TMRx_ C1DT <TMRx_CVAL, else high; 111: PWM mode B －OWCDIR=0, C1ORAW is low once TMRx_ C1DT >TMRx_CVAL, else high; －OWCDIR=1, C1ORAW is high once TMRx_ C1DT <TMRx_CVAL, else low. Note: In the configurations other than 000’, the C1OUT is connected to C1ORAW.
Page 261: Channel Control Register (Tmrx_Cctrl)
AT32A403A Series Reference Manual 0111: f /4, N=8 �� 1111: f /32, N=8 �� Channel 1 input divider This field defines Channel 1 input divider. 00: No divider. An input capture is generated at each active edge. Bit 3: 2...
Page 262: Period Register (Tmrx_Pr)
AT32A403A Series Reference Manual Register Reset value Type Description Divider value The counter clock frequency f /(DIV[15: CK_CNT TMR_CLK Bit 15: 0 0x0000 0]+1). DIV contains the value written at an overflow event. 14.3.5.9 Period register (TMRx_PR) Abbr. Reset value...
Page 263: Channel 1 Data Register (Tmrx_C1Dt)
AT32A403A Series Reference Manual 14.3.5.10 Channel 1 data register (TMRx_C1DT) Abbr. Reset value Type Description Channel 1 data register When the channel 1 is configured as input mode: The C1DT is the CVAL value stored by the last channel 1 input event (C1IN)
Page 264: Tmr1 And Tmr8 Functional Overview
AT32A403A Series Reference Manual Figure 14-59 Block diagram of advanced-control timer Clock failure event From clock control CSS(Clock Security System) Polarity TMRx_BRK selection Dead time TMRx_CH4 C4IRAW CH4 filter OUT MODE IN MODE C4IF C4IFP4 Output4 TMRx_CH4 STCI C4IN C4IN DIV...
Page 265: Figure 14-61 Control Circuit With Ck_Int, Tmrx_Div=0X0 And Tmrx_Pr=0X16
AT32A403A Series Reference Manual Figure 14-61 Control circuit with CK_INT, TMRx_DIV=0x0 and TMRx_PR=0x16 CK_INT TMREN COUNTER overflow OVFIF External clock (TRGIN/EXT) The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals. SMSEL=3’b111: External clock mode A is selected. Select an external clock source TRGIN signal by setting the STIS[2: 0] bit to drive the counter to start counting.
Page 266: Figure 14-62 Block Diagram Of External Clock Mode A
AT32A403A Series Reference Manual Figure 14-62 Block diagram of external clock mode A TMRx_CH1 C1DF C1P/C1CP STIS filter edge dector TMRx_CH2 C2DF C2P/C2CP C1INC External clock filter edge dector mode A enable External trigger C1IFP1 TRGIN SMSEL=3'b111 DIV_counter CK_CNT CNT_counter...
Page 267: Counting Mode
AT32A403A Series Reference Manual Below is the configuration procedure for internal trigger input: - Set counting cycles through TMRx_PR register - Set counting frequency through TMRx_DIV register - Set counting modes through the TWCMSEL[1:0] in TMRx_CTRL1 register - Select internal trigger by setting STIS[2:0]= 3’b000~3’b011 in TMRx_STCTRL register - Select external clock mode A by setting SMSEL[2:0]=3’b111 in TMRx_STCTRL register...
Page 268: Figure 14-16 Overflow Event When Prben=0
AT32A403A Series Reference Manual Figure 14-67 Basic structure of a counter PRBEN DIV_shadow TMRx_RPR Preload RPR_shadow TMRx_DIV Preload CNT_overflow Overflow event Overflow event DIV_counter CNT_counter RPR_counter DIV_overflow TMR_CLK (RPR_overflow) Overflow event TMRx_PR Preload PR_shadow PRBEN Upcounting mode Upcounting mode is enabled by setting CMSEL[1:0]=2’b00, OWCDIR=1’b0 in the TMRx_CTRL register.
Page 269: Figure 14-71 Counter Timing Diagram With Internal Clock Divided By 1 And Tmrx_Pr=0X32
AT32A403A Series Reference Manual Up/down counting mode Up/down counting mode can be enabled by setting CMSEL[1:0]≠2’b00 in the TMRx_CTRL1 register. In up/down counting mode, the counter counts up/down alternatively. When the counter counts from the value programmed in the TMRx_PR register down to 1, an underflow event is generated, and then restarts counting from 0;...
Page 270: Figure 14-72 Ovfif Behavior In Upcounting Mode And Two-Way Counting Mode
AT32A403A Series Reference Manual Figure 14-72 OVFIF behavior in upcounting mode and two-way counting mode Example 1 ： up count mode,RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 2 ： two-way up count mode3, RPR=0x2 COUNTER RPR[7:0] RPR_CNT overflow OVFIF clear Example 3 ：...
Page 271: Figure 14-73 Encoder Mode Structure
AT32A403A Series Reference Manual Figure 14-73 Encoder mode structure SMSEL=3'b001/010/011 encoder mode filter polarity select TMRx_CH2 C2IRAW C2DF C2IFP2 director C1DF C1IFP1 TMRx_CH3 filter polarity select edge C1IRAW TMRx_CH1 detector preload pos/neg edge C1INSEL TMRx_DIV encoder mode A encoder DIV_CLK...
Page 272: Tmr Input Function
AT32A403A Series Reference Manual Figure 14-74 Example of encoder interface mode C DOWN CI1RAW CI2RAW COUNTER TWCMSEL [1:0] 14.4.3.3 TMR input function Each timer of TMR1 and TMR8 has four independent channels. Each channel can be configured as input or output. As input, each channel input is handle as follows: TMRx_CHx outputs the pre-processed CxIRAW.
Page 273: Figure 14-76 Channel 1 Input Stage
AT32A403A Series Reference Manual Figure 14-76 Channel 1 input stage STIS edge detector C1INC input divider STCI C1IPS C1P/C1CP C1IDIV C1EN CNT counter Capture C1DT C1IFP1 C1IN TMRx_CH3 C1INSEL C2IFP1 C1SWTR C1IF TMRx_CH2 C1IRAW C1DF TMRx_CH1 filter C2IRAW C2DF C2IF...
Page 274: Tmr Output Function
AT32A403A Series Reference Manual Figure 14-77 PWM input mode configuration example C1C(2'b01) edge detector STCI C1P=0 C1DF C1IF C1IRAW C1EN Capture C1DT C1IFP1(pos) C1IN Capture trigger C1CP=0 filter C2IFP1 SMSEL(3'b110) (CH1 period) STIS(3'b101) Trigger mode C1INC Hang CNT counter mode...
Page 275: Figure 14-80 Channel 4 Output Stage
AT32A403A Series Reference Manual Figure 14-80 Channel 4 output stage CVAL CVAL = C4DT Output C4ORAW Compare mode Polarity Output controller CVAL>C4DT selection enable C4OUT C4DT circuit To the master mode controller Output mode Write CxC[1: 0]≠2’b00 to configure the channel as output to implement multiple output modes. In this...
Page 276: Figure 14-81 C1Oraw Toggles When Counter Value Matches The C1Dt Value
AT32A403A Series Reference Manual words, the comparison result is advanced, so the comparison result between the counter value and the TMRx_CxDT register will determine the level of CxORAW in advance. Figure 14-81 gives an example of output compare mode (toggle) with C1DT=0x3. When the counter value is equal to 0x3, C1OUT toggles.
Page 277: Figure 14-83 Up/Down Counting Mode And Pwm Mode A
AT32A403A Series Reference Manual Figure 14-83 Up/down counting mode and PWM mode A TMR_CLK COUNTER PR[15:0] DIV[15:0] C1OCTRL[2：0] C1DT[15：0] C1ORAW CIDT[15：0] C1ORAW ≥32 C1DT[15：0] C1ORAW Figure 14-84 One-pulse mode COUNTER PR[15：0] C1DT[15：0] TRGIN C1ORAW C1OUT Master mode timer event output When TMR is used as a master timer, one of the following source of signals can be selected as TRGOUT output to a slave mode timer.
Page 278: Tmr Break Function
AT32A403A Series Reference Manual Figure 14-85 Clearing CxORAW(PWM mode A) by EXT input COUNTER CxDT CxOSEN CxORAW Dead-time insertion The channel 1 to 3 of the advanced-control timers contains a set of reverse channel output. This function is enabled by the CxCEN bit and its polarity is defined by CxCP. Refer to...
Page 279: Figure 14-87 Tmr Output Control
AT32A403A Series Reference Manual BRKV bit. When a break event occurs, there are the following actions:  The OEN bit is cleared asynchronously, and the channel output state is selected by setting the FCSODIS bit. This function works even if the MCU oscillator is off.
Page 280: Tmr Synchronization
AT32A403A Series Reference Manual Figure 14-88 Example of TMR break function AOEN CxORAW CxEN CxCEN CxIOS CxCIOS CxOUT Delay CxCOUT Delay Delay 14.4.3.6 TMR synchronization The timers are linked together internally for timer synchronization. Master timer is selected by setting the PTOS[2: 0] bit;...
Page 281: Debug Mode
AT32A403A Series Reference Manual Figure 14-90 Example of suspend mode TMR_CLK CI1F1 TMR_EN CNT_CLK COUNTER PR[15:0] DIV[15:0] STIS[2：0] SMSEL[2：0] Slave mode: Trigger mode The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1) Figure 14-91 Example of trigger mode...
Page 282: Tmr1 And Tmr8 Control Register1 (Tmrx_Ctrl1)
AT32A403A Series Reference Manual TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_RPR 0x30 0x0000 TMRx_C1DT 0x34 0x0000 TMRx_C2DT 0x38 0x0000 TMRx_C3DT 0x3C 0x0000 TMRx_C4DT 0x40 0x0000 TMRx_BRK 0x44 0x0000 TMRx_DMACTRL 0x48 0x0000 TMRx_DMADT 0x4C 0x0000 14.4.4.1 TMR1 and TMR8 control register1 (TMRx_CTRL1) Abbr.
Page 283: Tmr1 And Tmr8 Control Register2 (Tmrx_Ctrl2)
AT32A403A Series Reference Manual Overflow event enable 0: Enabled Bit 1 OVFEN 1: Disabled TMR enable 0: Disabled Bit 0 TMREN 1: Enabled 14.4.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2) Abbr. Reset value Type Description Bit 15 Reserved 0x00 resd Kept at its default value.
Page 284: Tmr1 And Tmr8 Slave Timer Control Register (Tmrx_Stctrl)
AT32A403A Series Reference Manual 14.4.4.3 TMR1 and TMR8 slave timer control register (TMRx_STCTRL) Abbr. Reset value Type Description External signal polarity 0: High or rising edge Bit 15 1: Low or falling edge External clock mode B enable This bit is used to enable external clock mode B...
Page 285: Tmr1 And Tmr8 Dma/Interrupt Enable Register (Tmrx_Iden)
AT32A403A Series Reference Manual Subordinate TMR mode selection 000: Slave mode is disabled 001: Encoder mode A 010: Encoder mode B 011: Encoder mode C 100: Reset mode —Rising edge of the TRGIN input reinitializes the counter Bit 2: 0 SMSEL 101: Suspend mode —...
Page 286: Tmr1 And Tmr8 Interrupt Status Register (Tmrx_Ists)
AT32A403A Series Reference Manual 1: Enabled Channel 2 interrupt enable 0: Disabled Bit 2 C2IEN 1: Enabled Channel 1 interrupt enable 0: Disabled Bit 1 C1IEN 1: Enabled Overflow interrupt enable 0: Disabled Bit 0 OVFIEN 1: Enabled 14.4.4.5 TMR1 and TMR8 interrupt status register (TMRx_ISTS) Abbr.
Page 287: Software Event Register (Tmrx_Swevt)
AT32A403A Series Reference Manual This bit is set by hardware on a capture event. It is cleared by software or read access to the TMRx_C1DT 0: No capture event occurs 1: Capture event is generated If the channel 1 is configured as output mode: This bit is set by hardware on a compare event.
Page 288: Tmr1 And Tmr8 Channel Mode Register1 (Tmrx_Cm1)
AT32A403A Series Reference Manual 14.4.4.7 TMR1 and TMR8 channel mode register1 (TMRx_CM1) The channel can be used in input (capture mode) or output (compare mode). The direction of a channel is defined by the corresponding CxC bits. All the other bits of this register have different functions in input and output modes.
Page 289 AT32A403A Series Reference Manual 1: Buffer function of TMRx_C1DT is enabled. The value to be written to the TMRx_C1DT is stored in the buffer register, and can be sent to the TMRx_C1DT register only on an overflow event. Channel 1 output enable immediately In PWM mode A or B, this bit is used to accelerate the channel 1 output’s response to the trigger event.
Page 290: Channel Mode Register2 (Tmrx_Cm2)
AT32A403A Series Reference Manual 00: No divider. An input capture is generated at each active edge. 01: An input compare is generated every 2 active edges 10: An input compare is generated every 4 active edges 11: An input compare is generated every 8 active edges Note: the divider is reset once C1EN=’0’...
Page 291: Channel Control Register (Tmrx_Cctrl)
AT32A403A Series Reference Manual Input capture mode: Abbr. Reset value Type Description Channel 4 digital filter Bit 15: 12 C4DF Channel 4 input divider Bit 11: 10 C4IDIV Channel 4 configuration This field is used to define the direction of the channel 1 (input or output), and the selection of input pin when C4EN=’0’:...
Page 292 AT32A403A Series Reference Manual Channel 1 polarity When the channel 1 is configured in output mode: 0: C1OUT is active high 1: C1OUT is active low When the channel 1 is configured in input mode: The active edge of the input signal is defined by C1CP/C1P.
Page 293: Table 14-15 Complementary Output Channel Cxout And Cxcout Control Bits With Break Function
AT32A403A Series Reference Manual Table 14-15 Complementary output channel CxOUT and CxCOUT control bits with break function Control bit Output state FCSOEN CxEN CxCEN OEN bit FCSODIS bit CxOUT output state CxCOUT output state Output disabled Output disabled (no driven by the timer)
Page 294: Tmr1 And Tmr8 Counter Value (Tmrx_Cval)
AT32A403A Series Reference Manual 14.4.4.10 TMR1 and TMR8 counter value (TMRx_CVAL) Abbr. Reset value Type Description Bit 15: 0 CVAL 0x0000 Counter value 14.4.4.11 TMR1 and TMR8 division value (TMRx_DIV) Abbr. Reset value Type Description Divider value The counter clock frequency f...
Page 295: Tmr1 And Tmr8 Channel 3 Data Register (Tmrx_C3Dt)
AT32A403A Series Reference Manual 14.4.4.16 TMR1 and TMR8 channel 3 data register (TMRx_C3DT) Abbr. Reset value Type Description Channel 3 data register When the channel 3 is configured as input mode: The C3DT is the CVAL value stored by the last channel...
Page 296: Tmr1 And Tmr8 Dma Control Register (Tmrx_ Dmactrl)
AT32A403A Series Reference Manual 1: CxOUT/CxCOUT outputs are enabled. Output idle level. Write protection configuration This field is used to enable write protection. 00: Write protection is OFF. 01: Write protection level 3, and the following bits are write protected:...
Page 297: Tmr1 And Tmr8 Dma Data Register (Tmrx_ Dmadt)
AT32A403A Series Reference Manual 14.4.4.20 TMR1 and TMR8 DMA data register (TMRx_ DMADT) Abbr. Reset value Type Description DMA data register A write/read operation to the DMADT register accesses any TMR register located at the following address: Bit 15: 0...
Page 298: Window Watchdog Timer (Wwdt)
AT32A403A Series Reference Manual 15 Window watchdog timer (WWDT) 15.1 WWDT introduction The window watchdog downcounter must be reloaded in a limited time window to prevent the watchdog circuits from generating a system reset. The window watch dog is used to detect the occurrence of system malfunctions.
Page 299: Debug Mode
AT32A403A Series Reference Manual Table 15-1 Minimum and maximum timeout value when PCLK1=72 MHz Prescaler Min. Timeout value Max. Timeout value 56.5μs 3.64ms 113.5μs 7.28ms 227.5μs 14.56ms 455μs 29.12ms Figure 15-2 Window watchdog timing diagram 55 54 52 51 50...
Page 300: Status Register (Wwdt_Sts)
AT32A403A Series Reference Manual 01: PCLK1 divided by 8192 10: PCLK1 divided by 16384 11: PCLK1 divided by 32768 Window value If the counter is reloaded while its value is greater than the Bit 6: 0 0x7F window register value, a reset is generated. The counter must be reloaded between 0x40 and WIN[6: 0].
Page 301: Watchdog Timer (Wdt)
AT32A403A Series Reference Manual 16 Watchdog timer (WDT) 16.1 WDT introduction The WDT is driven by a dedicated low-speed clock (LICK). Due to the lower clock accuracy of LICK, the WDT is best suited to the applications that have lower timing accuracy and can run independently outside the main application.
Page 302: Debug Mode
AT32A403A Series Reference Manual Figure 16-1 WDT block diagram power domain 1.2 V power domain Prescaler register 8-bit SYNC WDT_DIV prescaler Reload register 12-bit reload 12-bit SYNC CNT=0 reset WDT_RLD value downcounter Status register WDT_STS CMD register WDT_CMD LICK 40KHz...
Page 303: Command Register (Wdt_Cmd)
AT32A403A Series Reference Manual 16.5.1 Command register (WDT_CMD) (Reset in Standby mode) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value. Command register 0xAAAA: Reload counter Bit 15: 0 0x0000 0x5555: Unlock write-protected WDT_DIV and WDT_RLD 0xCCCC: Enable WDT.
Page 304: Real-Time Clock (Rtc)
AT32A403A Series Reference Manual 17 Real-time clock (RTC) 17.1 RTC introduction The real-time clock provides a calendar clock function. It has an internal 32-bit incremental counter that is increased by one at each second. In other words, this counter serves as a second clock. The current second value can be converted into time and date to provide a calendar function.
Page 305: Rtc Functional Overview
AT32A403A Series Reference Manual Figure 17-1 Simplified RTC block diagram 1.2V power domain VBAT domain Powered in Standby mode RTC_TA Not powered in Standby mode RTC_Alarm RTC_Oveflow RTC_CNT OVFF LN_CLK Reload RTC_Second RTC_DIVCNT RTC_DIV RTC registers interface RTC_CLK NVIC interrupt controller...
Page 306: Reading Rtc Registers
AT32A403A Series Reference Manual 17.4.2 Reading RTC registers Based on synchronization circuit, when reading the RTC registers, the correct values have yet been uploaded from the battery powered domain to the APB1 interface if one of the following events occurred: A system reset or power reset has occurred;...
Page 307: Rtc Registers
AT32A403A Series Reference Manual Figure 17-3 RTC overflow waveform example with DIV=0004 RTC_CLK RTC_Second Can be cleared by software RTC_Overflow RTC_CNT FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 FFFFFFFC 17.5 RTC registers These peripheral registers must be accessed by words (32 bits).
Page 308: Rtc Control Register Low (Rtc_Ctrll)
AT32A403A Series Reference Manual 17.5.2 RTC control register low (RTC_CTRLL) Abbr. Reset value Type Description Bit 15: 6 Reserved 0x000 resd Kept at its default value. RTC configuration finish Indicates whether the last write operation on the RTC registers has been completed or not. Write access to the...
Page 309: Rtc Divider Counter Register (Rtc_Divcnth/Rtc_Divcntl)
AT32A403A Series Reference Manual 17.5.4 RTC divider counter register (RTC_DIVCNTH/RTC_DIVCNTL) RTC divider counter register high (RTC_DIVCNTH ) Abbr. Reset value Type Description Bit 15: 4 Reserved 0x000 resd Kept at its default value. Bit 3: 0 DIVCNT RTC clock divider counter RTC divider counter register low (RTC_DIVCNTL ) Abbr.
Page 310: Battery Powered Registers (Bpr)
AT32A403A Series Reference Manual 18 Battery powered registers (BPR) 18.1 BPR introduction The battery powered registers are located in the battery powered domain and powered by VDD/VBAT. These registers are forty two 16-bit registers. Upon a tamper event or when battery powered domain reset occurs, the contents in these registers are cleared so as to ensure the highest level of data security.
Page 311: Battery Powered Data Register X (Bpr_Dtx) (X = 1
AT32A403A Series Reference Manual BPR_DT14 0x4C 0x0000 0000 BPR_DT15 0x50 0x0000 0000 BPR_DT16 0x54 0x0000 0000 BPR_DT17 0x58 0x0000 0000 BPR_DT18 0x5C 0x0000 0000 BPR_DT19 0x60 0x0000 0000 BPR_DT20 0x64 0x0000 0000 BPR_DT21 0x68 0x0000 0000 BPR_DT22 0x6C 0x0000 0000...
Page 312: Bpr Control Register (Bpr_ Ctrl)
AT32A403A Series Reference Manual 1: Toggle output (The corresponding pin output level changes at each time when an alarm event or second event is detected) Note: This bit is reset only by a battery powered domain reset. Calibration clock output selection...
Page 313: Bpr Control/Status Register (Bpr_Ctrlsts)
AT32A403A Series Reference Manual 18.4.4 BPR control/status register (BPR_CTRLSTS) Abbr. Reset value Type Description Kept at its default value. Bit 15: 10 Reserved 0x00 resd Tamper interrupt flag This bit is set when a tamper event is detected and the TPIEN is set.
Page 314: Analog-To-Digital Converter (Adc)
AT32A403A Series Reference Manual 19 Analog-to-digital converter (ADC) 19.1 ADC introduction The ADC is a peripheral that converts an analog input signal into a 12-bit digital signal. Its sampling rate is as high as 2 MSPS. It has up to 18 channels for sampling and conversion.
Page 315: Adc Functional Overview
AT32A403A Series Reference Manual Figure 19-1 ADC1 block diagram OCTESEL[3:0] ADCPSC[3:0] TMR1_CH1 TMR1_CH2 ADC prescaler TMR1_CH3 PCLK2 TMR2_CH2 ADCCLK TMR3_TRGOUT TMR4_CH4 OCTEN EXINT11 ADCx_IN0 TMR8_TRGOUT Trigger ADCx_IN1 detection GPIO ADCx_ETO_MUX Ordinary OCSWTRG ADCx_IN15 conversion start TMR1_TRGOUT TMR8_CH1 Temp.sensor TMR8_CH2 INTRV...
Page 316: Internal Temperature Sensor
AT32A403A Series Reference Manual  ADC3_IN0 to ADC3_IN3, and ADC3_IN10 to ADC3_IN13 are referred to as the external analog input, the rest of them are Vss. Channel conversion The conversions are divided into two groups: ordinary and preempted. The preempted group has priority over the ordinary group.
Page 317: Power-On And Calibration
AT32A403A Series Reference Manual 19.4.2.1 Power-on and calibration Power-on Set the ADCxEN bit in the CRM_APB2EN register to enable ADC clocks: PCLK2 and ADCCLK. Program the desired ADCCLK frequency by setting the ADCDIV bit in the CRM_CFG register. The ADCCLK is derived from PCLK2 frequency division.
Page 318: Sampling And Conversion Sequence
AT32A403A Series Reference Manual Table 19-1 Trigger sources for ADC1 and ADC2 OCTESEL Source PCTESEL Source 0000 TMR1_CH1 event 0000 TMR1_TRGOUT event 0001 TMR1_CH2 event 0001 TMR1_CH4 event 0010 TMR1_CH3 event 0010 TMR2_TRGOUT event 0011 TMR2_CH2 event 0011 TMR2_CH1 event...
Page 319: Conversion Sequence Management
AT32A403A Series Reference Manual 19.4.3 Conversion sequence management Only one channel is converted at each trigger event by default, that is, OSN1-defined channel or PSN4- defined channel. The detailed conversion sequence modes are described in the following sections. With this, the channels can be converted in a specific order.
Page 320: Repetition Mode
AT32A403A Series Reference Manual 19.4.3.3 Repetition mode The repetition mode is enabled by setting the RPEN bit in the ADC_CTRL2 register. When a trigger signal is detected, the ordinary channels will be converting repeatedly. This mode can work with the ordinary channel conversion in the sequence mode to enable the repeated conversion of the ordinary group.
Page 321: Data Management
AT32A403A Series Reference Manual 19.4.4 Data management At the end of the conversion of the ordinary group, the converted value is stored in the ADC_ODT register. Once the preempted group conversion ends, the converted data of the preempted group is stored in the ADC_PDTx register.
Page 322: Master/Slave Mode
AT32A403A Series Reference Manual 19.5 Master/Slave mode If Master/Slave mode is enabled, the master is triggered to work with the slave to do the channel conversion. The ADC_ODT register is used as a single interface obtaining the ordinary channel converted data of master/salve ADC.
Page 323: Alternate Preempted Trigger Mode
AT32A403A Series Reference Manual Figure 19-10 Regular simultaneous mode ADC1: OCLEN=2, OSN1=ADC1_IN0, OSN2=ADC1_IN1, OSN3=ADC1_IN2 Sampling ADC2: OCLEN=2, OSN1=ADC2_IN5, OSN2=ADC2_IN4, OSN3=ADC2_IN3 Conversion ADC1 ordinary ADC1 ordinary trigger trigger ADC1 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC1_IN0 ADC1_IN1 ADC1_IN2 ADC2 ADC2_IN5 ADC2_IN4 ADC2_IN3 ADC2_IN5 ADC2_IN4...
Page 324: Regular Switch Mode
AT32A403A Series Reference Manual Combined regular simultaneous + alternate preempted trigger mode MSSEL bit in the ADC_CTRL1 register is used to select combined regular simultaneous + alternate preempted trigger mode. In this mode, trigger the regular group of the master to start regular simultaneous conversion of master/slave, or trigger the preempted group of the master continuously to allow the master/slave ADCs to convert the preempted group alternately.
Page 325: Adc Registers
AT32A403A Series Reference Manual Figure 19-14 Fast slow mode ADC1: SQEN=0, OSN1=ADC1_IN3, RPEN=1 Sampling ADC2: SQEN=0, OSN1=ADC2_IN3, RPEN=1 ADC1 ordinary Conversion trigger ADC1 ADC1_IN3 ADC1_IN3 ADC1_IN3 ADC1 CCE flag set ADC2_IN3 ADC2_IN3 ADC2_IN3 ADC2 ADC2 CCE flag set 14 ADCCLK...
Page 326: Adc Status Register (Adc_Sts)
AT32A403A Series Reference Manual 19.6.1 ADC status register (ADC_STS) Abbr. Reset value Type Description Bit 31: 5 Reserved 0x0000000 resd Kept at its default value. Ordinary channel conversion start flag This bit is set by hardware and cleared by software (writing...
Page 327 AT32A403A Series Reference Manual Master/slave mode select 0000: Independent mode 0001: Combined regular simultaneous + preempted simultaneous mode 0010: Combined regular simultaneous + alternate preempted trigger mode 0011: Combined preempted simultaneous + fast switch mode on regular group 0100: Combined preempted simultaneous + slow switch...
Page 328: Adc Control Register2 (Adc_Ctrl2)
AT32A403A Series Reference Manual Channel conversion end interrupt enable 0: Channel conversion end interrupt disabled Bit 5 CCEIEN 1: Channel conversion end interrupt enabled Voltage monitoring channel select This filed is valid only when the VMSGEN is enabled. 00000: ADC_IN0 channel 00001: ADC_IN1 channel ……...
Page 329 AT32A403A Series Reference Manual For ADC3, the trigger events are configured as follows: 0000: Timer 3 CH1 event 0001: Timer 2 CH3 event 0010: Timer 1 CH3 event 0011: Timer 8 CH1 event 0100: Timer 8 TRGOUT event 0101: Timer 5 CH1 event...
Page 330: Adc Sampling Time Register 1 (Adc_Spt1)
AT32A403A Series Reference Manual generate a DMA request itself Kept at its default value. Bit 7: 4 Reserved resd Initialize A/D calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized.
Page 331 AT32A403A Series Reference Manual 011; 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN15 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 17: 15 CSPT15 100: 41.5 cycles...
Page 332: Adc Sampling Time Register 2 (Adc_Spt2)
AT32A403A Series Reference Manual 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 19.6.5 ADC sampling time register 2 (ADC_SPT2) Abbr. Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Sample time selection of channel ADC_IN9 000: 1.5 cycles...
Page 333 AT32A403A Series Reference Manual 110: 71.5 cycles 111: 239.5 cycles Sample time selection of channel ADC_IN4 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles Bit 14: 12 CSPT4 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles...
Page 334: Adc Preempted Channel Data Offset Register
AT32A403A Series Reference Manual 19.6.6 ADC preempted channel data offset register x (ADC_PCDTOx) (x=1..4) Abbr. Reset value Type Description Kept at its default value Bit 31: 12 Reserved 0x00000 resd Data offset for Preempted channel x Bit 11: 0 PCDTOx...
Page 335: Adc Ordinary Sequence Register 3 (Adc_ Osq3)
AT32A403A Series Reference Manual 19.6.11 ADC ordinary sequence register 3 ( ADC_ OSQ3) Abbr. Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value Bit 29: 25 OSN6 0x00 Number of 6th conversion in ordinary sequence...
Page 336: Digital-To-Analog Converter (Dac)
AT32A403A Series Reference Manual 20 Digital-to-analog converter (DAC) 20.1 DAC introduction The DAC uses a 12-bit digital input to generate an analog output between 0 and reference voltage. The digital part of the DAC can be configured in 8-bit or 12-bit mode and can be used in conjunction with the DMA.
Page 337: Function Overview
AT32A403A Series Reference Manual  Input/output configuration The digital inputs are linearly converted to analog voltage outputs by the DAC, and it is between 0 and V The analog DAC module is supplied by VDDA. The positive analog reference voltage REF+.
Page 338: Figure 20-2 Lfsr Register Calculation Algorithm
AT32A403A Series Reference Manual Figure 20-2 LFSR register calculation algorithm The DxNBSEL [3: 0] bit in the DAC_CTRL register is set to mark partially or totally the LFSR data. The resulting value is then added up to the DHRx value without overflow and this value is loaded into the DAC_DxODT register.
Page 339: Dac Data Alignment
AT32A403A Series Reference Manual 20.4.3 DAC data alignment The DAC supports a single DAC and dual DA mode. The data format is dependent on the selected configuration mode. Single DAC data format: 8-bit right alignment: load data into the DAC_DxDTH8R [7:0]...
Page 340 AT32A403A Series Reference Manual to 7 0011: Unmask LSFR bit [3: 0] /Triangle amplitude is equal to 15 0100: Unmask LSFR bit [4: 0] /Triangle amplitude is equal to 31 0101: Unmask LSFR bit [5: 0] /Triangle amplitude is equal to 63...
Page 341 AT32A403A Series Reference Manual DAC1 noise bit select These bits are used to select the mark bit in noise generation mode amplitude triangular-wave generation mode. 0000: Unmask LSFR bit0/Triangle amplitude is equal to 1 0001: Unmask LSFR bit[1:0]/Triangle amplitude is equal to...
Page 342: Dac Software Trigger Register (Dac_Swtrg)
AT32A403A Series Reference Manual 1: DAC1 output buffer disabled DAC1 enable 0: DAC1 disabled Bit 0 D1EN 1: DAC1 enabled 20.5.2 DAC software trigger register (DAC_SWTRG) Abbr. Reset value Type Description Kept at its default value Bit 31: 2 Reserved...
Page 343: Dac2 12-Bit Left-Aligned Data Holding Register (Dac_D2Dth12L)
AT32A403A Series Reference Manual 20.5.7 DAC2 12-bit left-aligned data holding register (DAC_D2DTH12L) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Kept at its default value Bit 15: 4 D2DT12L 0x000 DAC2 12-bit left-aligned data Bit 3: 0...
Page 344: Can
AT32A403A Series Reference Manual 21 CAN 21.1 CAN introduction CAN (Controller Area Network) is a distributed serial communication protocol for real-time and reliable data communication among various nodes. It supports the CAN protocol version 2.0A and 2.0B. 21.2 CAN main features ...
Page 345 AT32A403A Series Reference Manual = 1 x t ��_�� = (1 + BTS1[3: 0]) x t ��1 �� = (1 + BTS2[2: 0]) x t ��2 �� = (1 + BRDIV[11: 0]) x t �� Hard synchronization and resynchronization The start location of each bit in CAN nodes is always in synchronization segment by default, and the sampling is performed at the edge location of bit segment 1 and big segment 2 simultaneously.
Page 346: Figure 21-2 Frame Type
AT32A403A Series Reference Manual Figure 21-2 Frame type Inter-frame Inter-frame space or Data frame (standard identifier) space overload frame 44 + 8* N Ack field Data field Arbitration field Control field CRC field 8* N Inter-frame Inter-frame space or Data frame ( extended identifier)
Page 347: Interrupt Management
AT32A403A Series Reference Manual 21.4 Interrupt management The CAN controller contains four interrupt vectors that can be used to enable or disable interrupts by setting the CAN_INTEN register. Figure 21-3 Transmit interrupt generation TCIEN = 1 TX_INT TM0TCF = 1...
Page 348: Design Tips
AT32A403A Series Reference Manual 21.5 Design tips The following information can be used as reference for CAN application development:  Debug control When the system enters the debug mode, the CAN controller stops or continues to work normally, depending on the CANx_PAUSE bit in the DEBUG_CTRL register or the PTD bit in the CAN_MCTRL register.
Page 349: Operating Modes
AT32A403A Series Reference Manual 21.6.2 Operating modes The CAN controller has three operating modes:  Sleep mode After a system reset, the CAN controller is in Sleep mode. In this mode, the CAN clock is stopped to reduce power consumption and an internal pull-up resistance is disabled. However, the software can still access to the mailbox registers.
Page 350: Message Filtering
AT32A403A Series Reference Manual 21.6.4 Message filtering The received message has to go through filtering by its identifier. If passed, the message will be stored in the corresponding FIFOs. If not, the message will be discarded. The whole operation is done by hardware without using CPU resources.
Page 351: Figure 21-11 16-Bit Identifier List Mode
AT32A403A Series Reference Manual Figure 21-11 16-bit identifier list mode CAN_FiFB1[15:8] CAN_FiFB1[7:0] CAN_FiFB1[31:24] CAN_FiFB1[23:16] CAN_FiFB2[15:8] CAN_FiFB2[7:0] CAN_FiFB2[31:24] CAN_FiFB2[23:16] SID[10:0] EID[17:15] Mapping Filter match number 14 filter banks have different filtering effects dependent on the bit width mode. For example, 32-bit identifier mask mode contains the filters numbered n while 16-bit identifier list mode contains the filters numbered n, n+1, n+2 and n+3.
Page 352: Message Transmission
AT32A403A Series Reference Manual Priority rules When the CAN controller receives a frame of message, the message may pass through several filters. In this case, the filter match number stored in the receive mailbox is determined according to the following priority rules: ...
Page 353: Figure 21-12 Transmit Mailbox Status
AT32A403A Series Reference Manual Figure 21-12 Transmit mailbox status EMPTY Send request(TMSR = 1) Abort sending(TMxCT = 1) PENDING Is it the highest priority Abort sending(TMxCT = 1) SCHEDULED Is the bus idle Send success or send failed with Send failed with automatic...
Page 354: Message Reception
AT32A403A Series Reference Manual 21.6.6 Message reception Register configuration The CAN_RFIx, CAN_RFCx, CAN_RFDTLx and CAN_RFDTHx registers can be used by user applications to obtain valid messages. Message reception The CAN controller boasts two FIFO with three levels to receive messages. FIFO rule is adopted. When the message is received correctly and has passed the identifier filtering, it is regarded as a valid message and is stored in the corresponding FIFO.
Page 355: Can Registers
AT32A403A Series Reference Manual Option 2: When AEBOEN=1 in the CAN_MCTRL register, the CAN will resume from bus-off state automatically after 128 occurrences of 11 consecutive recessive bits have been detected on the CAN RX pin 21.7 CAN registers These peripheral registers must be accessed by words (32 bits).
Page 356: Can Control And Status Registers
AT32A403A Series Reference Manual Reserved 210h 214h 0x0000 0000 Reserved 218h FACFG 21Ch 0x0000 0000 Reserved 220h~23Fh F0FB1 240h 0xXXXX XXXX F0FB2 244h 0xXXXX XXXX F1FB1 248h 0xXXXX XXXX F1FB2 24Ch 0xXXXX XXXX … … F13FB1 2A8h 0xXXXX XXXX F13FB2...
Page 357: Can Master Status Register (Can_Msts)
AT32A403A Series Reference Manual mode is left by software clearing the sleep request command. When Automatic exit sleep mode is enabled, the sleep mode is left without the need of software intervention as soon as a message is monitored on the CAN bus.
Page 358 AT32A403A Series Reference Manual 1: Transmit is in progress Note: This bit is set by hardware when the CAN transmission starts, and it is cleared by hardware at the end of transmission. Kept at its default value. Bit 7: 5...
Page 359: Can Transmit Status Register (Can_Tsts)
AT32A403A Series Reference Manual Freeze mode after this bit is set by hardware. The Freeze mode is left only once 11 consecutive recessive bits have been detect on the CAN RX pin. For this reason, the software acknowledges the exit of Freeze mode after this bit is cleared by hardware.
Page 360 AT32A403A Series Reference Manual occurred. It is cleared by software writing 1 or by hardware at the start of the next transmission Transmit mailbox 2 arbitration lost flag 0: No arbitration lost 1: Transmit mailbox 2 arbitration lost Note: Bit 18...
Page 361: Can Receive Fifo 0 Register (Can_Rf0)
AT32A403A Series Reference Manual successful or not. It is cleared by software writing 1. Transmit mailbox 1 transmission completed flag 0: Transmission is in progress 1: Transmission is completed Note: This bit is set by hardware when the transmission/abort Bit 8...
Page 362: Can Receive Fifo 1 Register (Can_Rf1)
AT32A403A Series Reference Manual 0: No effect 1: Release FIFO Note: This bit is set by software to release FIFO 0. It is cleared by hardware when the FIFO 0 is released. Setting this bit by software has no effect when the FIFO 0 is empty.
Page 363: Can Interrupt Enable Register (Can_Inten)
AT32A403A Series Reference Manual Receive FIFO 1 full flag 0: Receive FIFO 1 is not full 1: Receive FIFO 1 is full Note: Bit 3 RF1FF rw1c This bit is set by hardware when three messages are pending in the FIFO 1.
Page 364: Can Error Status Register (Can_Ests)
AT32A403A Series Reference Manual 0: Error warning interrupt disabled 1: Error warning interrupt enabled Note: EOIF is set only when this interrupt is enabled and the EAF is set by hardware. Kept at its default value. Bit 7 Reserved resd...
Page 365: Can Bit Timing Register (Can_Btmg)
AT32A403A Series Reference Manual 010: Format error 011: Acknowledgement error 100: Recessive bit error 101: Dominant bit error 110: CRC error 111: Set by software Note: This field is used to indicate the current error type. It is set by hardware according to the error condition detected on the CAN bus.
Page 366: Can Mailbox Registers
AT32A403A Series Reference Manual Baud rate division tq = (BRDIV[11: 0]+1) x tPCLK Bit 11: 0 BRDIV 0x000 Note: This field defines the length of a time unit (tq). 21.7.2 CAN mailbox registers This section describes the registers of the transmit and receive mailboxes. Refer to Section 21.6.5...
Page 367: Transmit Mailbox Data Length And Time Stamp Register (Can_Tmcx
AT32A403A Series Reference Manual 21.7.2.2 Transmit mailbox data length and time stamp register (CAN_TMCx) (x=0..2) All the bits in the register are write protected when the mailbox is not in empty state. Abbr. Reset value Type Description Transmit mailbox time stamp...
Page 368: Receive Fifo Mailbox Data Length And Time Stamp Register
AT32A403A Series Reference Manual identifier. Receive FIFO identifier type indication 0: Standard identifier Bit 2 RFIDI 1: Extended identifier Receive FIFO frame type indication 0: Data frame Bit 1 RFFRI 1: Remote frame Kept at its default value Bit 0...
Page 369: Can Filter Registers
AT32A403A Series Reference Manual 21.7.3 CAN filter registers 21.7.3.1 CAN filter control register (CAN_FCTRL) Note: All the non-reserved bits of this register are controlled by software completely. Abbr. Reset value Type Description Bit 31: 1 Reserved 0x160E0700 resd Kept at its default value...
Page 370: Can Filter Bank I Filter Bit Register (Can_ Fifbx) (I=0
AT32A403A Series Reference Manual 21.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2) Note: There are 14 filter banks (i=0..13). Each filter bank consists of two 32-bit registers, CAN_FiFB[2: 1]. This register can be modified only when the FAENx bit of the CAN_FACFG register is cleared or the FCS bit of the CAN_FCTRL register is set.
Page 371: External Memory Controller
AT32A403A Series Reference Manual 22 External memory controller 22.1 XMC introduction XMC peripheral block can translate the AHB signals into the external memory signals and vice versa. It boasts two chip-select signals for interfacing up to external memories at a time. The supported external memories include a NAND Flash and a static memory device featuring multiplexed signals or additional address latch function.
Page 372: Xmc Architecture
AT32A403A Series Reference Manual 22.3 XMC architecture 22.3.1 Block diagram Figure 22-1 XMC block diagram Address/Data bus XMC registers AHB XMC memory AHB interface interface Central memory XMC_A[0] controller XMC_A[23:16] XMC_D[15:0] XMC_NOE NOR/PSRAM memory interface XMC_NWE XMC_NWAIT XMC_NE[1] XMC_NE[4] XMC_NADV...
Page 373: Address Mapping
AT32A403A Series Reference Manual 22.3.2 Address mapping XMC address is divided into multiple memory banks, as shown below. Figure 22-2 XMC memory banks Memory Address Memory banks chip select signals 6000 0000h NOR/PSRAM bank1 16 MB XMC_NE[1] 60FF FFFFh Reserved...
Page 374: Nor/Psram
AT32A403A Series Reference Manual 22.4 NOR/PSRAM NOR/PSRAM offers multiple access modes with different timings to drive multiple memories including NOR Flash, SRAM, PSRAM and Cellular RAM. There are two banks, bank 1 and bank 4, with independent control registers. Such two banks can be accessed by means of different timings and different chip-select signals.
Page 375: Access Mode
AT32A403A Series Reference Manual read/write Synchronous read Synchronous Split into two XMC accesses read Asynchronous read Asynchronous Use XMC_LB and XMC_UB write Asynchronous read/write Asynchronous PSRAM Split into two XMC accesses read/write Synchronous Use XMC_LB and XMC_UB write Synchronous read/write...
Page 376: Table 22-9 Mode 1-Sram/Nor Flash Chip Select Timing Register (Xmc_ Bk1Tmg)
AT32A403A Series Reference Manual Bit 10 WRAPEN: Wrapped enable Bit 9 NWPOL: NWAIT polarity Configure according to memory specifications Bit 8 SYNCBEN: Synchronous burst enable Bit 7 Reserved Bit 6 NOREN: NOR flash access enable EXTMDBW: External memory data Bit 5: 4...
Page 377: Figure 22-3 Nor/Psarm Mode 1 Read Access
AT32A403A Series Reference Manual Figure 22-3 NOR/PSARM mode 1 read access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] XMC_NOE High XMC_NWE Data signals XMC_LB XMC_UB Data from external memory High-Z XMC_D[15：0]...
Page 378: Figure 22-4 Nor/Psarm Mode 1 Write Access
AT32A403A Series Reference Manual Figure 22-4 NOR/PSARM mode 1 write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0]...
Page 379: Figure 22-5 Nor/Psarm Mode 2 Read Access
AT32A403A Series Reference Manual Table 22-11 Mode 2 — SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale...
Page 380: Read/Write Operation With Different Timings
AT32A403A Series Reference Manual Figure 22-6 NOR/PSARM mode 2 write access Don t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15：0] Data from XMC High-Z 22.4.2.2 Read/write operation with different timings...
Page 381: Figure 22-7 Nor/Psarm Mode A Read Access
AT32A403A Series Reference Manual Table 22-13 Mode A— SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x0 (Mode A) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale...
Page 382: Figure 22-8 Nor/Psarm Mode A Write Access
AT32A403A Series Reference Manual Figure 22-8 NOR/PSARM mode A write access Don t care DTST+1 ADDRST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_A[23：16] Address signals Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15：0] Data from XMC...
Page 383: Figure 22-9 Nor/Psarm Mode B Read Access
AT32A403A Series Reference Manual Table 22-16 Mode B— SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x1 (Mode B) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale...
Page 384: Figure 22-10 Nor/Psarm Mode B Write Access
AT32A403A Series Reference Manual Figure 22-10 NOR/PSARM mode B write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0]...
Page 385: Figure 22-11 Nor/Psarm Mode C Read Access
AT32A403A Series Reference Manual Table 22-19 Mode C—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x2 (Mode C) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale...
Page 386: Figure 22-12 Nor/Psarm Mode C Write Access
AT32A403A Series Reference Manual Figure 22-12 NOR/PSARM mode C write access Don t care ADDRST+1 DTST+1 HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB XMC_D[15：0] Data from XMC...
Page 387: Figure 22-13 Nor/Psarm Mode D Read Access
AT32A403A Series Reference Manual Table 22-22 Mode D—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode 0x3 (Mode D) Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale...
Page 388: Multiplexed Mode
AT32A403A Series Reference Manual Figure 22-14 NOR/PSARM mode D write access t care ADDRST+1 ADDRHT+1 DTST+1 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address XMC_A[0] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Data from XMC XMC_D[15：0]...
Page 389: Figure 22-15 Nor/Psarm Multiplexed Mode Read Access
AT32A403A Series Reference Manual Table 22-25 Multiplexed mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Bit 27: 24 DTLAT: Data latency Bit 23: 20 CLKPSC: Clock prescale Indicates the time the XMC_NE[x] from the rising edge to the...
Page 390: Synchronous Mode
AT32A403A Series Reference Manual Figure 22-16 NOR/PSARM multiplexed mode write access Don t care ADDRST+1 ADDRHT+1 DTST+2 HCLK HCLK HCLK HCLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address[23:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Address data Data from XMC XMC_D[15：0]...
Page 391: Figure 22-17 Nor/Psarm Synchronous Multiplexed Mode Read Access
AT32A403A Series Reference Manual Bit 0 EN: Memory bank enable Table 22-27 Synchronous mode—SRAM/NOR Flash chip select timing register (XMC_BK1TMG) Description Configuration Bit 31: 30 Reserved Bit 29: 28 ASYNCM: Asynchronous mode Figure 22-17 Figure 22-18 Bit 27: 24 DTLAT: Data latency Refer to XMC_CLK cycle is HCLK cycle*(CLKPSC+1).
Page 392: Nand
AT32A403A Series Reference Manual Figure 22-18 NOR/PSARM synchronous multiplexed mode write access DTLAT+1 Don t care XMC_CLK Clock XMC_CLK Chip select XMC_NE[x] signal XMC_NADV Address signals XMC_A[23：16] Memory address[23:16] High XMC_NOE XMC_NWE Data signals XMC_LB XMC_UB Wait signal XMC_NWAIT Address data XMC_D[15：0]...
Page 393: Access Timings
AT32A403A Series Reference Manual section, and reads or writes the data from or to the data section. As the access addresses are transmitted through data bus, the HADDR is actually not associated with NAND Flash size, so theoretically the XMC has no limitation on the NAND Flash capacity accessible.
Page 394: Figure 22-19 Nand Read Access
AT32A403A Series Reference Manual Figure 22-19 NAND read access RGST+2 HCLK RGWT+1 RGHT RGDHIZT+1 HCLK HCLK HCLK Chip select XMC_NCE[2] signal XMC_A[17:16] ALE/CLE If write XMC_NOE High Data XMC_NWE signals XMC_D[15：0] Data from XMC High-Z If read XMC_NOE High Data...
Page 395: Ecc Computation
AT32A403A Series Reference Manual Figure 22-20 NAND wait functionality XMC check SPHT+1 XMC_NWAIT HCLK Chip select XMC_NCE[2] signal XMC_A[17] XMC_A[16] High XMC_NOE Data XMC_NWE signals Address3 Command Address0 Address1 Address2 XMC_D[7：0] High-Z XMC_NWAIT CPU write CPU write CPU write CPU write...
Page 396: Nor Flash And Psram Control Registers
AT32A403A Series Reference Manual XMC_BK2TMGRG 0x068 0xFCFC FCFC XMC_BK2TMGSP 0x06C 0xFCFC FCFC XMC_BK2ECC 0x074 0x0000 0000 XMC_BK1TMGWR1 0x104 0x0FFF FFFF XMC_BK1TMGWR4 0x11C 0x0FFF FFFF XMC_EXT1 0x220 0x0000 0808 XMC_EXT4 0x22C 0x0000 0808 22.6.1 NOR Flash and PSRAM control registers 22.6.1.1...
Page 397: Sram/Nor Flash Chip Select Control Register 4 (Xmc_Bk1Ctrl4)
AT32A403A Series Reference Manual access into two accesses. 0: Direct wrapped access is not allowed 1: Direct wrapped access is allowed NWAIT polarity This bit defines the polarity of the NWAIT signal in synchronous mode. Bit 9 NWPOL 0: NWAIT active low...
Page 398 AT32A403A Series Reference Manual Others: Reserved. NWAIT enable during asynchronous transfer 0: NWAIT signal is disabled Bit 15 NWASEN 1: NWAIT signal is enable Read-write timing different Different timings are used for read and write operations, that is, the XMC_BK1TMGWR register is enabled.
Page 399: Sram/Nor Flash Chip Select Timing Register
AT32A403A Series Reference Manual Memory bank enable 0: Memory bank disabled Bit 0 1: Memory bank enabled 22.6.1.3 SRAM/NOR Flash chip select timing register 1, 4 (XMC_BK1CTRL1, 4) Abbr. Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value.
Page 400: Sram/Nor Flash Write Timing Register 1, 4 (Xmc_Bk1Tmgw R1, 4)
AT32A403A Series Reference Manual 22.6.1.4 SRAM/NOR Flash write timing register 1, 4 (XMC_BK1TMGWR1, 4) Abbr. Reset value Type Description Bit 31: 30 Reserved resd Kept at its default value. Asynchronous mode This field is valid only when the RWTD bit is enabled.
Page 401: Nand Flash Control Registers
AT32A403A Series Reference Manual duration for consecutive write operations. A delay is inserted between two consecutive write operations in order to avoid bus conflicts. 00000000: 1 HCLK cycle is inserted for consecutive write operations 00000001: 2 HCLK cycles are inserted for consecutive write operations ……...
Page 402: Interrupt Enable And Fifo Status Register 2 (Xmc_Bk2Is)
AT32A403A Series Reference Manual This bit is used to enable NAND Flash wait function. 0: Disabled 1: Enabled Kept at its default value. Bit 0 Reserved resd 22.6.2.2 Interrupt enable and FIFO status register 2 (XMC_BK2IS) Abbr. Reset value Type...
Page 403: Special Memory Timing Register 2 (Xmc_ Bk2Tmgsp)
AT32A403A Series Reference Manual Specifies the regular memory wait time when the XMC_NWE and XMC_NOE is low. 00000000: 0 HCLK cycle is inserted 00000001: 1 additional HCLK cycle is inserted …… 11111111: 255 additional HCLK cycles are inserted Regular memory setup time This field defines the address setup time when access to NAND Flash in a regular memory.
Page 404: Sdio Interface
AT32A403A Series Reference Manual 23 SDIO interface 23.1 SDIO introduction The SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB peripheral bus and MultiMediaCards (MMC), SD memory cards and SDIO cards. SD memory card and SDI/O card system specifications are available through the SD card association website www.sdcard.org.
Page 405: Figure 23-1 Sdio "No Response" And "No Data" Operations
AT32A403A Series Reference Manual Figure 23-1 SDIO “no response” and “no data” operations From From From host host card to card to card to host SDIO_CMD Command Command Response SDIO_D Operation (No response) Operation (No data) Figure 23-2 SDIO multiple block read operation...
Page 406: Sdio Main Features
AT32A403A Series Reference Manual Figure 23-4 SDIO sequential read operation From From host card to card to host Stop command stops data Data from card transfer to host SDIO_CMD Command Response Command Response SDIO_D Data stream Data stop operation Data transfer operation...
Page 407: Data Transfer Mode
AT32A403A Series Reference Manual The card identification process is described as follows: The bus is activated to confirm whether the card is connected or not. The clock frequency is at 0- 400kHz during the card identification process. The SDIO host sends a SD card, SDI/O card or MMC card.
Page 408: Erase
AT32A403A Series Reference Manual Data blocks will keep transferring until the host sends CMD12(STOP_TRANSMISSION). The stop command has an execution delay due to the serial command transmission and the data transfers stops after the end bit of the stop command.
Page 409: Table 23-1 Lock/Unlock Command Structure
AT32A403A Series Reference Manual bit in the CSD, part of the data can be protected, and the write protection can be changed by the application. The SET_WRITE_PROT commands set the write protection of the addressed group. The CLR_WRITE_PROT commands clear the write protection of the addressed group. The SEND_WRITE_PROT command is similar to a single block read command.
Page 410 AT32A403A Series Reference Manual When the old password is matched, the new password and its size are saved into the PWD and PWD_LEN fields, respectively. When the old password sent is not correct (in size and/or content), the LOCK_UNLOCK_FAILED error bit is set in the SDIO_STS register, and the old password is not changed.
Page 411: Commands And Responses
AT32A403A Series Reference Manual Forcing erase If the user forgot the password (PWD content), it is possible to access the card after clearing all the data on the card. This forced erase operation will erase all card data and all password data.
Page 412: Table 23-3 Data Block Read Commands
AT32A403A Series Reference Manual [31: 26] set to 0 [25: 24] access Used only for the MMC card to switch the [23: 16] index CMD6 SWITCH operation modes modify [15: 8] value EXT_CSD register [7: 3] set to 0 [2: 0] command set...
Page 413 AT32A403A Series Reference Manual Read data stream form the host starting WRITE_DAT_ CMD20 adtc [31: 0]= data address R1 from given address until UNTIL_STOP STOP_TRANSMISSION is received. 2023.07.10 Page 413 Rev 2.00...
Page 414: Table 23-5 Data Block Write Commands
AT32A403A Series Reference Manual Table 23-5 Data block write commands Response CMD index Type Parameter Abbreviation Description format This command is used to set the length [31: 0]=data block SET_ of data blocks (in bytes) for all block CMD16 length BLOCKLEN commands.
Page 415: Response Formats
AT32A403A Series Reference Manual Table 23-8 I/O mode commands Response CMD index Type Parameter Abbreviation Description format Used to write and read 8-bit (register) data fields. The command specifies a [31: 16]=RCA card and a register and provides the data [15]=register write for writing if the write flag is set.
Page 416: Table 23-11 R1 Response
AT32A403A Series Reference Manual Table 23-11 R1 response [45: 40] [39: 8] [7: 1] Field width Value Transmission Command Description Start bit Card status CRC7 End bit index 23.3.2.2.2 It is the same as R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception.
Page 417: Sdio Functional Description
AT32A403A Series Reference Manual 23.3.2.2.6 For SD I/O only, an SDIO card will respond with a unique SDIO response R4 after receiving the CMD5. Table 23-15 R4b response [45: 40] [39: 8] [7: 1] Field width Value Card Number of I/O...
Page 418: Sdio Adapter
AT32A403A Series Reference Manual Figure 23-6 SDIO block diagram SDIO Adapter AHB Bus Control unit SDIO_CK Adapter DMA_req Command Interface SDIO_CMD Register Path DMA_ack SDIO_INT Data SDIO_D [ 7:0 ] Path HCLK SDIOCLK 23.3.3.1 SDIO adapter SDIO_CK is a clock to the MultiMedia/SD/SDIO car provided by the host. One bit of command or data is transferred on both command and data lines with each clock cycle.
Page 419: Table 23-19 Command Formats
AT32A403A Series Reference Manual register where the CLKDIV bit is used to define the divider factor between the SDIOCLK and the SDIO output clock. If BYPSEN = 0, the SDIO_CK output signal is driven by the SDIOCLK divided according to the CLKDIV bit; if BYPSEN = 1, the SDIO_CK output signal is directly driven by the SDIOCLK. The HFCEN is set to enable hardware flow control feature in order to avoid the occurrence of an error at transmission underflow or reception overflow.
Page 420: Figure 23-7 Command Channel State Machine (Ccsm)
AT32A403A Series Reference Manual Table 23-22 Command path status flags Flag Description CMDRSPCMPL A response is already received (CRC OK) CMDFAIL A command response is already received (CRC fails) CMDCMPL A command is sent (does not require a response) CMDTIMEOUT...
Page 421: Figure 23-8 Sdio Command Transfer
AT32A403A Series Reference Manual Figure 23-8 SDIO command transfer At least 8 SDIO_CK cycles SDIO_CMD Response CPSM status Idle Send Wait Receive Idle Send Data path The data path subunit transfers data between the host and the cards. The databus width can be configured using the BUSWS bit in the SDIO_CLKCTRL register.
Page 422: Data Buf
AT32A403A Series Reference Manual  Busy: The DCSM waits for the CRC flag. If the DCSM receives a correct CRC status and is not busy, it will enter the Wait_S state. If it does not receive a correct CRC status or a timeout occurs while the DCSM is in the busy state, a CRC fail flag or timeout flag is generated.
Page 423: Hardware Flow Control
AT32A403A Series Reference Manual and then program the SDIO data control register (SDIO_DTCTRL): TFREN=1 (enable the SDIO card host to send data), TFRDIR=0 (from the controller to the card), TFRMODE=0 (block data transfer), DMAEN=1 (enable DMA), BLKSIZE=9 (512 bytes), and wait from SDIO_STS [10]=DTBLKCMPL.
Page 424: Sdio Registers
AT32A403A Series Reference Manual SDIO interrupts There is a pin with interrupt feature on the SD interface in order to enable the SD I/O card to interrupt the MultiMedia card/SD module. In 4-bit SD mode, this pin is SDIO_D1. The SD I/O interrupts are detected when the level is active.
Page 425: Sdio Clock Control Register (Sdio_ Clkctrl)
AT32A403A Series Reference Manual 23.4.2 SDIO clock control register (SDIO_ CLKCTRL) The SDIO_CLKCTRL register controls the SDIO_CK output clock. Abbr. Reset value Type Description Bit 31: 17 Reserved 0x0000 resd Kept at its default value. Clock division This field is set or cleared by software. It defines the clock...
Page 426: Sdio Argument Register (Sdio_Arg)
AT32A403A Series Reference Manual SDIO_CK can be stopped during the read wait period for SD I/O cards. In this case, the SDIO_ CLKCTRL register does not control the SDIO_CK. 23.4.3 SDIO argument register (SDIO_ARG) The SDIO_ARG register contains 32-bit command argument, which is sent to a card as part of a command.
Page 427: Sdio Command Response Register (Sdio_Rspcmd)
AT32A403A Series Reference Manual can vary according to the type of response. The software will distinguish the type of response according to the command sent. 23.4.5 SDIO command response register (SDIO_RSPCMD) The SDIO_RSPCMD register contains the command index of the last command response received. If...
Page 428: Sdio Data Control Register (Sdio_Dtctrl)
AT32A403A Series Reference Manual 23.4.9 SDIO data control register (SDIO_DTCTRL) The SDIO_DTCTRL register controls the data channel statue machine (DCSM). Abbr. Reset value Type Description Bit 31: 12 Reserved 0x00000 resd Kept at its default value. SD I/O enable functions This bit is set or cleared by software.
Page 429: Sdio Data Counter Register (Sdio_Dtcntr)
AT32A403A Series Reference Manual indicates block data transfer. 0: Disabled 1: Enabled Data transfer direction selection This bit is set or cleared by software. If this bit is set, data transfer is from a card to a controller; if this bit is cleared,...
Page 430: Sdio Clear Interrupt Register (Sdio_Intclr)
AT32A403A Series Reference Manual used as DMA request. Transmit BUF half empty: At least 8 words can be written to the BUF. This flag bit Bit 14 TXBUFH can be used as DMA request. Data receive in progress Bit 13...
Page 431: Sdio Interrupt Mask Register (Sdio_Inten)
AT32A403A Series Reference Manual 23.4.13 SDIO interrupt mask register (SDIO_INTEN) The SDIO_INTEN register determines which status bit generates an interrupt by setting the corresponding bit. Abbr. Reset value Type Description Bit 31: 23 Reserved 0x000 resd Kept at its default value.
Page 432 AT32A403A Series Reference Manual 1: Enabled Data transmit acting interrupt enable This bit is set or cleared by software to enable/disable the Data transmit acting interrupt. Bit 12 DOTXIEN 0: Disabled 1: Enabled Command acting interrupt enable This bit is set or cleared by software to enable/disable the Command acting interrupt.
Page 433: Sdiobuf Counter Register (Sdio_Bufcntr)
AT32A403A Series Reference Manual 1: Enabled Data CRC fail interrupt enable This bit is set or cleared by software to enable/disable the Data CRC fail interrupt. Bit 1 DTFAILIEN 0: Disabled 1: Enabled Command CRC fail interrupt enable This bit is set or cleared by software to enable/disable the Command CRC fail interrupt.
Page 434: Universal Serial Bus Full-Seed Device Interface (Usbfs)
AT32A403A Series Reference Manual 24 Universal serial bus full-seed device interface (USBFS) 24.1 USBFS introduction The USBFS implements the USB2.0 full-speed protocols. At the bus speed of 12 Mb/s, it supports control transfer, bulk transfer, synchronous transfer and interrupt transfer, as well as USB suspend/resume.
Page 435: Endpoint Configuration
AT32A403A Series Reference Manual 24.3.2 Endpoint configuration The USBFS supports up to 8 bidirectional and 16 unidirectional endpoints (8 IN and 8 OUT). Each point has its corresponding USBFS endpoint n register (USBFS_EPTn) that is used to store the endpoint status.
Page 436: Double-Buffered Endpoints
AT32A403A Series Reference Manual describe the buffer and data length of the endpoint receive/transmit. The structure of a regular endpoint register buffer description field is shown as follows (dual buffer description table is detailed in the next section): Endpoint n:...
Page 437: Sof Output
AT32A403A Series Reference Manual RnLEN_1 SBUF=0, USBFS uses RnADDR_1 and RnLEN_1, while the user application uses RnADDR_0 and RnLEN_0 Double-buffered IN endpoints: SBUF corresponds to bit 14 in the USB_EPTn  SBUF=1, USBFS uses TnADDR_0 and TnLEN_0, while the user application uses TnADDR_1 and...
Page 438: Usbfs Endpoint N Register (Usbfs_Eptn), N=[0
AT32A403A Series Reference Manual USBFS_EPT4 0x10 0x0000 USBFS_EPT5 0x14 0x0000 USBFS_EPT6 0x18 0x0000 USBFS_EPT7 0x1C 0x0000 USBFS_CTRL 0x40 0x0003 USBFS_INTSTS 0x44 0x0000 USBFS_SOFRNUM 0x48 0x0XXX USBFS_DEVADDR 0x4C 0x0000 USBFS_BUFTBL 0x50 0x0000 USBFS_CFG 0x60 0x0000 USBFS_TnADDR [USB_BUFTBL] x 2 + n x 16...
Page 439: Usbfs Control Register (Usbfs_Ctrl)
AT32A403A Series Reference Manual USB endpoint extend function is used for Bulk and Control transfers. For Bulk transfer, this bit is set to indicate that double-buffered is enabled. For Control transfer, if this bit is set, it detects whether the data length in the SETUP transaction is 0 or not, a STALL is returned if the value is not 0.
Page 440: Usbfs Interrupt Status Register (Usbfs_Intsts)
AT32A403A Series Reference Manual Kept at its default value. Bit 7: 5 Reserved resd Generate Resume request In suspend mode, the software can set this bit to send a Bit 4 GRESUME resume signal to the host in order to wake up it. It must be cleared between 10ms and 15ms.
Page 441: Usbfs Sof Frame Number Register (Usbfs_Sofrnum)
AT32A403A Series Reference Manual 0: Reset value 1: No SOF has been received for more than 1ms. Kept at its default value. Bit 7: 5 Reserved resd IN/Out transaction When TC complete interrupt is generated, this bit is used to indicate whether IN/OUT transaction has been...
Page 442: Usbfs Transmission Buffer First Address Register (Usbfs_ Tnaddr)442
AT32A403A Series Reference Manual 0: No SOF pulse output 1: SOF pulse output to the pin 24.5.8 USBFS transmission buffer first address register (USBFS_TnADDR) Abbr. Reset value Type Description Transmission buffer first address This field indicates the start address of the buffer where...
Page 443: Hick Auto Clock Calibration (Acc)
AT32A403A Series Reference Manual 25 HICK auto clock calibration (ACC) 25.1 ACC introduction HICK auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks.
Page 444: Functional Description
AT32A403A Series Reference Manual 25.4 Functional description Auto clock calibration (HICK ACC), which uses the SOF signal (1 ms of period) generated as a reference signal, implements the sampling and calibration for the HICK clocks. In particular, the HICK clock frequency can be calibrated to a precision of ±0.25% so as to meet the needs of the high-precision clock...
Page 445: Principle
AT32A403A Series Reference Manual Figure 25-2 ACC block diagram CRM_HICKCAL HICKCAL CALON CRM_HICKTRIM HICKTRIM 控制寄存器(CR） STEP ENTRIM ACC_HICKCAL USB_SOF CALIBRATION CONTROL ACC_HICKTRIM HICKCLK CALRDY INTERRUPT RSLOST CONTROL CALRDYIEN EIEN 25.5 Principle USB_SOF period signal: 1ms of period must be accurate, which is a prerequisite of the normal operation of an auto calibration module.
Page 446: Acc Registers
AT32A403A Series Reference Manual Return: After cross operation is completed, the actual value closest to C2 can be obtained by comparing the difference (calculated as absolute value) between the actual sampling value and C2 before and after crossing C2 so as to get the best calibration value HICKCAL or HICKTRIM.
Page 447: Control Register 1 (Acc_Ctrl1)
AT32A403A Series Reference Manual CALON=1. Internal high-speed clock calibration ready 0: Internal 8MHz oscillator calibration is not ready 1: Internal 8MHz oscillator calibration is ready Note: This bit is set by hardware to indicate that internal Bit 0 CALRDY 8MHz oscillator has been calibrated to the frequency closest to 8MHz.
Page 448: Control Register 2 (Acc_Ctrl2)
AT32A403A Series Reference Manual 25.6.3 Control register 2 (ACC_CTRL2) Abbr. Reset value Type Description Forced to 0 by hardware Bit 31: 14 Reserved 0x00000 resd Internal high-speed auto clock trimming This field is read only, but not written. Internal high-speed clock is adjusted by ACC module, which is added to the ACC_HICKCAL[7: 0] bit.
Page 449: Compare Value 3 (Acc_C3)
AT32A403A Series Reference Manual 25.6.6 Compare value 3 (ACC_C3) Abbr. Reset value Type Description Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware Compare 3 This value is the upper boundary for triggering calibration. When the number of clock sampled by ACC in 1ms period...
Page 450: Debug (Debug)
AT32A403A Series Reference Manual 26 Debug (DEBUG) 26.1 Debug introduction ® Cortex -M4F core provides powerful debugging features including halt and single step support, as well as trace function that is used for checking the details of the program execution. The debug features are implemented with two interfaces: serial wire debug (SWD) and JTAG debug port.
Page 451: Debug Registers
AT32A403A Series Reference Manual Table 26-2 Trace function mode TRACE PB3/JTDO/TR PE2/TRAC PE3/TRAC PE4/TRAC PE5/TRACE PE6/TRAC _MODE[1: 0] ACESWO ED[0] ED[1] D[2] ED[3] Asynchronous TRACES Released (can be used as general-purpose I/Os) trace Synchronous TRAC TRAC Released (can be used as general-...
Page 452: Debug Control Register (Debug_Ctrl)
AT32A403A Series Reference Manual 26.4.2 DEBUG control register (DEBUG_CTRL) This register is asynchronously reset by POR Reset (not reset by system reset). It can be written by the debugger under reset. Abbr. Reset value Type Description C3 pause control bit...
Page 453 AT32A403A Series Reference Manual TMR4 pause control bit 0: Work normally Bit 13 TMR4_PAUSE 1: Timer is disabled TMR3 pause control bit 0: Work normally Bit 12 TMR3_PAUSE 1: Timer is disabled TMR2 pause control bit 0: Work normally Bit 11...
Page 454: Revision History
AT32A403A Series Reference Manual 27 Revision history Document Revision History Date Version Revision Note Initial release. 2023.07.10 2.00 2023.07.10 Page 454 Rev 2.00...
Page 455 No license, express or implied, to any intellectual property rights is granted under this document. If any part of this document deals with any third party products or services, it shall not be deemed a license granted by ARTERY for the use of such third party products or services, or any intellectual property contained therein, or considered as a warranty regarding the use in any manner of such third party products or services or any intellectual property contained therein.

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