ARTERY AT32A403AVCT7 Manuals
Manuals and User Guides for ARTERY AT32A403AVCT7. We have 1 ARTERY AT32A403AVCT7 manual available for free PDF download: Reference Manual
ARTERY AT32A403AVCT7 Reference Manual (455 pages)
ARM-based 32-bit Cortex-M4F MCU+FPU with 256 to 1024 KB Flash, sLib, USB, 2 CANs, 17 timers, 3 ADCs, 20 communication interfaces
Brand: ARTERY
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Category: Computer Hardware
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Size: 12 MB
Table of Contents
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Bit Band33
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Reset38
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Flash Memory42
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SRAM Memory43
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Introduction46
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Por/Lvr46
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Power Domain48
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Clock52
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System Clock53
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Interrupts54
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Reset54
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System Reset54
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Unlock/Lock75
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Unlock/Lock79
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Introduction93
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Introduction98
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IOMUX Registers109
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EXINT Registers123
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Introduction125
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Main Features125
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Arbiter127
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Errors128
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Interrupts128
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DMA Registers131
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CRC Introduction139
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CRC Registers140
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C Interface142
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I 2 C Interface143
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Smbus154
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C Debug Mode156
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I 2 C Registers157
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Mode Selector166
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Introduction166
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Introduction171
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Configuration171
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Transmitter172
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Receiver173
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I/O Pin Control176
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USART Registers176
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SPI Introduction182
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SPI Description182
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Crc186
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DMA Transfer187
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Transmitter187
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Receiver188
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Motorola Mode188
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Interrupt191
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IO Pin Control191
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Precautions192
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S Introduction192
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S Full-Duplex193
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DMA Transfer198
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Interrupts199
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IO Pin Control200
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SPI Registers201
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Mode)201
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Mode)204
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Timer206
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Counting Clock207
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Counting Mode207
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Debug Mode209
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Counting Clock213
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Counting Mode216
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Debug Mode227
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Tmrx Registers227
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Counting Clock240
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Counting Mode242
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Debug Mode249
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Counting Clock264
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Tmrx_Ch1266
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Tmrx_Ch2266
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Counting Mode267
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Debug Mode281
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Debug Mode299
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WWDT Registers299
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WDT Introduction301
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Debug Mode302
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WDT Registers302
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RTC Introduction304
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RTC Structure304
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RTC Interrupts306
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RTC Registers307
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BPR Introduction310
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BPR Registers310
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ADC Introduction314
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ADC Structure314
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Trigger317
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Sequence Mode319
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Repetition Mode320
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Partition Mode320
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Data Management321
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Data Alignment321
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Data Read321
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Voltage Monitor321
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Data Management322
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ADC Registers325
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DAC Introduction336
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Design Tips336
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Trigger Events337
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DAC Registers339
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Can344
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CAN Introduction344
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Baud Rate344
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Design Tips348
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Operating Modes349
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Test Modes349
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Error Management354
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CAN Registers355
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(Can_Rfcx) (X=0368
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XMC Introduction371
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XMC Architecture372
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Block Diagram372
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Address Mapping373
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Nor/Psram374
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Operation Mode374
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Access Mode375
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Multiplexed Mode388
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Synchronous Mode390
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Nand392
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Operation Mode392
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Access Timings393
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ECC Computation395
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XMC Registers395
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SDIO Interface404
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Erase408
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Commands411
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Response Formats415
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SDIO Adapter418
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Data BUF422
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SDIO Registers424
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SDIO Response 1427
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USB Buffer435
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SOF Output437
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Suspend/Resume437
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USB Interrupts437
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USBFS Registers437
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ACC Introduction443
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Main Features443
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Principle445
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ACC Registers446
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Debug (DEBUG)450
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Debug and Trace450
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I/O Pin Control450
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DEBUG Registers451
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Revision History454
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