Asus RS720A-E12 Series User Manual page 140

Corrector Branch Predictor [Disabled]
Enabling for branch heavy codes may reduce conditional branch mispredicts.
Configuration options: [Disabled] [Enabled]
CPU Speculative Store Modes [Auto]
[Balanced]
[More Speculative]
[Less Speculative]
[Auto]
PAUSE Delay [Auto]
Number of cycles thread will be idle after a PAUSE instruction.
Configuration options: [Auto] [Disabled] [16 cycles] [32 cycles] [64 cycles] [128 cycles]
DF Common Options
Memory Addressing
Allows you to configure memory addressing options.
ACPI
Allows you to configure ACPI options.
Link
Allows you to configure Link settings.
SDCI
Allows you to configure SDCI settings.
DF Watchdog Timer Interval [Auto]
Allows you to set the Data Fabric watchdog timer interval.
Configuration options: [Auto] [41ms] [166ms] [334ms] [669ms] [1.34 seconds] [2.68
seconds] [5.36 seconds]
Disable DF to external IP SyncFloodPropagation [Auto]
Allows you to enable or disable SyncFlood to UMC and downstream slaves.
Configuration options: [Sync flood disabled] [Sync flood enabled] [Auto]
Sync Flood Propagation to DF Components [Auto]
Configuration options: [Sync flood disabled] [Sync flood enabled] [Auto]
Freeze DF module queues on error [Auto]
Configuration options: [Disabled] [Enabled] [Auto]
CC6 Memory Region Encryption [Auto]
Configuration options: [Disabled] [Enabled] [Auto]
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Store instructions may delay sending out their invalidations to
remote cacheline copies when the cacheline is present but not
in a writable state in the local cache.
Store instructions will send out invalidations to remote cacheline
copies as soon as possible.
Store instructions may delay sending out their invalidations to
remote cacheline copies when the cacheline is not present in
the local cache or not in a writable state in the local cache.
Default setting is applied.
Chapter 5: BIOS Setup