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Specifications
CPU Specifications
Main Control Element
Programming Method
Instruction Length
Number of Instructions
Execution Time
Memory Capacity
I/O bits
IR bits
SR bits
TR bits
HR bits
AR bits
LR bits
Timers/Counters
DM words
RUN Output
Memory Protection
Self-diagnostic Functions
Program Check
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MPU, CMOS, LS-TTL
Ladder diagram
1 address/instruction, 1 to 4 words/instruction
145 (12 basic instructions + 133 special instructions)
C200H-CPU11 159 (12 basic instructions + 147 special instructions)
Basic instructions: 0.75 to 2.25 ms
6,974 words (with 8k-word memory)
480
I/O Units mounted
(00000 through 02915)
to Remote I/O Slave
Racks 800 (05000
3,296
through 09915)
(03000 through 23515)
312 (23600 through 25507)
8 (TR 0 through 7)
1,600 (HR 0000 through 9915)
448 (AR 0000 through 2715
1,024 (LR 0000 through 6315)
512 (TIM/CNT 000 through 511)
TIMHs: 0 through 99.99 s
Read/write: 1,000 (DM 0000 through 0999)
Read only: 1,000 (DM 1000 through 1999)
Contacts are closed while PC is in RUN mode and operating.
Max. switching capacity:
2A 250 VAC (resistive load)
0.5 A 250 VAC (inductive load, cos of phase angle = 0.4)
2 A 24 VDC
Status of HR bits, AR bits, preset value of counters (CNT), and contents of data memory
(DM) are retained during power failure. Length of memory protection depends on the
Memory Pack model being used (refer to Section 2-6 Memory Packs ).
CPU failure (watchdog timer)
Cycle time error
I/O bus failure
Remote I/O error, etc.
Program check (executed on start of RUN operation):
END missing
(Program can be checked by Programming Console or GPC at three levels.)
Special instructions: 34 to 724 ms
Special I/O Units
Optical I/O Units
1,600
and I/O Terminals
512
(10000 through
(20000 through
19915)
23115)
TIMs: 0 through 999.9 s
CNT: 0 through 9999 counts
DM area is in Memory Pack.
Battery failure
Memory failure
Host Link error
Instruction errors
Appendix B
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