Advanced Dram Control - JETWAY For Socket 370 User Manual

Advanced DRAM Control 1

Please refer to section 3-6-1
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
Memory Parity Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
3-6-1 Advanced DRAM Control
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Auto Configuration
SDRAM RAS Active Time
SDRAM RAS Precharg Time
RAS to CAS Delay
Dram Background Command
LD-Off Dram RD/WR Cycles
Write Recovery Time
VCM ACCT – ACT/REF Delay
Early CKE Delay 1T Cntrl
Early CKE Delay Adjust
Mem Command Output Time
SDRAM/VCM CAS Latency
Advanced DRAM Control 1
Auto
5T
3T
4T
Delay 1T
Delay 1T
2T
9T
Normal
7ns
Delay 1T
3T
31
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