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iWave Zynq Ultrascale+ MPSoC Hardware User's Manual

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Zynq Ultrascale+ MPSoC SBC Hardware User Guide
iW-RainboW-G36S
Zynq Ultrascale+ MPSoC SBC
Hardware User Guide
REL0.1
iWave Systems Technologies Pvt. Ltd.
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Summary of Contents for iWave Zynq Ultrascale+ MPSoC

  • Page 1 Zynq Ultrascale+ MPSoC SBC Hardware User Guide iW-RainboW-G36S Zynq Ultrascale+ MPSoC SBC Hardware User Guide REL0.1 iWave Systems Technologies Pvt. Ltd. Page 1 of 88 Arrow.com. Downloaded from...
  • Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL0.1 iWave Systems Technologies Pvt.
  • Page 3 No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 4: Table Of Contents

    List of Acronyms ............................8 Terminlogy Description ..........................10 References..............................10 ARCHITECTURE AND DESIGN ..........................11 Zynq Ultrascale+ MPSoC SBC Block Diagram ....................11 Zynq Ultrascale+ MPSoC SBC Features ....................... 12 Zynq Ultrascale+ MPSoC ..........................16 2.3.1 MPSoC Power ............................18 2.3.2 MPSoC Reset ............................
  • Page 5 2.12.1.2 PL IOs –HD BANK44 ........................73 2.12.2 Power ..............................77 2.13 Zynq Ultrascale+ MPSoC PS Pin Multiplexing on Board to Board Connectors ..........78 TECHNICAL SPECIFICATION ..........................80 Power Input Requirement.......................... 80 Power Output Specification ........................81 3.2.1 Power Consumption ..........................81 Environmental Characteristics ........................
  • Page 6 Figure 21: Board to Board Connector3 ........................66 Figure 22: Input Power Jack ............................80 Figure 23: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Top View ............83 Figure 24: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Bottom View ............. 83 Figure 25: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Side View............
  • Page 7 Table 12: Board to Board Connector2 Pinout ......................54 Table 13: Board to Board Connector3 Pinout ......................67 Table 14: PS IOMUX on Zynq Ultrascale+ MPSoC SBC ....................78 Table 15: Power Input Requirement .......................... 80 Table 16: Power Output Specification ........................81 Table 17: Power Consumption¹...

  • Page 8: Introduction

    1. INTRODUCTION Purpose This document is the Hardware User Guide for the Zynq Ultrascale+ MPSoC Single Board Computer based on the Xilinx Zynq Ultrascale+ MPSoC . This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the Zynq Ultrascale+ MPSoC SBC from a Hardware Systems perspective.
  • Page 9 Zynq Ultrascale+ MPSoC SBC Hardware User Guide Acronyms Abbreviations NPTH Non Plated Through hole Printed Circuit Board PMIC Power Management Integrated IC Plated Through hole Programmable Logic Processing System RGMII Reduced Gigabit Media Independent Interface Real Time Clock Single Board Computer...

  • Page 10: Terminlogy Description

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Terminlogy Description In this document, wherever Signal Type is mentioned, below terminology is used. Table 2: Terminology Terminology Description Input Signal Output Signal Bidirectional Input/output Signal CMOS Complementary Metal Oxide Semiconductor Signal LVDS...

  • Page 11: Architecture And Design

    GTH Transceiver block is supported in ZU4 & ZU5 MPSoC with data rates up to 12.5Gb/s. GTH transceiver block is not supported in ZU2 & ZU3 MPSoC. “ “ This symbol indicates Hardware assembly options available in the board and by default which option is support ed. Contact iWave to support other assembly option. Figure 1: Zynq Ultrascale+ MPSoC SBC Block Diagram REL0.1...

  • Page 12: Zynq Ultrascale+ Mpsoc Sbc Features

    Real Time Processor (up to 600MHz) and Mali™-400 MP2 Graphics Processor and H.264/H.265 Video Codec. ➢ Compatible Zynq Ultrascale+ MPSoC Family (SFVC784) – ZU2EG, ZU3EG, ZU4EG, ZU5EG Programming Logic with up to 256K Logic cells and Processing System with integrated Quad-core ARM Cortex-A53 MPCore Application processor (up to 1.5GHz), Dual-core ARM Cortex-R5 MPCore...
  • Page 13 Zynq Ultrascale+ MPSoC SBC Hardware User Guide Features from PS-GTR Transceiver • Display Port Connector (Dual Lane upto 4K@30) • Dual USB3.0 Type A Jack • M.2 Key B Connector with SATA, PCIex1 and USB3.0 Features from PL-GTH Transceiver •...
  • Page 14 Zynq Ultrascale+ MPSoC SBC Hardware User Guide Board to Board Connector2 Interfaces (60pin) From PL Block • PL IOs - HP Bank64 ➢ Upto 7 LVDS IOs/14 Single ended (SE) IOs o Upto 1 GC Global Clock Input pins (LVDS/SE) o Upto 5 ADC Input pins (Differential/Single Ended) o Variable IO voltage support from 1.2V to 1.8V...
  • Page 15 PL-GTH are not supported in ZU3 & ZU2 Zynq Ultrascale+MPSoC based SBC. In Zynq Ultrascale+ MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So either SFP+ or SDI IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI IN & Out.

  • Page 16: Zynq Ultrascale+ Mpsoc

    The Zynq Ultrascale+ MPSoC SBC is based on Xilinx Zynq Ultrascale+ MPSoC with SFVC784 package. Zynq Ultrascale+ MPSoC family integrates Processing system (PS) and Xilinx programmable logic (PL) in a single device. MPSoC’s Processing system includes feature-rich Quad-core ARM Cortex-A53 MPCore up to 1.5 GHz of Application processor,...

  • Page 17: Figure 3: Zynq Ultrascale+ Mpsoc Devices Comparison

    Figure 3: Zynq Ultrascale+ MPSoC Devices Comparison The Zynq Ultrascale+ MPSoC’s PS has 78 dedicated I/O pins referred as MIO (Multiplexed I/O) for the PS peripheral interfaces. These 78 MIO pins are divided into three banks (PS BANK500, 501 & 502) and each bank includes 26 device pins.

  • Page 18: Mpsoc Power

    I/Os organized in banks of 24pins. In Zynq Ultrascale+ MPSoC PL, each bank supports four global clock (GC or HDGC) input pin pairs. GC pins have direct access to the global clock buffers, MMCMs and PLLs of the same Bank. HDGC pins are from HD I/O banks and have direct access only to the global clock buffers.

  • Page 19: Mpsoc Reset

    2.2.2 MPSoC Reset The Zynq Ultrascale+ MPSoC SBC uses PMIC’s Reset output (nRESET) for PS Power On Reset and connected to PS_POR_B pin of MPSoC. Also it supports warm reset input from Reset Switch (SW2) and connected to PS_SRST_B pin of MPSoC.

  • Page 20: Mpsoc Configuration & Status

    2.2.4 MPSoC Configuration & Status The Zynq Ultrascale+ MPSoC uses multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. Upon reset, device executes code out of on-chip ROM and copies the first stage boot loader (FSBL) from the boot device to the on-chip RAM.

  • Page 21: Mpsoc System Monitor/Adc

    2.2.6 MPSoC System Monitor/ADC The Zynq Ultrascale+ MPSoC contain two System Monitor block (SYSMONE4), one in the PL (PL SYSMON) and another in the PS (PS SYSMON). It is used to enhance the overall safety, security and reliability of the system by monitoring the physical environment via on-chip power supply and temperature sensors.

  • Page 22: Memory

    2.4.1 DDR4 SDRAM for PS The Zynq Ultrascale+ MPSoC SBC supports 64bit, 2GB DDR4 RAM memory for MPSoC’s PS. Four 16 bit, 512MB DDR4 SDRAM ICs are used to support a total on board RAM memory of 2GB. These DDR4 devices operates at 1.2 voltage level.

  • Page 23: Micro Sd Connector (Optional)

    The memory card voltage level translator’s voltage selection is controlled through PS GPIO (PS_MIO43_501) pin from Zynq Ultrascale+ MPSoC PS. If PS_MIO43_501 is set to low, then 3.3V IO level is selected for SD1 signals to SD connector. If PS_MIO43_501 is set to high, then 1.8V IO level is selected for SD1 signals to SD connector.

  • Page 24: Fearures From Ps Block

    GEM0 and GEM3 RGMII interface of MPSoC is used for dual Ethernet support. The GEM0 & GEM3 MAC is integrated in the Zynq Ultrascale+ MPSoC PS and connected to the external individual Gigabit Ethernet PHY “AR8031” on SBC. Also both the Ethernet port supports Speed (Yellow) and Link/Activity (Green) LED indications on correponding RJ45 Magjack port.

  • Page 25: Wlan & Bt Module With Antenna Connector

    Note: In Zynq Ultrascale+ MPSoC SBC, SD1 signals from MPSoC is shared with WLAN module and MicroSD connector. So either WLAN or Micro SD connector can be supported. By default WLAN module is supported in SBC. Contact iWave to support Micro SD connector.

  • Page 26: Debug Uart Header

    The Zynq Ultrascale+ MPSoC SBC supports debug interface through UART0 interface of Zynq Ultrascale+ MPSoC PS. This UART0 signals from Zynq Ultrascale+ MPSoC PS is connected to Debug UART Header(J14) through 1.8V to 3.3V Level Translator. This UART Header can be used for Debug purpose which is physically located at the top of the board as shown below.

  • Page 27: Features From Ps-Gtr

    The Zynq Ultrascale+ MPSoC SBC supports Display port connector through PS-GTR Lanes of Zynq Ultrascale+ MPSoC PS. PS-GTR Lane3 & Lane2 from Zynq Ultrascale+ MPSoC PS is connected to Display port connector to support dual lane display port. The Zynq Ultrascale+ MPSoC can support upto 4K@30 resolution.

  • Page 28: Dual Usb3.0 Type A Jack

    2.6.2 Dual USB3.0 Type A Jack The Zynq Ultrascale+ MPSoC SBC support two Super Speed USB3.0 Host ports through dual stack USB 3.0 Type A connector. The PS-GTR Lane1 of Zynq Ultrascale+ MPSoC is used for USB3.0 interface through 4port USB3.0 HUB “USB5744”...

  • Page 29: Key B Connector With Sata & Usb3.0

    USB3.0 HUB. MPSoC’s SATA supports SATA Specification revision 3.1 with Gen1(1.5Gbps), Gen2(3Gbps) & Gen3(6Gbps) datarates. This M.2 connector (J27) is physically located at the bottom of the board as shown below. * In Zynq Ultrascale+ MPSoC SBC, PS-GTR lane0 can be used for either SATA or PCIe Interface through M.2 Key-B Connector.

  • Page 30: Table 5: M.2 Connector Pin Assignment

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Table 5: M.2 Connector Pin Assignment MPSoC Pin MPSoC MPSoC Signal Type/ Description Name Name Bank Pin No Termination CONFIG_3 M.2 Configuration Pin 3. VCC_3V3 3.3V Supply Voltage. Power Power Ground. VCC_3V3 3.3V Supply Voltage.
  • Page 31 Zynq Ultrascale+ MPSoC SBC Hardware User Guide MPSoC Pin MPSoC MPSoC Signal Type/ Description Name Name Bank Pin No Termination PERN1/USB3.1 I, DIFF USB3.0 Port3 Receiver pair _RX-/SSIC_RX- negative. This pin is connected to 23 pin of 4-Port USB HUB(U33).
  • Page 32 Zynq Ultrascale+ MPSoC SBC Hardware User Guide MPSoC Pin MPSoC MPSoC Signal Type/ Description Name Name Bank Pin No Termination CLKREQ# IO, 3.3V PCIe Clock Request. CMOS/ This signal is configuring from 10K PU PMIC GPIO3 (U14). REFCLKN O, DIFF 100 MHz PCIe Device negative Reference Clock.

  • Page 33: Features From Pl-Gth

    Important Note: In Zynq Ultrascale+ MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So either SFP+ or SDI IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI IN &...

  • Page 34: Hdmi Output Connector

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide 2.7.2 HDMI Output Connector The Zynq Ultrascale+ MPSoC SBC supports one HDMI Output through HDMI TypeA connector (J11). The Zynq Ultrascale+ MPSoC’s PL GTH Bank224 Channel0 to Channel2 transmitter is directly connected to HDMI Retimer chip (SN65DP159RGZR) and then connected to HDMI Out Connector for HDMI out.

  • Page 35: Sfp+ Connector

    Important Note: In Zynq Ultrascale+ MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So either SFP+ or SDI IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI IN &...

  • Page 36: Table 6: Sfp+ Connector Pin Assignment

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Table 6: SFP+ Connector Pin Assignment MPSoC Pin MPSoC MPSoC Signal Type/ Description Name Name Bank Pin No Termination VEET1 Power Ground. TFAULT I, LVTTL/ Module Transmitter Fault. 4.7K PU TDIS O, LVTTL/ Transmitter Disable.

  • Page 37: 12G Sdi In (Optional)

    Important Note: In Zynq Ultrascale+ MPSoC SBC, GTH Transceiver Channel3 is shared with SFP+ and SDI In & Out. So either SFP+ or SDI IN & Out only can be supported. By default SFP+ is supported in SBC. Contact iWave to support SDI IN &...

  • Page 38: Additional Features

    Important Note: In Zynq Ultrascale+ MPSoC SBC, OUT3 & 3b from clock synthesizer is optionally connected to GTREFCLK1P & N_224 of Zynq Ultrascale+ MPSoC V6 & V5 . By default GTREFCLK1P & N_224 of V6 & V5 is connected from HDMI IN Connector(J9).

  • Page 39: Figure 14: Jtag Header

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Figure 14: JTAG Header Table 8: JTAG Header Pinout Signal Type/ Pin No Pin Name Description Termination VCC_3V3 O, 3.3V Power Supply Voltage. Power Ground. JTAG_TMS I, 3.3V LVCMOS/ JTAG Test Mode Select.

  • Page 40: Fan Header

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide 2.8.3 Fan Header The Zynq Ultrascale+ MPSoC SBC supports a Fan Header (J12) to connect cooling Fan if required. The Fan Header (J12) is physically located on topside of the SBC as shown below.

  • Page 41: Rtc Header

    The Zynq Ultrascale+ MPSoC SBC supports Coin Cell Header to connect “2032” series 3V coin cell through external cable. This coin cell voltage is connected to Zynq Ultrascale+ MPSoC SBC for RTC back up voltage when VCC main power is off. This Coin Cell Header (J6) is physically located at the top of the board as shown below.

  • Page 42: Power On/Off Switch

    Figure 17: Power ON/OFF Switch 2.8.6 Reset Switch The Zynq Ultrascale+ MPSoC SBC supports Push button switch (SW2) to reset the Zynq Ultrascale+ MPSoC CPU. Reset signal of Zynq Ultrascale+ MPSoC is directly connected from Reset Push button switch. This Reset Push button switch (SW2) is physically located at the top of the board as shown below.

  • Page 43: Board To Board Connector1

    The Zynq Ultrascale+ MPSoC SBC supports three 60 pin high speed ruggedized terminal strip connectors, Three 60pin High performace High Density connector for interfaces expansion. All the effort is made in Zynq Ultrascale+ MPSoC SBC design to provide the maximum interfaces of Zynq Ultrascale+ MPSoC to SBC by adding these three Board to Board Connectors.

  • Page 44: Table 11: Board To Board Connector1 Pinout

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Table 11: Board to Board Connector1 Pinout Signal Name B2B-1 Pin B2B-1 Pin Signal Name PL_AE5_LVDS64_L12P_GC PL_C11_LVDS45_L9P PL_AF5_LVDS64_L12N_GC PL_B10_LVDS45_L9N PL_B11_LVDS45_L10P PL_AF6_LVDS64_L11N_GC PL_A10_LVDS45_L10N PL_AF7_LVDS64_L11P_GC PL_AD5_LVDS64_L13P_GC SPI0_MISO(PS_MIO4_500) PL_AD4_LVDS64_L13N_GC SPI0_MOSI(PS_MIO5_500) SPI0_SS0(PS_MIO3_500) PL_AG5_LVDS64_L10N_QBC SPI0_SCLK(PS_MIO0_500) PL_AG6_LVDS64_L10P_QBC I2C1_SCL(PS_MIO24_500) I2C1_SDA(PS_MIO25_500)

  • Page 45: Ps Interfaces

    2.9.1.1 SPI Interface The Zynq Ultrascale+ MPSoC SBC supports one SPI interface with one chip select on Board to Board Connector1. The SPI0 controller of MPSoC’s PS is used for SPI interface through MIO pins. It can function in master mode, slave mode or multi-master mode and supports full-duplex operation.

  • Page 46: I2C Interface

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank64 signals are routed as LVDS IOs to Board to Board Connector1. Even though PL Bank64 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector1 pins 1, 3, 7, 9, 13, and 15 are HDGC Global Clock Input capable pins of PL Bank64.
  • Page 47 Zynq Ultrascale+ MPSoC SBC Hardware User Guide For more details on PL HP Bank64 pinouts on Board to Board Connector1, refer the below table. B2B1 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No...
  • Page 48 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B1 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AD4_LVDS64_ IO_L13N_T2L_N1_ IO, 1.8V LVDS Bank64 IO13 L13N_GC GC_QBC_64 differential negative. Same configured as HDGC Global...
  • Page 49 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B1 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AG9_LVDS64_ IO_L7P_T1L_N0_Q IO, 1.8V LVDS PL Bank64 IO7 differential L7P_QBC BC_AD13P_64 positive. Same configured as PLSYSMON...
  • Page 50 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B1 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AB8_LVDS64_ IO_L3P_T0L_N4_AD IO, 1.8V LVDS PL Bank64 IO3 differential 15P_64 positive. Same configured as PLSYSMON differential analog input15 positive or Single ended I/O.

  • Page 51: Ios - Hd Bank45

    2.9.2.2 PL IOs – HD BANK45 The Zynq Ultrascale+ MPSoC SBC supports 4 Single Ended (SE) IOs on Board to Board Connector1 from MPSoC’s PL High-Density (HD) Bank45. Upon these 4 SE IOs are available. PL Bank45 signals are routed as Single Ended IOs to Board to Board Connector1.

  • Page 52: Power

    I/O. 2.9.3 Power In Zynq Ultrascale+ MPSoC SBC, 5V and 1.8V powers are fed to Board to Board Connector1. Also in Board to Board Connector1, Ground pins are distributed throughout the connector for better performance. For more details on Power control & Ground pins on Board to Board Connector1, refer the below table.

  • Page 53: Board To Board Connector2

    The Zynq Ultrascale+ MPSoC SBC supports three 60 pin high speed ruggedized terminal strip connectors, Three 60pin High performance High Density connector for interfaces expansion. All the effort is made in Zynq Ultrascale+ MPSoC SBC design to provide the maximum interfaces of Zynq Ultrascale+ MPSoC to SBC by adding these three Board to Board Connectors.

  • Page 54: Table 12: Board To Board Connector2 Pinout

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Table 12: Board to Board Connector2 Pinout Signal B2B-2 Pin B2B-2 Pin Signal PL_AG4_LVDS64_L19P_DBC PL_AH4_LVDS64_L19N_DBC PL_AF1_LVDS64_L24P PL_AG1_LVDS64_L24N PL_AB4_LVDS64_L15P PL_AB3_LVDS64_L15N PL_AB2_LVDS64_L17P PL_AC2_LVDS64_L17N PL_AB1_LVDS64_L18P PL_AC1_LVDS64_L18N PL_AD2_LVDS64_L16P_QBC PL_AD1_LVDS64_L16N_QBC PL_AC4_LVDS64_L14P_GC PL_AC3_LVDS64_L14N_GC PL_K14_LVDS46_L11P PL_J14_LVDS46_L11N PL_L14_LVDS46_L12P PL_L13_LVDS46_L12N PL_G15_LVDS46_L9P PL_G14_LVDS46_L9N...

  • Page 55: Interfaces

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank64 signals are routed as LVDS IOs to Board to Board Connector2. Even though PL Bank64 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector2 pins 15 and 16 are HDGC Global Clock Input capable pins of PL Bank64.
  • Page 56 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AG1_LVDS64_ IO_L24N_T3U_N11 IO, 1.8V LVDS Bank64 IO24 L24N differential negative. Same configured as Single ended I/O.
  • Page 57 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AC1_LVDS64_ IO_L18N_T2U_N11 IO, 1.8V LVDS Bank64 IO18 L18N _AD2N_64 differential negative. Same configured as PLSYSMON differential analog input2 negative or Single ended I/O.

  • Page 58: Ios -Hd Bank45

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank45 signals are routed as LVDS IOs to Board to Board Connector2. Even though PL Bank45 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector2 pins 47, 48, 51, 52, 53, 54, 55 and 56 are PLSYSMON auxiliary analog Input capable pins of PL Bank45.
  • Page 59 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_J12_LVDS45_L IO_L4P_AD12P_45 IO, 1.8V LVDS PL Bank45 IO4 differential positive. Same configured as PLSYSMON differential analog input12 positive or Single ended I/O.

  • Page 60: Ios -Hd Bank46

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank46 signals are routed as LVDS IOs to Board to Board Connector2. Even though PL Bank46 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector2 pins 27, 28, 37, 38, 41, 42, 43 and 44 are HDGC Global Clock Input capable pins of PL Bank46.
  • Page 61 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_L14_LVDS46_ IO_L12P_AD0P_46 IO, 1.8V LVDS Bank46 IO12 L12P differential positive. Same configured as PLSYSMON differential analog input0 positive or Single ended I/O.
  • Page 62 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_D15_LVDS46_ IO_L5P_HDGC_AD7 IO, 1.8V LVDS PL Bank46 IO5 differential L5P_GC P_46 positive. Same configured as HDGC Global...
  • Page 63 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_A14_LVDS46_ IO_L2N_AD10N_46 IO, 1.8V LVDS PL Bank46 IO2 differential negative. Same configured as PLSYSMON differential analog input10 negative or Single ended I/O.
  • Page 64 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B2 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_F15_LVDS46_ IO_L8P_HDGC_AD4 IO, 1.8V LVDS PL Bank46 IO8 differential L8P_HDGC P_46 positive. Same configured as HDGC Global...

  • Page 65: Power

    I/O. 2.10.2 Power In Zynq Ultrascale+ MPSoC SBC, 5V and 12V powers are fed to Board to Board Connector2. Also in Board to Board Connector2, Ground pins are distributed throughout the connector for better performance. For more details on Power control & Ground pins on Board to Board Connector2, refer the below table.

  • Page 66: Board To Board Connector3

    The Zynq Ultrascale+ MPSoC SBC supports three 60 pin high speed ruggedized terminal strip connectors, Three 60pin High performance High Density connector for interfaces expansion. All the effort is made in Zynq Ultrascale+ MPSoC SBC design to provide the maximum interfaces of Zynq Ultrascale+ MPSoC to SBC by adding these three Board to Board Connectors.

  • Page 67: Table 13: Board To Board Connector3 Pinout

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Table 13: Board to Board Connector3 Pinout Signal B2B-3 Pin B2B-3 Pin Signal PL_AE13_LVDS44_L4P PL_AF13_LVDS44_L4N PL_AE15_LVDS44_L1P PL_AE14_LVDS44_L1N PL_AD15_LVDS44_L5P_HDGC PL_AD14_LVDS44_L5N_HDGC PL_AB15_LVDS44_L8P_HDGC PL_AB14_LVDS44_L8N_HDGC PL_AC14_LVDS44_L6P_HDGC PL_AC13_LVDS44_L6N_HDGC PL_Y14_LVDS44_L10P PL_Y13_LVDS44_L10N PL_W14_LVDS44_L9P PL_W13_LVDS44_L9N PL_AA13_LVDS44_L7P_HDGC PL_AB13_LVDS44_L7N_HDGC PL_W12_LVDS44_L11P PL_W11_LVDS44_L11N PL_Y12_LVDS44_L12P PL_AA12_LVDS44_L12N...

  • Page 68: Interfaces

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank43 signals are routed as LVDS IOs to Board to Board Connector3. Even though PL Bank43 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector3 pins 41, 42, 43, 44, 53 and 54 are HDGC Global Clock Input capable pins of PL Bank43.
  • Page 69 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_Y9_LVDS43_L IO_L11P_AD1P_43 IO, 1.8V LVDS Bank43 IO11 differential positive. Same configured as PLSYSMON differential analog input1 positive or Single ended I/O.
  • Page 70 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AB11_LVDS43 IO_L8P_HDGC_AD4 AB11 IO, 1.8V LVDS PL Bank43 IO8 differential _L8P_HDGC P_43 positive. Same configured as HDGC Global...
  • Page 71 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AE10_LVDS43 IO_L4P_AD8P_43 AE10 IO, 1.8V LVDS PL Bank43 IO4 differential _L4P positive. Same configured as PLSYSMON...
  • Page 72 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AC12_LVDS43 IO_L6P_HDGC_AD6 AC12 IO, 1.8V LVDS PL Bank43 IO6 differential _L6P_HDGC P_43 positive. Same configured as HDGC Global...

  • Page 73: Ios -Hd Bank44

    MPSoC datasheet. In the Zynq Ultrascale+ MPSoC SBC, PL Bank44 signals are routed as LVDS IOs to Board to Board Connector3. Even though PL Bank44 signals are routed as LVDS IOs, these pins can be used as SE IOs if required. The Board to Board Connector3 pins 5, 6, 7, 8, 11, 12, 17, and 18 are HDGC Global Clock Input capable pins of PL Bank44.
  • Page 74 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AE15_LVDS44 IO_L1P_AD15P_44 AE15 IO, 1.8V LVDS PL Bank44 IO1 differential _L1P positive. Same configured as PLSYSMON...
  • Page 75 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AC14_LVDS44 IO_L6P_HDGC_44 AC14 IO, 1.8V LVDS PL Bank44 IO6 differential _L6P_HDGC positive. Same configured as HDGC Global...
  • Page 76 Zynq Ultrascale+ MPSoC SBC Hardware User Guide B2B3 MPSoC MPSoC MPSoC Signal Type/ Signal Name Description Pin No Pin Name Bank Pin No Termination PL_AA13_LVDS44 IO_L7P_HDGC_44 AA13 IO, 1.8V LVDS PL Bank44 IO7 differential _L7P_HDGC positive. Same configured as HDGC Global...

  • Page 77: Power

    I/O. 2.11.2 Power In Zynq Ultrascale+ MPSoC SBC, 5V and 12V powers are fed to Board to Board Connector3. Also in Board to Board Connector3, Ground pins are distributed throughout the connector for better performance. For more details on Power control & Ground pins on Board to Board Connector3, refer the below table.

  • Page 78: Zynq Ultrascale+ Mpsoc Ps Pin Multiplexing On Board To Board Connectors

    2.12 Zynq Ultrascale+ MPSoC PS Pin Multiplexing on Board to Board Connectors The Zynq Ultrascale+ MPSoC PS IO pins have many alternate functions and can be configured to any one of the altern The below table provides the details of PS pin connections on Zynq Ultrascale+ MPSoC SBC with selected pin function in Xilinx Vivado Design Suite.
  • Page 79 GEM1_TX_CLK eMMC _CLK CAN0_RX CAN0 PS_MIO39_501 GPIO39 GEM1_TXD0 CAN0_TX PS_MIO40_501 GPIO40 GEM1_TXD1 eMMC _CMD CAN1 PS_MIO41_501 GPIO41 GEM1_TXD2 eMMC_DATA0 iWave Systems Technologies Pvt. Ltd. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 80: Technical Specification

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide 3. TECHNICAL SPECIFICATION This section provides detailed information about the Zynq Ultrascale+ MPSoC SBC technical specification with Electrical, Environmental and Mechanical characteristics. Power Input Requirement The Zynq Ultrasclae+ MPSoC SBC is designed to work with 12V external power and uses on board voltage regulators for internal power management.

  • Page 81: Power Output Specification

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Power Output Specification The Zynq Ultrasclae+ MPSoC SBC shares different on-board power to Board to Board Connector 1, 2, and 3 for its Add- On Module power. Table 16: Power Output Specification Power Rail...

  • Page 82: Environmental Characteristics

    3.3.3 Electrostatic Discharge iWave’s Zynq Ultrascale+ MPSoC SBC is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SBC except at an electrostatic free workstation.

  • Page 83: Mechanicalcharacteristics

    MechanicalCharacteristics 3.4.1 Zynq Ultrascale+ MPSoC SBC Mechanical Dimensions Zynq Ultrascale+ MPSoC SBC PCB size is 72mm x 100 mm x 1.6mm. SBC mechanical dimension is shown below. Measured dimensions are all in MM. Figure 23: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Top View Figure 24: Mechanical dimension of Zynq Ultrascale+ MPSoC SBC - Bottom View REL0.1...

  • Page 84: Figure 25: Mechanical Dimension Of Zynq Ultrascale+ Mpsoc Sbc - Side View

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide Zynq Ultrascale+ MPSoC SBC PCB thickness is 1.60±0.1mm, top side maximum height component is HDMI IN & Out Connectors J11 & J9 (16.40mm) followed by USB Type-A connector J17 (16.20mm) and bottom side maximum height component is Board to Board connectors J21, J22, J26 (7.37mm) followed by Inductor L12 (4.05mm).

  • Page 85: Ordering Information

    The below table provides the standard orderable part numbers for different Zynq Ultrascale+ MPSoC SBC variations. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size SBC configurations. Also if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave.
  • Page 86 Zynq Ultrascale+ MPSoC SBC Hardware User Guide Product Part Number Description Temperature ZU4EV (-1) MPSOC(XCZU4EV-1SFVC784E), 2GB PS DDR4, 1GB PL DDR4, 8GB EMMC, HDMI In/Out, SDI and Wi-Fi – iW-G36S-4EV1-4E002G-E008G-BEF Extended Boot code ZU4EV (-1) MPSOC(XCZU4EV-1SFVC784E), 2GB PS DDR4, iW-G36S-4EV1-4E002G-E008G-BEG Extended 1GB PL DDR4, 8GB EMMC, HDMI In/Out, SFP+ –...
  • Page 87 Zynq Ultrascale+ MPSoC SBC Hardware User Guide Product Part Number Description Temperature ZU2CG (-1) MPSOC(XCZU2CG-1SFVC784I), 2GB PS DDR4, iW-G36S-2CG1-4E002G-E008G-BIF Industrial 8GB EMMC – Boot code REL0.1 iWave Systems Technologies Pvt. Ltd. Page 87 of 88 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 88: Iwave Systems Technologies Pvt. Ltd

    Zynq Ultrascale+ MPSoC SBC Hardware User Guide REL0.1 iWave Systems Technologies Pvt. Ltd. Page 88 of 88 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

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