iWave iW-RainboW-G15M-SM Hardware User's Manual
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iWave iW-RainboW-G15M-SM Hardware User's Manual

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i.MX6 SODIMM SOM Hardware User Guide
iW-RainboW-G15M-SM
i.MX6 SODIMM System On Module
Hardware User Guide
REL 1.2
iWave Systems Technologies Pvt. Ltd.
Page 1 of 56

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Summary of Contents for iWave iW-RainboW-G15M-SM

  • Page 1 SODIMM SOM Hardware User Guide iW-RainboW-G15M-SM i.MX6 SODIMM System On Module Hardware User Guide REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 1 of 56...
  • Page 2 If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copying distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.” REL 1.2 iWave Systems Technologies Pvt.
  • Page 3 (including liability to any person by reason of negligence) will be accepted by iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.

  • Page 4: Table Of Contents

    2.6.19 JTAG Interface ............................. 23 2.6.20 Power Input ..............................24 2.6.21 Reset Button Input ............................24 2.6.22 Power Button Input ............................. 24 i.MX6 Pin Multiplexing on SODIMM Edge ...................... 36 TECHNICAL SPECIFICATION.......................... 47 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 4 of 56...
  • Page 5 Guidelines to insert the SODIMM SOM into Carrier board ................54 Guidelines to remove the SODIMM SOM from Carrier board ................ 54 APPENDIX II ..............................55 i.MX6 SODIMM SOM Development Platform ....................55 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 5 of 56...
  • Page 6 Table 7: Power Input Requirement ..........................47 Table 8: Power Sequence Timing ............................ 48 Table 9: Power Consumption ............................49 Table 10: Environmental Specification ........................... 50 Table 11: Orderable Product Part Numbers ........................52 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 6 of 56...

  • Page 7: Introduction

    This document is the Hardware User Guide for the i.MX6 SODIMM System On Module based on the NXP’s i.MX6 Applications Processor with PMIC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide provides detailed information on the overall design and usage of the i.MX6 SODIMM System On Module from a Hardware Systems perspective.
  • Page 8 SDRAM Synchronous Dynamic Random Access Memory System On Module SODIMM Small Outline Dual in-line Memory Module UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus USB OTG USB On The Go REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 8 of 56...

  • Page 9: Terminlogy Description

    Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes the pull-ups or pull-downs implemented On-SOM. References  i.MX6 Applications Processors Datasheet  i.MX6 Applications Processors Reference Manual REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 9 of 56...

  • Page 10: Important Note

    In this signal, PWM4_OUT is the functionality which we are using and GPIO1_IO05 is the CPU pad name. Note: The above naming is not applicable for other signals which are not connected to CPU. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 10 of 56...

  • Page 11: Architecture And Design

    This section provides detailed information about the i.MX6 SODIMM SOM Features and Hardware architecture with high level block diagram. Also this section provides detailed information about SODIMM edge connector pin assignment and usage. i.MX6 SODIMM SOM Block Diagram iW-RainboW-G15M-SM -i.MX6 SODIMM SOM Block Diagram 10/100/1000 RGMII x 1 Ethernet...

  • Page 12: I.mx6 Sodimm Som Features

     SPI x 1 Port  CAN x 2 Ports  I2C x 2 Ports  PWM x 4 Ports  General Purpose IOs  JTAG x 1 Port REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 12 of 56...
  • Page 13 If Parallel camera is used with 12bit interface, then SPI interface (eCSPI2) cannot be used on SODIMM edge. i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces (including LVDS, HDMI & Parallel RGB) can be supported. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 13 of 56...

  • Page 14: I.mx6 Cpu

    Figure 2: i.MX6 Simplified Block Diagram Note: Please refer the latest i.MX6 Datasheet & Reference Manual from NXP website for Electrical characteristics of i.MX6 Application CPU which may be revised from time to time. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 14 of 56...

  • Page 15: Pmic

    CPU and operating at 3.3V Voltage level. The eMMC flash memory is physically located on bottom side of the SODIMM SOM. The memory size of the eMMC Flash can be expandable. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 15 of 56...

  • Page 16: I.mx6 Sodimm Pcb Edge Connector

    Figure 3: i.MX6 SODIMM PCB Edge Connector Number of Pins - 200 Connector Part - Not Applicable (On Board PCB Edge connector) Mating Connector - 1473005-1 from TE Connectivity REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 16 of 56...

  • Page 17: Boot Setting

    SODIMM SOM boot media is fixed as SPI flash by On-SOM GPIO setting in hardware. Note: Contact iWave if different boot media support is required other than SPI flash. i.MX6 SODIMM SOM supports two boot mode signals on SODIMM Edge Connector. BOOT_MODE is initialized by sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the rising edge of POR_B.

  • Page 18: Gigabit Ethernet

    PCIe connector. Connect two 49.9 Ω resistors between REFCLK- and GND & REFCLK+ and GND. Alternately, Connect a 100 Ω resistor between REFCLK- and REFCLK+. PCIe differential transmitter lines are ac coupled on SOM itself. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 18 of 56...

  • Page 19: Sata Interface

    (eCSPI2_SS3(EIM_D25) of eCSPI2 interface. Note: If more SDIO interfaces are required on SODIMM edge, it can be supported by modifying the CPU IOMUX setting on SODIMM edge pins. Contact iWave for more details. REL 1.2 iWave Systems Technologies Pvt. Ltd.

  • Page 20: Parallel Camera Interface

    Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces (including LVDS, HDMI & Parallel RGB) can be supported. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 20 of 56...

  • Page 21: Hdmi Interface

    For more details, refer SODIMM Edge connector pins 61, 64, 67, 89 & 90 on Table 5. Note: If AUDMUX4 interface is not required on SODIMM edge, the same pins can be configured as uSDHC2 interface. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 21 of 56...

  • Page 22: Uart Interface

    64 Message Buffers. To connect external CAN module to this bus, it is necessary to add transceiver in between. For more details, refer SODIMM Edge connector pins 175, 176, 177 & 178 on Table 5. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 22 of 56...

  • Page 23: I2C Interface

    1149.1 v2001 (JTAG). The SJC module of the processor provides the bridge between external development and test instrumentation and the internal JTAG-accessible debug and test resources. For more details, refer SODIMM Edge connector pins 191, 193, 195, 197 & 199 on Table 5. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 23 of 56...

  • Page 24: Power Input

    CPU power supply is Off, a button press greater in duration than 750ms asserts an output signal to request power from a power IC to power up the i.MX6 CPU. For more details, refer SODIMM Edge connector pin 196 on Table 5. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 24 of 56...

  • Page 25: Table 5: 200-Pin Pcb Edge Connector Pin Assignment

    HDMI_D1M HDMI_D1M/ O, TMDS HDMI differential data lane 1 negative. HDMI_HPD HDMI_HPD/ I, 3.3V CMOS HDMI Hot plug detect. HDMI_D2P HDMI_D2P/ O, TMDS HDMI differential data lane 2 positive. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 25 of 56...
  • Page 26 Note: Same signal is optionally connected to Reset input of On-SOM eMMC through resistor and default not populated. LVDS0_TX0_N LVDS0_TX0_N/ O, 2.5V LVDS LVDS primary channel differential pair 0 negative. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 26 of 56...
  • Page 27 Observability clock 1 output. Power Ground. eCSPI2_SCLK(CSI0_DAT8) CSI0_DAT8/ O, 3.3V CMOS SPI2 clock signal. AUD4_TXD(SD2_DAT2) SD2_DAT2/ O, 3.3V CMOS Audio Transmit data. GPIO6_IO10(NANDF_RB0) NANDF_RB0/ IO, 3.3V CMOS General Purpose Input/Output. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 27 of 56...
  • Page 28 0.01uF AC coupled GPIO6_IO31(EIM_BCLK) EIM_BCLK/ IO, 3.3V General Purpose Input/Output. CMOS SATA_RXM SATA_RXM/ I, DIFF/ SATA0 receive input differential negative. 0.01uF AC coupled VIN_3V3 I, 3.3V Power Supply Voltage. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 28 of 56...
  • Page 29 SD3_DAT0/ IO, 3.3V CMOS SD3 Data0. SD3_CMD SD3_CMD/ IO, 3.3V CMOS SD3 command. SD3_CLK SD3_CLK/ O, 3.3V CMOS SD3 clock. eCSPI2_SS0(CSI0_DAT11) CSI0_DAT11/ O, 3.3V CMOS SPI2 Chip select 2. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 29 of 56...
  • Page 30 O, DIFF PCIe differential receive line positive PCIE_TXM PCIE_TXM/ O, DIFF/ PCIe differential transmit line negative. 0.1uf AC coupled PCIE_RXM PCIE_RXM/ O, DIFF PCIe differential receive line negative. Power Ground. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 30 of 56...
  • Page 31 Parallel LCD data 17 (Red data1). DISP0_DAT18 DISP0_DAT18/ O, 3.3V CMOS Parallel LCD data 18 (Red data2). Power Ground. DISP0_DAT19 DISP0_DAT19/ O, 3.3V CMOS Parallel LCD data 19 (Red data3). REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 31 of 56...
  • Page 32 O, 3.3V CMOS/ Parallel LCD data 5 (Blue data5). DISP0_DAT6 DISP0_DAT6/ O, 3.3V CMOS Parallel LCD data 6 (Blue data6). DISP0_DAT7 DISP0_DAT7/ O, 3.3V CMOS Parallel LCD data 7 (Blue data7). REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 32 of 56...
  • Page 33 Make sure to use this pin in carrier board to select desired boot mode by driving only low if required. 185 GND Power Ground. 186 GND Power Ground. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 33 of 56...
  • Page 34 KEY_COL2 is also connected to Edge connector pin179 through resistor and default populated. 197 JTAG_TCK JTAG_TCK/ I, 3.3V CMOS JTAG Test Clock. 198 GND Power Ground. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 34 of 56...
  • Page 35 JTAG Test Mode Select. 200 VBUS_5V USB_OTG_VBUS/ I, Power 5V USB VBUS Power. E9 & Important Note: Recommended to connect USB_H1_VBUS/ always available 5V power on this pin in carrier board. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 35 of 56...

  • Page 36: I.mx6 Pin Multiplexing On Sodimm Edge

    This table has been prepared by referring NXP’s i.MX6 Applications Processor Reference Manual. Important Note: It is strongly recommended to use the pin function same as selected in the i.MX6 SOIDMM SOM Edge connector for iWave’s BSP reusability and to have compatible SODIMM modules in future for upgradability.
  • Page 37 READY EVENT0 SATA_PHY_T SATA_TXP SATA_PHY_T SATA_TXM SATA SATA_PHY_R SATA_RXP ATA_PHY_RX SATA_RXM USB_OTG_C USB_OTG_C HD_B HD_B GPIO_1 ESAI_RX_CLK WDOG2_B KEY_ROW5 USB_OTG_ID PWM2_OUT GPIO1_IO01 SD1_CD_B GPIO1_IO01 OTG2.0 USB_OTG_D USB_OTG_D USB_OTG_D USB_OTG_D REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 37 of 56...
  • Page 38 IPU1_CSI0_P ARM_EVENT CSI0_PIXCLK GPIO5_IO18 GPIO5_IO18 IXCLK IPU1_CSI0_H ARM_TRACE CSI0_MCLK CCM_CLKO1 GPIO5_IO19 GPIO5_IO19 SYNC _CTL IPU1_CSI0_V EIM_DATA0 ARM_TRACE CSI0_VSYNC GPIO5_IO21 GPIO5_IO21 SYNC CSI0_DATA_ IPU1_CSI0_D EIM_DATA0 ARM_TRACE GPIO5_IO20 GPIO5_IO20 ATA_EN _CLK REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 38 of 56...
  • Page 39 GPIO1_IO11 SD2_CLK SD2_CLK ECSPI5_SCLK KEY_COL5 AUD4_RXFS GPIO1_IO10 GPIO1_IO10 LVDS0_TX0_ LVDS0_DATA LVDS0_TX0_ LVDS0_DATA LVDS0_TX1_ LVDS0_DATA LVDS0_TX1_ LVDS0_DATA LVDS0_TX2_ LVDS0_DATA LVDS LVDS0_TX2_ LVDS0_DATA LVDS0_TX3_ LVDS0_DATA LVDS0_TX3_ LVDS0_DATA LVDS0_CLK_ LVDS0_CLK_ LVDS0_CLK_ LVDS0_CLK_ REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 39 of 56...
  • Page 40 DATA13 DISP0_DAT1 IPU1_DISP0_ IPU2_DISP0_ AUD5_RXC GPIO5_IO08 GPIO5_IO08 DATA14 DATA14 DISP0_DAT1 IPU1_DISP0_ IPU2_DISP0_ ECSPI1_SS1 ECSPI2_SS1 GPIO5_IO09 GPIO5_IO09 DATA15 DATA15 DISP0_DAT1 IPU1_DISP0_ IPU2_DISP0_ ECSPI2_MOS SDMA_EXT_ AUD5_TXC GPIO5_IO10 GPIO5_IO10 DATA16 DATA16 EVENT0 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 40 of 56...
  • Page 41 GPIO5_IO17 GPIO5_IO17 DATA23 DATA23 DI0_DISP_CL IPU1_DI0_DI IPU2_DI0_DI GPIO4_IO16 GPIO4_IO16 SP_CLK SP_CLK IPU1_DI0_PI IPU2_DI0_PI DI0_PIN2 AUD6_TXD GPIO4_IO18 GPIO4_IO18 IPU1_DI0_PI IPU2_DI0_PI DI0_PIN3 AUD6_TXFS GPIO4_IO19 GPIO4_IO19 IPU1_DI0_PI IPU2_DI0_PI DI0_PIN15 AUD6_TXC GPIO4_IO17 GPIO4_IO17 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 41 of 56...
  • Page 42 ARM_TRACE CSI0_DAT11 AUD3_RXFS ECSPI2_SS0 GPIO5_IO29 GPIO5_IO29 ATA11 DATA IPU1_DI1_PI SRC_BOOT_ EPDC_DATA EIM_LBA EIM_LBA ECSPI2_SS1 GPIO2_IO27 EIM_LBA CFG26 EIM_DATA2 UART3_TX_ UART1_DTR EIM_D24 ECSPI4_SS2 ECSPI1_SS2 ECSPI2_SS2 GPIO3_IO24 AUD5_RXFS EPDC_SDCE7 GPIO3_IO24 DATA REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 42 of 56...
  • Page 43 GPIO1_IO06 USB_OTG_P ESAI_TX5_RX XTALOSC_RE FLEXCAN1_R UART2_RX_ SPDIF_SR_CL GPIO_8 EPIT2_OUT GPIO1_IO08 WR_CTL_WA I2C4_SDA GPIO1_IO08 F_CLK_32K DATA CAN1 ESAI_TX4_RX FLEXCAN1_T UART2_TX_ USB_OTG_H GPIO_7 ECSPI5_RDY EPIT1_OUT GPIO1_IO07 SPDIF_LOCK I2C4_SCL GPIO1_IO07 DATA OST_MODE REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 43 of 56...
  • Page 44 WDOG1_B GPIO1_IO19 GPIO1_IO19 ET_B_DEB GPT_CAPTU SD1_DAT1 SD1_DATA1 ECSPI5_SS0 PWM3_OUT GPIO1_IO17 GPIO1_IO17 ECSPI5_MOS GPT_COMPA SD1_CMD SD1_CMD PWM4_OUT GPIO1_IO18 GPIO1_IO18 JTAG_TDI JTAG_TDI JTAG_TDO JTAG_TDO JTAG JTAG_TMS JTAG_TMS JTAG_TRSTB JTAG_TRSTB JTAG_TCK JTAG_TCK REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 44 of 56...
  • Page 45 GPIO2_IO06 GPIO2_IO06 NAND_CE0_ NANDF_CS0 GPIO6_IO11 GPIO6_IO11 XTALOSC_OS ECSPI5_SCLK SD1_CLK SD1_CLK C32K_32K_O GPT_CLKIN GPIO1_IO20 GPIO1_IO20 NANDF_CLE NAND_CLE IPU2_SISG4 GPIO6_IO07 GPIO6_IO07 ENET_1588_ GPIO_19 KEY_COL5 EVENT0_OU SPDIF_OUT CCM_CLKO1 ECSPI1_RDY GPIO4_IO05 ENET_TX_ER GPIO4_IO05 REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 45 of 56...
  • Page 46 Note: *Purple Coloured ALT functions are not supported in i.MX6 Quad and Dual core CPUs. * Green Coloured ALT functions are not supported in i.MX6 Solo and Duallite CPUs. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 46 of 56...

  • Page 47: Technical Specification

    ³ This power is used as supply voltage to both USB OTG and USB HOST1 block of i.MX6 CPU. It is recommended to connect always available 5V power to this pin from carrier board. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 47 of 56...

  • Page 48: Power Input Sequencing

    Important Note: All the carrier board power supplies should be powered ON only after the SOM is powered ON completely. Otherwise it can cause internal latch-up and malfunctions/bootup issues due to reverse current flows. REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 48 of 56...

  • Page 49: Power Consumption

    500uA provided ¹ Power consumption measurements have been done in iWave’s i.MX6 Quad CPU based SODIMM SOM with iWave’s Generic SODIMM Carrier board running iWave’s Linux3.14.38 BSP (iW-PREPZ-DF-01-R2.0-REL1.0-Linux3.14.38). ² Only i.MX6 CPU related power management is implemented in the BSP for low power modes.

  • Page 50: Environmental Characteristics

    3.2.3 Electrostatic Discharge iWave’s i.MX6 SODIMM SOM is sensitive to electro static discharge and so high voltages caused by static electricity could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or use the SOM except at an electrostatic free workstation.

  • Page 51: Mechanical Characteristics

    CPU (2.10mm) and bottom side maximum height component is Capacitor (1.25mm) followed by DDR3 SDRAM (1.0mm). Please refer the below figure which gives height details of the i.MX6 SODIMM SOM. Figure 6: Mechanical dimension of i.MX6 SODIMM SOM - Side View REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 51 of 56...

  • Page 52: Ordering Information

    SODIMM SOM is available in different variations. The below table provides the standard orderable part numbers for different i.MX6 SODIMM SOM variations. Please contact iWave for orderable part number of higher RAM memory size or Flash memory size configurations. Also if the desired part number is not listed in below table or if any custom configuration part number is required, please contact iWave.
  • Page 53 Industrial code Important Note: Some of the above mentioned Part Number is subject to MOQ purchase. Please contact iWave for further details. Note: For SOM identification purpose, Product Part Number and SOM Unique Serial Number are pasted as Label with Barcode readable format on SOM.

  • Page 54: Guidelines To Insert The Sodimm Som Into Carrier Board

    When you remove the module, pull away the retention clips (A) on each side of the memory module.  The module pops up. Grasp the edge of the module (B) and gently pull the module out of the connector. Figure 8: Module Removal Procedure REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 54 of 56...

  • Page 55: I.mx6 Sodimm Som Development Platform

    Systems supports iW-RainboW-G15D-SM – i.MX6 SODIMM Development Platform which is targeted for quick validation of i.MX6 CPU with i.MX6 SODIMM SOM. iWave's i.MX6 SODIMM Development Board incorporates i.MX6 SODIMM SOM and SODIMM Carrier board for complete validation of i.MX6 SODIMM SOM functionality with complete BSP support.
  • Page 56 SODIMM SOM Hardware User Guide REL 1.2 iWave Systems Technologies Pvt. Ltd. Page 56 of 56...

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