Table of Contents
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Power On SEQ
5
DD_ON
3.3V
5V
D
0.95V
1.8V
RSMRST#
PWR_BTN#
SUSC#
DDR_V
VTT_MEM
SUSB#
3.3VS
C
1.5VS
1.8VS
5VS
SYS_RST#
EC_PWRGD
0.95V_EN
0.95VS
B
APU_VCORE_ON
APU_VRM_PWRGD_EC
VDDCR_NB
VDDCR_CPU
DELAY_VCORE_ON
SYS_PWROK
SB_PWRGD
APU_PWRGD
A
LDT_RST#
5
4
3
POWER ON SEQUENCE
1.675ms
2.42ms
2.42ms
3.17ms
50.93ms
24.16msms
16.13ms
1.829ms
2.967ms
0us (SUSC# to SUSB#)
404us
1.94ms
3.44ms
27.46ms
5.28ms (DD_ON to SYS_RST#)
71.6ms (SYS_RST# to EC_PWRGD)
36.288ms (SUSB# to 0.95V_EN)
2.9947ms (0.95_EN to 0.95VS)
36.288ms (SUSB# to 0.95V_EN)
23.137ms
23.137ms
41us (VDDCR_NB to VDDCR_CPU)
24.42ms (EC Delay SUSB# 50 ms; Vcore Power)
24.64ms
(APU_VRM_PWRGD_EC
24.65ms
(APU_VRM_PWRGD_EC
111.35ms (SYS_PWRGD to APU_PWRGD)
5.81ms (APU_PWRGD to LDT_RST#)
4
3
2
1
to
SYS_PWRGD)
to
SB_PWRGD)
DMFWP!DP/!!
Title
Title
Title
[28]POWER ON SEQUENCE
[28]POWER ON SEQUENCE
[28]POWER ON SEQUENCE
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W54K0-D02
6-71-W54K0-D02
6-71-W54K0-D02
Custom
Custom
Custom
Date:
Date:
Date:
Thursday, September 12, 2013
Thursday, September 12, 2013
Thursday, September 12, 2013
Sheet
Sheet
Sheet
28
28
28
o f
o f
o f
2
1
Schematic Diagrams
D
Sheet 28 of 28
Power On SEQ
C
B
A
R e v
R e v
R e v
D02
D02
D02
28
28
28
Power On SEQ B - 29
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